GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,50 @@
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# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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if TARGET_PDU001
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config SYS_BOARD
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default "pdu001"
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config SYS_VENDOR
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default "eets"
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config SYS_SOC
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default "am33xx"
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config SYS_CONFIG_NAME
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default "pdu001"
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choice
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prompt "State of Run LED"
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default RUN_LED_RED
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help
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The PDU001 has a bi-color (red/green) LED labeled 'Run' which
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can be used to indicate the operating state of the board. By
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default it will be lit red by U-Boot. Later in the start-up
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process it can be changed to green (or heartbeat or anything else)
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by the kernel or some other software.
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config RUN_LED_RED
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bool
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prompt "Red"
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help
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Lit Run LED red.
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config RUN_LED_GREEN
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bool
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prompt "Green"
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help
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Lit Run LED green.
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config RUN_LED_OFF
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bool
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prompt "Off"
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help
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Do not lit Run LED.
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endchoice
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endif
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@@ -0,0 +1,6 @@
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PDU001 BOARD
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M: Felix Brack <fb@ltec.ch>
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S: Maintained
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F: board/eets/pdu001/
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F: include/configs/pdu001.h
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F: configs/am335x_pdu001_defconfig
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@@ -0,0 +1,13 @@
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#
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# Makefile
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#
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# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
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obj-y := mux.o
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endif
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obj-y += board.o
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@@ -0,0 +1,35 @@
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# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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Summary
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=======
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This document covers the PDU001 target.
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Hardware
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========
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The PDU-001 (Processor and Display Unit) is a plugin card for 19" racks. It is
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manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2
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SOM from bytes at work (https://www.bytesatwork.ch) which in turn is based on
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AM3352 SOC from TI (http://www.ti.com).
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Customization
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=============
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As usual the console serial interface is set by CONFIG_CONS_INDEX. Best choice
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is 4 here since UART3 is wired to the connector K2.
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The Run LED on the PDU-001 can be turned on red by setting CONFIG_RUN_LED_RED
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or green by setting CONFIG_RUN_LED_GREEN. Setting CONFIG_RUN_LED_OFF will turn
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off the Run LED.
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Booting
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=======
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The system boots from either eMMC or SD card cage. It will first try to boot
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from the SD card cage. If this fails (missing or unbootable SD card) it will
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try to boot from the internal eMMC. The root file system is always expected to
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be located in the second partition of the device (eMMC or SD card) that pro-
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vided the boot loader.
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@@ -0,0 +1,275 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for EETS PDU001 board
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*
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* Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <spl.h>
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#include <i2c.h>
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#include <watchdog.h>
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#include <debug_uart.h>
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#include <dm/ofnode.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define I2C_ADDR_NODE_ID 0x50
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#define I2C_REG_NODE_ID_BASE 0xfa
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#define NODE_ID_BYTE_COUNT 6
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#define I2C_ADDR_LEDS 0x60
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#define I2C_REG_RUN_LED 0x06
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#define RUN_LED_OFF 0x0
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#define RUN_LED_RED 0x1
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#define RUN_LED_GREEN (0x1 << 2)
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#define VDD_MPU_REGULATOR "regulator@2"
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#define VDD_CORE_REGULATOR "regulator@3"
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#define DEFAULT_CORE_VOLTAGE 1137500
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/*
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* boot device save register
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* -------------------------
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* The boot device can be quired by 'spl_boot_device()' in
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* 'am33xx_spl_board_init'. However it can't be saved in the u-boot
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* environment here. In turn 'spl_boot_device' can't be called in
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* 'board_late_init' which allows writing to u-boot environment.
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* To get the boot device from 'am33xx_spl_board_init' to
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* 'board_late_init' we therefore use a scratch register from the RTC.
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*/
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#define CONFIG_SYS_RTC_SCRATCH0 0x60
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#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
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#ifdef CONFIG_SPL_BUILD
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static void save_boot_device(void)
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{
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*((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device();
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}
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#endif
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u32 boot_device(void)
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{
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return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER));
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}
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/* Store the boot device in the environment variable 'boot_device' */
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static void env_set_boot_device(void)
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{
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switch (boot_device()) {
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case BOOT_DEVICE_MMC1: {
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env_set("boot_device", "emmc");
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break;
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}
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case BOOT_DEVICE_MMC2: {
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env_set("boot_device", "sdcard");
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break;
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}
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default: {
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env_set("boot_device", "unknown");
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break;
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}
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}
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}
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static void set_run_led(struct udevice *dev)
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{
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int val = RUN_LED_OFF;
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if (IS_ENABLED(CONFIG_RUN_LED_RED))
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val = RUN_LED_RED;
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else if (IS_ENABLED(CONFIG_RUN_LED_GREEN))
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val = RUN_LED_GREEN;
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dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val);
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}
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/* Set 'serial#' to the EUI-48 value of board node ID chip */
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static void env_set_serial(struct udevice *dev)
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{
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int val;
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char serial[2 * NODE_ID_BYTE_COUNT + 1];
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int n;
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for (n = 0; n < sizeof(serial); n += 2) {
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val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2);
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sprintf(serial + n, "%02X", val);
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}
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serial[2 * NODE_ID_BYTE_COUNT] = '\0';
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env_set("serial#", serial);
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}
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static void set_mpu_and_core_voltage(void)
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{
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int mpu_vdd;
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int sil_rev;
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struct udevice *dev;
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struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/*
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* The PDU001 (more precisely the computing module m2) uses a
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* TPS65910 PMIC. For all MPU frequencies we support we use a CORE
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* voltage of 1.1375V. For MPU voltage we need to switch based on
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* the frequency we are running at.
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*/
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/*
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* Depending on MPU clock and PG we will need a different VDD
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* to drive at that speed.
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*/
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sil_rev = readl(&cdev->deviceid) >> 28;
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mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m);
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/* first update the MPU voltage */
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if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) {
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if (regulator_set_value(dev, mpu_vdd))
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debug("failed to set MPU voltage\n");
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} else {
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debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR);
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}
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/* second update the CORE voltage */
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if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) {
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if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE))
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debug("failed to set CORE voltage\n");
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} else {
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debug("invalid CORE voltage ragulator %s\n",
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VDD_CORE_REGULATOR);
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}
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}
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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static const struct ddr_data ddr2_data = {
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.datardsratio0 = MT47H128M16RT25E_RD_DQS,
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.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
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.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr2_cmd_ctrl_data = {
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.cmd0csratio = MT47H128M16RT25E_RATIO,
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.cmd1csratio = MT47H128M16RT25E_RATIO,
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.cmd2csratio = MT47H128M16RT25E_RATIO,
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};
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static const struct emif_regs ddr2_emif_reg_data = {
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.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
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.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
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.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
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.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
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.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
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.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
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};
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#define OSC (V_OSCK / 1000000)
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const struct dpll_params dpll_ddr = {
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266, OSC - 1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_ddr_evm_sk = {
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303, OSC - 1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_ddr_bone_black = {
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400, OSC - 1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* Get the frequency */
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dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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/* Set CORE Frequencies to OPP100 */
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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/* Set MPU Frequency to what we detected now that voltages are set */
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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/* save boot device for later use by 'board_late_init' */
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save_boot_device();
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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enable_i2c0_pin_mux();
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return &dpll_ddr;
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}
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void set_mux_conf_regs(void)
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{
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/* done first by the ROM and afterwards by the pin controller driver */
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enable_i2c0_pin_mux();
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}
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const struct ctrl_ioregs ioregs = {
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.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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};
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void sdram_init(void)
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{
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config_ddr(266, &ioregs, &ddr2_data,
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&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
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}
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#ifdef CONFIG_DEBUG_UART
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void board_debug_uart_init(void)
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{
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/* done by pin controller driver if not debugging */
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enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
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}
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#endif
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/*
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* Basic board specific setup. Pinmux has been handled already.
|
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*/
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int board_init(void)
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{
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#ifdef CONFIG_HW_WATCHDOG
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hw_watchdog_init();
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#endif
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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|
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#ifdef CONFIG_BOARD_LATE_INIT
|
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int board_late_init(void)
|
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{
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struct udevice *dev;
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|
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set_mpu_and_core_voltage();
|
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env_set_boot_device();
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/* second I2C bus connects to node ID and front panel LED chip */
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if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev))
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set_run_led(dev);
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if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev))
|
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env_set_serial(dev);
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|
||||
return 0;
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||||
}
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#endif
|
||||
@@ -0,0 +1,37 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* board.h
|
||||
*
|
||||
* EETS GmbH PDU001 board information header
|
||||
*
|
||||
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
/*
|
||||
* We have two pin mux functions that must exist. First we need I2C0 to
|
||||
* access the TPS65910 PMIC located on the M2 computing module.
|
||||
* Second, if we want low-level debugging or a early UART (ie. before the
|
||||
* pin controller driver is running), we need one of the UART ports UART0 to
|
||||
* UART5 (usually UART3 since it is wired to K2).
|
||||
* In case of I2C0 access we explicitly don't rely on the the ROM but we could
|
||||
* do so as we use the primary mode (mode 0) for I2C0.
|
||||
* All other multiplexing and pin configuration is done by the DT once it
|
||||
* gets parsed by the pin controller driver.
|
||||
* However we relay on the ROM to configure the pins of MMC0 (eMMC) as well
|
||||
* as MMC1 (microSD card-cage) since these are our boot devices.
|
||||
*/
|
||||
void enable_uart0_pin_mux(void);
|
||||
void enable_uart1_pin_mux(void);
|
||||
void enable_uart2_pin_mux(void);
|
||||
void enable_uart3_pin_mux(void);
|
||||
void enable_uart4_pin_mux(void);
|
||||
void enable_uart5_pin_mux(void);
|
||||
void enable_uart_pin_mux(u32 addr);
|
||||
void enable_i2c0_pin_mux(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,119 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* mux.c
|
||||
*
|
||||
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/io.h>
|
||||
#include "board.h"
|
||||
|
||||
static struct module_pin_mux uart0_pin_mux[] = {
|
||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart1_pin_mux[] = {
|
||||
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
|
||||
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart2_pin_mux[] = {
|
||||
{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
|
||||
{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart3_pin_mux[] = {
|
||||
{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart4_pin_mux[] = {
|
||||
{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
|
||||
{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart5_pin_mux[] = {
|
||||
{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
|
||||
{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart1_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart1_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart2_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart2_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart3_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart3_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart4_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart4_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart5_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart5_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart_pin_mux(u32 addr)
|
||||
{
|
||||
switch (addr) {
|
||||
case CONFIG_SYS_NS16550_COM1:
|
||||
enable_uart0_pin_mux();
|
||||
break;
|
||||
case CONFIG_SYS_NS16550_COM2:
|
||||
enable_uart1_pin_mux();
|
||||
break;
|
||||
case CONFIG_SYS_NS16550_COM3:
|
||||
enable_uart2_pin_mux();
|
||||
break;
|
||||
case CONFIG_SYS_NS16550_COM4:
|
||||
enable_uart3_pin_mux();
|
||||
break;
|
||||
case CONFIG_SYS_NS16550_COM5:
|
||||
enable_uart4_pin_mux();
|
||||
break;
|
||||
case CONFIG_SYS_NS16550_COM6:
|
||||
enable_uart5_pin_mux();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void enable_i2c0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
}
|
||||
Reference in New Issue
Block a user