GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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# Copyright (C) 2016 Amarula Solutions B.V.
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obj-y := board.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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@@ -0,0 +1,121 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <env.h>
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#include <init.h>
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#include <mmc.h>
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#include <asm/arch/sys_proto.h>
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#include <watchdog.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_ENV_IS_IN_MMC
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static void mmc_late_init(void)
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{
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char cmd[32];
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char mmcblk[32];
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u32 dev_no = mmc_get_env_dev();
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env_set_ulong("mmcdev", dev_no);
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/* Set mmcblk env */
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sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
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env_set("mmcroot", mmcblk);
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sprintf(cmd, "mmc dev %d", dev_no);
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run_command(cmd, 0);
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}
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#endif
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static void setenv_fdt_file(void)
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{
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const char *cmp_dtb = CONFIG_DEFAULT_DEVICE_TREE;
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if (!strcmp(cmp_dtb, "imx6q-icore")) {
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if (is_mx6dq())
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env_set("fdt_file", "imx6q-icore.dtb");
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else if (is_mx6dl() || is_mx6solo())
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env_set("fdt_file", "imx6dl-icore.dtb");
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} else if (!strcmp(cmp_dtb, "imx6q-icore-mipi")) {
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if (is_mx6dq())
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env_set("fdt_file", "imx6q-icore-mipi.dtb");
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else if (is_mx6dl() || is_mx6solo())
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env_set("fdt_file", "imx6dl-icore-mipi.dtb");
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} else if (!strcmp(cmp_dtb, "imx6q-icore-rqs")) {
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if (is_mx6dq())
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env_set("fdt_file", "imx6q-icore-rqs.dtb");
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else if (is_mx6dl() || is_mx6solo())
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env_set("fdt_file", "imx6dl-icore-rqs.dtb");
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} else if (!strcmp(cmp_dtb, "imx6ul-geam"))
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env_set("fdt_file", "imx6ul-geam.dtb");
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else if (!strcmp(cmp_dtb, "imx6ul-isiot-emmc"))
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env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
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else if (!strcmp(cmp_dtb, "imx6ul-isiot-nand"))
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env_set("fdt_file", "imx6ul-isiot-nand.dtb");
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}
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int board_late_init(void)
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{
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switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
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IMX6_BMODE_SHIFT) {
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case IMX6_BMODE_SD:
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case IMX6_BMODE_ESD:
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case IMX6_BMODE_MMC:
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case IMX6_BMODE_EMMC:
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#ifdef CONFIG_ENV_IS_IN_MMC
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mmc_late_init();
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#endif
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env_set("modeboot", "mmcboot");
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break;
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case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
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env_set("modeboot", "nandboot");
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break;
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default:
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env_set("modeboot", "");
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break;
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}
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if (is_mx6ul())
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env_set("console", "ttymxc0");
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else
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env_set("console", "ttymxc3");
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setenv_fdt_file();
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#ifdef CONFIG_HW_WATCHDOG
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hw_watchdog_init();
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#endif
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_NAND_MXS
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setup_gpmi_nand();
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#endif
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#ifdef CONFIG_VIDEO_IPUV3
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setup_display();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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@@ -0,0 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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void setup_gpmi_nand(void);
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void setup_display(void);
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#endif /* _BOARD_H_ */
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@@ -0,0 +1,432 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <serial.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/sizes.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/video.h>
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const uart_pads[] = {
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#ifdef CONFIG_MX6QDL
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IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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#elif CONFIG_MX6UL
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IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
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#endif
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};
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
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return 0;
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else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
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return 0;
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else if (is_mx6dq() && !strcmp(name, "imx6q-icore-mipi"))
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return 0;
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else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
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return 0;
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else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
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return 0;
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else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-mipi"))
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return 0;
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else
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return -1;
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}
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#endif
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#ifdef CONFIG_ENV_IS_IN_MMC
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void board_boot_order(u32 *spl_boot_list)
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{
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u32 bmode = imx6_src_get_boot_mode();
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u8 boot_dev = BOOT_DEVICE_MMC1;
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switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
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case IMX6_BMODE_SD:
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case IMX6_BMODE_ESD:
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/* SD/eSD - BOOT_DEVICE_MMC1 */
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break;
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case IMX6_BMODE_MMC:
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case IMX6_BMODE_EMMC:
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/* MMC/eMMC */
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boot_dev = BOOT_DEVICE_MMC2;
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break;
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default:
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/* Default - BOOT_DEVICE_MMC1 */
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printf("Wrong board boot order\n");
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break;
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}
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spl_boot_list[0] = boot_dev;
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}
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#endif
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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return 0;
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}
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#endif
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#ifdef CONFIG_MX6QDL
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/*
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* Driving strength:
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* 0x30 == 40 Ohm
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* 0x28 == 48 Ohm
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*/
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#define IMX6DQ_DRIVE_STRENGTH 0x30
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#define IMX6SDL_DRIVE_STRENGTH 0x28
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/* configure MX6Q/DUAL mmdc DDR io registers */
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static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
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.dram_cas = IMX6DQ_DRIVE_STRENGTH,
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.dram_ras = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_reset = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
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};
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/* configure MX6Q/DUAL mmdc GRP io registers */
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static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_addds = IMX6DQ_DRIVE_STRENGTH,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
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.grp_ddr_type = 0x000c0000,
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};
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/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_cas = IMX6SDL_DRIVE_STRENGTH,
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.dram_ras = IMX6SDL_DRIVE_STRENGTH,
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.dram_reset = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
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};
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/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
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struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = IMX6SDL_DRIVE_STRENGTH,
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.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
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};
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/* mt41j256 */
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static struct mx6_ddr3_cfg mt41j256 = {
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.mem_speed = 1066,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 13,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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.SRT = 0,
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};
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static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
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.p0_mpwldectrl0 = 0x000E0009,
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.p0_mpwldectrl1 = 0x0018000E,
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.p1_mpwldectrl0 = 0x00000007,
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.p1_mpwldectrl1 = 0x00000000,
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.p0_mpdgctrl0 = 0x43280334,
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.p0_mpdgctrl1 = 0x031C0314,
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.p1_mpdgctrl0 = 0x4318031C,
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.p1_mpdgctrl1 = 0x030C0258,
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.p0_mprddlctl = 0x3E343A40,
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.p1_mprddlctl = 0x383C3844,
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.p0_mpwrdlctl = 0x40404440,
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.p1_mpwrdlctl = 0x4C3E4446,
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};
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/* DDR 64bit */
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static struct mx6_ddr_sysinfo mem_q = {
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.ddr_type = DDR_TYPE_DDR3,
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.dsize = 2,
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.cs1_mirror = 0,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32,
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.ncs = 1,
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.bi_on = 1,
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.rtt_nom = 2,
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.rtt_wr = 2,
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.ralat = 5,
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.walat = 0,
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.mif3_mode = 3,
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.rst_to_cke = 0x23,
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.sde_to_rst = 0x10,
|
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};
|
||||
|
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static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
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.p0_mpwldectrl0 = 0x001F0024,
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.p0_mpwldectrl1 = 0x00110018,
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.p1_mpwldectrl0 = 0x001F0024,
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.p1_mpwldectrl1 = 0x00110018,
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.p0_mpdgctrl0 = 0x4230022C,
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.p0_mpdgctrl1 = 0x02180220,
|
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.p1_mpdgctrl0 = 0x42440248,
|
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.p1_mpdgctrl1 = 0x02300238,
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||||
.p0_mprddlctl = 0x44444A48,
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.p1_mprddlctl = 0x46484A42,
|
||||
.p0_mpwrdlctl = 0x38383234,
|
||||
.p1_mpwrdlctl = 0x3C34362E,
|
||||
};
|
||||
|
||||
/* DDR 64bit 1GB */
|
||||
static struct mx6_ddr_sysinfo mem_dl = {
|
||||
.dsize = 2,
|
||||
.cs1_mirror = 0,
|
||||
/* config for full 4GB range so that get_mem_size() works */
|
||||
.cs_density = 32,
|
||||
.ncs = 1,
|
||||
.bi_on = 1,
|
||||
.rtt_nom = 1,
|
||||
.rtt_wr = 1,
|
||||
.ralat = 5,
|
||||
.walat = 0,
|
||||
.mif3_mode = 3,
|
||||
.rst_to_cke = 0x23,
|
||||
.sde_to_rst = 0x10,
|
||||
};
|
||||
|
||||
/* DDR 32bit 512MB */
|
||||
static struct mx6_ddr_sysinfo mem_s = {
|
||||
.dsize = 1,
|
||||
.cs1_mirror = 0,
|
||||
/* config for full 4GB range so that get_mem_size() works */
|
||||
.cs_density = 32,
|
||||
.ncs = 1,
|
||||
.bi_on = 1,
|
||||
.rtt_nom = 1,
|
||||
.rtt_wr = 1,
|
||||
.ralat = 5,
|
||||
.walat = 0,
|
||||
.mif3_mode = 3,
|
||||
.rst_to_cke = 0x23,
|
||||
.sde_to_rst = 0x10,
|
||||
};
|
||||
#endif /* CONFIG_MX6QDL */
|
||||
|
||||
#ifdef CONFIG_MX6UL
|
||||
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
|
||||
.grp_addds = 0x00000030,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
.grp_b0ds = 0x00000030,
|
||||
.grp_ctlds = 0x00000030,
|
||||
.grp_b1ds = 0x00000030,
|
||||
.grp_ddrpke = 0x00000000,
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_ddr_type = 0x000c0000,
|
||||
};
|
||||
|
||||
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
|
||||
.dram_dqm0 = 0x00000030,
|
||||
.dram_dqm1 = 0x00000030,
|
||||
.dram_ras = 0x00000030,
|
||||
.dram_cas = 0x00000030,
|
||||
.dram_odt0 = 0x00000030,
|
||||
.dram_odt1 = 0x00000030,
|
||||
.dram_sdba2 = 0x00000000,
|
||||
.dram_sdclk_0 = 0x00000008,
|
||||
.dram_sdqs0 = 0x00000038,
|
||||
.dram_sdqs1 = 0x00000030,
|
||||
.dram_reset = 0x00000030,
|
||||
};
|
||||
|
||||
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
||||
.p0_mpwldectrl0 = 0x00070007,
|
||||
.p0_mpdgctrl0 = 0x41490145,
|
||||
.p0_mprddlctl = 0x40404546,
|
||||
.p0_mpwrdlctl = 0x4040524D,
|
||||
};
|
||||
|
||||
struct mx6_ddr_sysinfo ddr_sysinfo = {
|
||||
.dsize = 0,
|
||||
.cs_density = 20,
|
||||
.ncs = 1,
|
||||
.cs1_mirror = 0,
|
||||
.rtt_wr = 2,
|
||||
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
|
||||
.walat = 1, /* Write additional latency */
|
||||
.ralat = 5, /* Read additional latency */
|
||||
.mif3_mode = 3, /* Command prediction working mode */
|
||||
.bi_on = 1, /* Bank interleaving enabled */
|
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
||||
.ddr_type = DDR_TYPE_DDR3,
|
||||
};
|
||||
|
||||
static struct mx6_ddr3_cfg mem_ddr = {
|
||||
.mem_speed = 800,
|
||||
.density = 4,
|
||||
.width = 16,
|
||||
.banks = 8,
|
||||
#ifdef TARGET_MX6UL_ISIOT
|
||||
.rowaddr = 15,
|
||||
#else
|
||||
.rowaddr = 13,
|
||||
#endif
|
||||
.coladdr = 10,
|
||||
.pagesz = 2,
|
||||
.trcd = 1375,
|
||||
.trcmin = 4875,
|
||||
.trasmin = 3500,
|
||||
};
|
||||
#endif /* CONFIG_MX6UL */
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
#ifdef CONFIG_MX6QDL
|
||||
writel(0x00003F3F, &ccm->CCGR0);
|
||||
writel(0x0030FC00, &ccm->CCGR1);
|
||||
writel(0x000FC000, &ccm->CCGR2);
|
||||
writel(0x3F300000, &ccm->CCGR3);
|
||||
writel(0xFF00F300, &ccm->CCGR4);
|
||||
writel(0x0F0000C3, &ccm->CCGR5);
|
||||
writel(0x000003CC, &ccm->CCGR6);
|
||||
#elif CONFIG_MX6UL
|
||||
writel(0x00c03f3f, &ccm->CCGR0);
|
||||
writel(0xfcffff00, &ccm->CCGR1);
|
||||
writel(0x0cffffcc, &ccm->CCGR2);
|
||||
writel(0x3f3c3030, &ccm->CCGR3);
|
||||
writel(0xff00fffc, &ccm->CCGR4);
|
||||
writel(0x033f30ff, &ccm->CCGR5);
|
||||
writel(0x00c00fff, &ccm->CCGR6);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
#ifdef CONFIG_MX6QDL
|
||||
if (is_mx6solo()) {
|
||||
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
||||
mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
|
||||
} else if (is_mx6dl()) {
|
||||
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
||||
mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
|
||||
} else if (is_mx6dq()) {
|
||||
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
|
||||
mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
|
||||
}
|
||||
#elif CONFIG_MX6UL
|
||||
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
||||
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
||||
#endif
|
||||
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
ccgr_init();
|
||||
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
if (!(is_mx6ul()))
|
||||
gpr_init();
|
||||
|
||||
/* iomux */
|
||||
SETUP_IOMUX_PADS(uart_pads);
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_MX6Q_ENGICAM
|
||||
|
||||
config SYS_BOARD
|
||||
default "imx6q"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "engicam"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "imx6-engicam"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,29 @@
|
||||
MX6Q_ENGICAM BOARD
|
||||
M: Jagan Teki <jagan@amarulasolutions.com>
|
||||
S: Maintained
|
||||
F: board/engicam/imx6q
|
||||
F: include/configs/imx6-engicam.h
|
||||
F: configs/imx6qdl_icore_mmc_defconfig
|
||||
F: configs/imx6q_icore_nand_defconfig
|
||||
F: configs/imx6dl_icore_nand_defconfig
|
||||
F: configs/imx6qdl_icore_rqs_defconfig
|
||||
F: configs/imx6qdl_icore_mipi_defconfig
|
||||
F: configs/imx6qdl_icore_nand_defconfig
|
||||
F: arch/arm/dts/imx6qdl.dtsi
|
||||
F: arch/arm/dts/imx6qdl-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6qdl-icore.dtsi
|
||||
F: arch/arm/dts/imx6qdl-icore-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6q-icore.dts
|
||||
F: arch/arm/dts/imx6q-icore-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6dl-icore.dts
|
||||
F: arch/arm/dts/imx6dl-icore-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
|
||||
F: arch/arm/dts/imx6qdl-icore-rqs-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6q-icore-rqs.dts
|
||||
F: arch/arm/dts/imx6q-icore-rqs-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6dl-icore-rqs.dts
|
||||
F: arch/arm/dts/imx6dl-icore-rqs-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6dl-icore-mipi.dts
|
||||
F: arch/arm/dts/imx6dl-icore-mipi-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6q-icore-mipi.dts
|
||||
F: arch/arm/dts/imx6q-icore-mipi-u-boot.dtsi
|
||||
@@ -0,0 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
# Copyright (C) 2016 Amarula Solutions B.V.
|
||||
|
||||
obj-y := imx6q.o
|
||||
@@ -0,0 +1,33 @@
|
||||
Hsow to use U-Boot on Engicam i.CoreM6 (RQS) Solo/DualLite/Quad/Dual Starter Kit:
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
$ make mrproper
|
||||
|
||||
- Configure U-Boot for Engicam i.CoreM6 Quad/Duali/Solo/DualLite:
|
||||
$ make imx6qdl_icore_mmc_defconfig
|
||||
|
||||
- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Duali/Solo/DualLite:
|
||||
$ make imx6qdl_icore_rqs_defconfig
|
||||
|
||||
- Build U-Boot
|
||||
$ make
|
||||
|
||||
This will generate the SPL image called SPL and the u-boot-dtb.img.
|
||||
|
||||
- Flash the SPL image into the micro SD card:
|
||||
|
||||
sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
|
||||
|
||||
- Flash the u-boot-dtb.img image into the micro SD card:
|
||||
|
||||
sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
|
||||
|
||||
- Jumper settings:
|
||||
|
||||
MMC Boot: JM3 Closed
|
||||
|
||||
- Connect the Serial cable between the Starter Kit and the PC for the console.
|
||||
(J28 is the Linux Serial console connector)
|
||||
|
||||
- Insert the micro SD card in the board, power it up and U-Boot messages should
|
||||
come up.
|
||||
@@ -0,0 +1,196 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2016 Amarula Solutions B.V.
|
||||
* Copyright (C) 2016 Engicam S.r.l.
|
||||
* Author: Jagan Teki <jagan@amarulasolutions.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/video.h>
|
||||
|
||||
#include "../common/board.h"
|
||||
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
||||
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_SRE_FAST)
|
||||
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
|
||||
|
||||
static iomux_v3_cfg_t gpmi_pads[] = {
|
||||
IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
|
||||
IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
};
|
||||
|
||||
void setup_gpmi_nand(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
/* config gpmi nand iomux */
|
||||
SETUP_IOMUX_PADS(gpmi_pads);
|
||||
|
||||
/* gate ENFC_CLK_ROOT clock first,before clk source switch */
|
||||
clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
|
||||
|
||||
/* config gpmi and bch clock to 100 MHz */
|
||||
clrsetbits_le32(&mxc_ccm->cs2cdr,
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
|
||||
|
||||
/* enable ENFC_CLK_ROOT clock */
|
||||
setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
|
||||
|
||||
/* enable gpmi and bch clock gating */
|
||||
setbits_le32(&mxc_ccm->CCGR4,
|
||||
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
|
||||
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
|
||||
|
||||
/* enable apbh clock gating */
|
||||
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_VIDEO_IPUV3)
|
||||
static iomux_v3_cfg_t const rgb_pads[] = {
|
||||
IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
|
||||
IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
|
||||
IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
|
||||
IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
|
||||
IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
|
||||
IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
|
||||
IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
|
||||
IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
|
||||
IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
|
||||
IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
|
||||
IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
|
||||
IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
|
||||
IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
|
||||
IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
|
||||
IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
|
||||
IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
|
||||
IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
|
||||
IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
|
||||
IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
|
||||
IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
|
||||
IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
|
||||
IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
|
||||
};
|
||||
|
||||
static void enable_rgb(struct display_info_t const *dev)
|
||||
{
|
||||
SETUP_IOMUX_PADS(rgb_pads);
|
||||
}
|
||||
|
||||
struct display_info_t const displays[] = {
|
||||
{
|
||||
.bus = -1,
|
||||
.addr = 0,
|
||||
.pixfmt = IPU_PIX_FMT_RGB666,
|
||||
.detect = NULL,
|
||||
.enable = enable_rgb,
|
||||
.mode = {
|
||||
.name = "Amp-WD",
|
||||
.refresh = 60,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 30000,
|
||||
.left_margin = 30,
|
||||
.right_margin = 30,
|
||||
.upper_margin = 5,
|
||||
.lower_margin = 5,
|
||||
.hsync_len = 64,
|
||||
.vsync_len = 20,
|
||||
.sync = FB_SYNC_EXT,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
|
||||
void setup_display(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
int reg;
|
||||
|
||||
enable_ipu_clock();
|
||||
|
||||
/* Turn on LDB0,IPU,IPU DI0 clocks */
|
||||
reg = __raw_readl(&mxc_ccm->CCGR3);
|
||||
reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
|
||||
writel(reg, &mxc_ccm->CCGR3);
|
||||
|
||||
/* set LDB0, LDB1 clk select to 011/011 */
|
||||
reg = readl(&mxc_ccm->cs2cdr);
|
||||
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
|
||||
MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
|
||||
reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
|
||||
(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
|
||||
writel(reg, &mxc_ccm->cs2cdr);
|
||||
|
||||
reg = readl(&mxc_ccm->cscmr2);
|
||||
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
|
||||
writel(reg, &mxc_ccm->cscmr2);
|
||||
|
||||
reg = readl(&mxc_ccm->chsccdr);
|
||||
reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
|
||||
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
|
||||
writel(reg, &mxc_ccm->chsccdr);
|
||||
|
||||
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
|
||||
IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
|
||||
IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
|
||||
IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
|
||||
IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
|
||||
IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
|
||||
IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
|
||||
IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
|
||||
IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
|
||||
writel(reg, &iomux->gpr[2]);
|
||||
|
||||
reg = readl(&iomux->gpr[3]);
|
||||
reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
|
||||
(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
|
||||
IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
|
||||
writel(reg, &iomux->gpr[3]);
|
||||
}
|
||||
#endif /* CONFIG_VIDEO_IPUV3 */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
/* i.CoreM6 RQS has USDHC3 for SD and USDHC4 for eMMC */
|
||||
return (devno == 0) ? 0: (devno - 1);
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_MX6UL_ENGICAM
|
||||
|
||||
config SYS_BOARD
|
||||
default "imx6ul"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "engicam"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "imx6-engicam"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,19 @@
|
||||
MX6UL_ENGICAM BOARD
|
||||
M: Jagan Teki <jagan@amarulasolutions.com>
|
||||
S: Maintained
|
||||
F: board/engicam/imx6ul
|
||||
F: include/configs/imx6-engicam.h
|
||||
F: configs/imx6ul_geam_mmc_defconfig
|
||||
F: configs/imx6ul_geam_nand_defconfig
|
||||
F: configs/imx6ul_isiot_emmc_defconfig
|
||||
F: configs/imx6ul_isiot_mmc_defconfig
|
||||
F: configs/imx6ul_isiot_nand_defconfig
|
||||
F: arch/arm/dts/imx6ul.dtsi
|
||||
F: arch/arm/dts/imx6ul-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6ul-geam-kit.dts
|
||||
F: arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6ul-isiot.dtsi
|
||||
F: arch/arm/dts/imx6ul-isiot-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6ul-isiot-emmc.dts
|
||||
F: arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6ul-isiot-nand.dts
|
||||
@@ -0,0 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
# Copyright (C) 2016 Amarula Solutions B.V.
|
||||
|
||||
obj-y := imx6ul.o
|
||||
@@ -0,0 +1,33 @@
|
||||
Hsow to use U-Boot on Engicam GEAM6UL and Is.IoT MX6UL Starter Kit:
|
||||
-------------------------------------------------------------------
|
||||
|
||||
$ make mrproper
|
||||
|
||||
- Configure U-Boot for Engicam GEAM6UL:
|
||||
$ make imx6ul_geam_mmc_defconfig
|
||||
|
||||
- Configure U-Boot for Engicam Is.IoT MX6UL:
|
||||
$ make imx6ul_isiot_mmc_defconfig
|
||||
|
||||
- Build U-Boot
|
||||
$ make
|
||||
|
||||
This will generate the SPL image called SPL and the u-boot-dtb.img.
|
||||
|
||||
- Flash the SPL image into the micro SD card:
|
||||
|
||||
sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
|
||||
|
||||
- Flash the u-boot-dtb.img image into the micro SD card:
|
||||
|
||||
sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
|
||||
|
||||
- Jumper settings:
|
||||
|
||||
MMC Boot: JM3 Closed
|
||||
|
||||
- Connect the Serial cable between the Starter Kit and the PC for the console.
|
||||
(J28 is the Linux Serial console connector)
|
||||
|
||||
- Insert the micro SD card in the board, power it up and U-Boot messages should
|
||||
come up.
|
||||
@@ -0,0 +1,96 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2016 Amarula Solutions B.V.
|
||||
* Copyright (C) 2016 Engicam S.r.l.
|
||||
* Author: Jagan Teki <jagan@amarulasolutions.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mmc.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
|
||||
#include "../common/board.h"
|
||||
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
|
||||
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
||||
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_SRE_FAST)
|
||||
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
|
||||
|
||||
static iomux_v3_cfg_t const nand_pads[] = {
|
||||
IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
|
||||
};
|
||||
|
||||
void setup_gpmi_nand(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
/* config gpmi nand iomux */
|
||||
SETUP_IOMUX_PADS(nand_pads);
|
||||
|
||||
clrbits_le32(&mxc_ccm->CCGR4,
|
||||
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
|
||||
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
|
||||
|
||||
/*
|
||||
* config gpmi and bch clock to 100 MHz
|
||||
* bch/gpmi select PLL2 PFD2 400M
|
||||
* 100M = 400M / 4
|
||||
*/
|
||||
clrbits_le32(&mxc_ccm->cscmr1,
|
||||
MXC_CCM_CSCMR1_BCH_CLK_SEL |
|
||||
MXC_CCM_CSCMR1_GPMI_CLK_SEL);
|
||||
clrsetbits_le32(&mxc_ccm->cscdr1,
|
||||
MXC_CCM_CSCDR1_BCH_PODF_MASK |
|
||||
MXC_CCM_CSCDR1_GPMI_PODF_MASK,
|
||||
(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
|
||||
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
|
||||
|
||||
/* enable gpmi and bch clock gating */
|
||||
setbits_le32(&mxc_ccm->CCGR4,
|
||||
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
|
||||
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
|
||||
|
||||
/* enable apbh clock gating */
|
||||
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
||||
}
|
||||
#endif /* CONFIG_NAND_MXS */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
|
||||
return (devno == 0) ? 0 : 1;
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user