GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_MEESC
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config SYS_BOARD
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default "meesc"
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config SYS_VENDOR
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default "esd"
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config SYS_CONFIG_NAME
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default "meesc"
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endif
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@@ -0,0 +1,7 @@
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MEESC BOARD
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M: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
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S: Maintained
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F: board/esd/meesc/
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F: include/configs/meesc.h
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F: configs/meesc_defconfig
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F: configs/meesc_dataflash_defconfig
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@@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
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# Stelian Pop <stelian@popies.net>
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# Lead Tech Design <www.leadtechdesign.com>
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obj-y += meesc.o
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@@ -0,0 +1,279 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2009-2015
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* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
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* esd electronic system design gmbh <www.esd.eu>
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*/
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#include <common.h>
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#include <env.h>
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#include <serial.h>
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#include <vsprintf.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/mach-types.h>
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#include <asm/setup.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/clk.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_REVISION_TAG
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static int hw_rev = -1; /* hardware revision */
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int get_hw_rev(void)
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{
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if (hw_rev >= 0)
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return hw_rev;
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hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
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if (hw_rev == 15)
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hw_rev = 0;
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return hw_rev;
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}
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#endif /* CONFIG_REVISION_TAG */
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#ifdef CONFIG_CMD_NAND
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static void meesc_nand_hw_init(void)
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{
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unsigned long csa;
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at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
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at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
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/* Enable CS3 */
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csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa[0]);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(12),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
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/* Enable NandFlash */
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gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif /* CONFIG_CMD_NAND */
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#ifdef CONFIG_MACB
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static void meesc_macb_hw_init(void)
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{
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at91_periph_clk_enable(ATMEL_ID_EMAC);
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at91_macb_hw_init();
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}
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#endif
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/*
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* Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
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* controller debugging
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* The ET1100 is located at physical address 0x70000000
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* Its process memory is located at physical address 0x70001000
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*/
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static void meesc_ethercat_hw_init(void)
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{
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at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
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/* Configure SMC EBI1_CS0 for EtherCAT */
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writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
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&smc1->cs[0].setup);
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
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AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
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&smc1->cs[0].pulse);
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writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
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&smc1->cs[0].cycle);
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/*
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* Configure behavior at external wait signal, byte-select mode, 16 bit
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* data bus width, none data float wait states and TDF optimization
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*/
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
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AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
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AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
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/* Configure RDY/BSY */
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at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
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}
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
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PHYS_SDRAM_SIZE);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
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#endif
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return rc;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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char str[32];
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u_char hw_type; /* hardware type */
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/* read the "Type" register of the ET1100 controller */
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hw_type = readb(CONFIG_ET1100_BASE);
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switch (hw_type) {
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case 0x11:
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case 0x3F:
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/* ET1100 present, arch number of MEESC-Board */
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gd->bd->bi_arch_number = MACH_TYPE_MEESC;
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puts("Board: CAN-EtherCAT Gateway");
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break;
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case 0xFF:
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/* no ET1100 present, arch number of EtherCAN/2-Board */
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gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
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puts("Board: EtherCAN/2 Gateway");
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/* switch on LED1D */
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at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
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break;
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default:
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/* assume, no ET1100 present, arch number of EtherCAN/2-Board */
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gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
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printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
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puts("Board: EtherCAN/2 Gateway");
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break;
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}
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if (env_get_f("serial#", str, sizeof(str)) > 0) {
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puts(", serial# ");
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puts(str);
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}
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#ifdef CONFIG_REVISION_TAG
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printf("\nHardware-revision: 1.%d\n", get_hw_rev());
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#endif
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printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_BOARDINFO */
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#ifdef CONFIG_SERIAL_TAG
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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char *str;
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char *serial = env_get("serial#");
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if (serial) {
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str = strchr(serial, '_');
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if (str && (strlen(str) >= 4)) {
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serialnr->high = (*(str + 1) << 8) | *(str + 2);
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serialnr->low = simple_strtoul(str + 3, NULL, 16);
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}
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} else {
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serialnr->high = 0;
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serialnr->low = 0;
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}
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}
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#endif
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#ifdef CONFIG_REVISION_TAG
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u32 get_board_rev(void)
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{
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return hw_rev | 0x100;
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}
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#endif
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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char *str;
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char buf[32];
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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/*
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* Normally the processor clock has a divisor of 2.
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* In some cases this this needs to be set to 4.
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* Check the user has set environment mdiv to 4 to change the divisor.
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*/
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str = env_get("mdiv");
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if (str && (strcmp(str, "4") == 0)) {
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writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
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AT91SAM9_PMC_MDIV_4, &pmc->mckr);
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at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
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serial_setbrg();
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/* Notify the user that the clock is not default */
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printf("Setting master clock to %s MHz\n",
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strmhz(buf, get_mck_clk_rate()));
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}
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return 0;
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}
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#endif /* CONFIG_MISC_INIT_R */
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int board_early_init_f(void)
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{
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at91_periph_clk_enable(ATMEL_ID_UHP);
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return 0;
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}
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int board_init(void)
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{
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/* initialize ET1100 Controller */
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meesc_ethercat_hw_init();
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_CMD_NAND
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meesc_nand_hw_init();
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#endif
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#ifdef CONFIG_MACB
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meesc_macb_hw_init();
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#endif
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#ifdef CONFIG_AT91_CAN
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at91_can_hw_init();
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#endif
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#ifdef CONFIG_USB_OHCI_NEW
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at91_uhp_hw_init();
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#endif
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return 0;
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}
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@@ -0,0 +1,25 @@
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if TARGET_VME8349
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config SYS_BOARD
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default "vme8349"
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config SYS_VENDOR
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default "esd"
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config SYS_CONFIG_NAME
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default "vme8349"
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endif
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if TARGET_CADDY2
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config SYS_BOARD
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default "vme8349"
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config SYS_VENDOR
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default "esd"
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config SYS_CONFIG_NAME
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default "caddy2"
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endif
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@@ -0,0 +1,7 @@
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VME8349 BOARD
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M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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S: Maintained
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F: board/esd/vme8349/
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F: include/configs/vme8349.h
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F: configs/caddy2_defconfig
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F: configs/vme8349_defconfig
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@@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (c) 2009 esd gmbh hannover germany.
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obj-y += vme8349.o caddy.o
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obj-$(CONFIG_PCI) += pci.o
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@@ -0,0 +1,177 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
|
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* Copyright (c) 2009 esd gmbh.
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*
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* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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*/
|
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|
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#include <common.h>
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#include <console.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#include <pci.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include "caddy.h"
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static struct caddy_interface *caddy_interface;
|
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void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
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{
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struct caddy_answer *answer;
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uint32_t ptr;
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answer = &caddy_interface->answer[caddy_interface->answer_in];
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memset((void *)answer, 0, sizeof(struct caddy_answer));
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answer->answer = cmd->cmd;
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answer->issue = cmd->issue;
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answer->status = status;
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memcpy(answer->par, result, 5 * sizeof(result[0]));
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ptr = caddy_interface->answer_in + 1;
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ptr = ptr & (ANSWER_SIZE - 1);
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if (ptr != caddy_interface->answer_out)
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caddy_interface->answer_in = ptr;
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}
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int do_caddy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
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{
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unsigned long base_addr;
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||||
uint32_t ptr;
|
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struct caddy_cmd *caddy_cmd;
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uint32_t result[5];
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uint16_t data16;
|
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uint8_t data8;
|
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uint32_t status;
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pci_dev_t dev;
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void *pci_ptr;
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|
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if (argc < 2) {
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puts("Missing parameter\n");
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return 1;
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}
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base_addr = simple_strtoul(argv[1], NULL, 16);
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caddy_interface = (struct caddy_interface *) base_addr;
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memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
|
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memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
|
||||
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while (ctrlc() == 0) {
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if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
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memset(result, 0, 5 * sizeof(result[0]));
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status = 0;
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caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
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pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
|
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(caddy_cmd->addr & 0x001fffff);
|
||||
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||||
switch (caddy_cmd->cmd) {
|
||||
case CADDY_CMD_IO_READ_8:
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result[0] = in_8(pci_ptr);
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break;
|
||||
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case CADDY_CMD_IO_READ_16:
|
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result[0] = in_be16(pci_ptr);
|
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break;
|
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case CADDY_CMD_IO_READ_32:
|
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result[0] = in_be32(pci_ptr);
|
||||
break;
|
||||
|
||||
case CADDY_CMD_IO_WRITE_8:
|
||||
data8 = caddy_cmd->par[0] & 0x000000ff;
|
||||
out_8(pci_ptr, data8);
|
||||
break;
|
||||
|
||||
case CADDY_CMD_IO_WRITE_16:
|
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data16 = caddy_cmd->par[0] & 0x0000ffff;
|
||||
out_be16(pci_ptr, data16);
|
||||
break;
|
||||
|
||||
case CADDY_CMD_IO_WRITE_32:
|
||||
out_be32(pci_ptr, caddy_cmd->par[0]);
|
||||
break;
|
||||
|
||||
case CADDY_CMD_CONFIG_READ_8:
|
||||
dev = PCI_BDF(caddy_cmd->par[0],
|
||||
caddy_cmd->par[1],
|
||||
caddy_cmd->par[2]);
|
||||
status = pci_read_config_byte(dev,
|
||||
caddy_cmd->addr,
|
||||
&data8);
|
||||
result[0] = data8;
|
||||
break;
|
||||
|
||||
case CADDY_CMD_CONFIG_READ_16:
|
||||
dev = PCI_BDF(caddy_cmd->par[0],
|
||||
caddy_cmd->par[1],
|
||||
caddy_cmd->par[2]);
|
||||
status = pci_read_config_word(dev,
|
||||
caddy_cmd->addr,
|
||||
&data16);
|
||||
result[0] = data16;
|
||||
break;
|
||||
|
||||
case CADDY_CMD_CONFIG_READ_32:
|
||||
dev = PCI_BDF(caddy_cmd->par[0],
|
||||
caddy_cmd->par[1],
|
||||
caddy_cmd->par[2]);
|
||||
status = pci_read_config_dword(dev,
|
||||
caddy_cmd->addr,
|
||||
&result[0]);
|
||||
break;
|
||||
|
||||
case CADDY_CMD_CONFIG_WRITE_8:
|
||||
dev = PCI_BDF(caddy_cmd->par[0],
|
||||
caddy_cmd->par[1],
|
||||
caddy_cmd->par[2]);
|
||||
data8 = caddy_cmd->par[3] & 0x000000ff;
|
||||
status = pci_write_config_byte(dev,
|
||||
caddy_cmd->addr,
|
||||
data8);
|
||||
break;
|
||||
|
||||
case CADDY_CMD_CONFIG_WRITE_16:
|
||||
dev = PCI_BDF(caddy_cmd->par[0],
|
||||
caddy_cmd->par[1],
|
||||
caddy_cmd->par[2]);
|
||||
data16 = caddy_cmd->par[3] & 0x0000ffff;
|
||||
status = pci_write_config_word(dev,
|
||||
caddy_cmd->addr,
|
||||
data16);
|
||||
break;
|
||||
|
||||
case CADDY_CMD_CONFIG_WRITE_32:
|
||||
dev = PCI_BDF(caddy_cmd->par[0],
|
||||
caddy_cmd->par[1],
|
||||
caddy_cmd->par[2]);
|
||||
status = pci_write_config_dword(dev,
|
||||
caddy_cmd->addr,
|
||||
caddy_cmd->par[3]);
|
||||
break;
|
||||
|
||||
default:
|
||||
status = 0xffffffff;
|
||||
break;
|
||||
}
|
||||
|
||||
generate_answer(caddy_cmd, status, &result[0]);
|
||||
|
||||
ptr = caddy_interface->cmd_out + 1;
|
||||
ptr = ptr & (CMD_SIZE - 1);
|
||||
caddy_interface->cmd_out = ptr;
|
||||
}
|
||||
|
||||
caddy_interface->heartbeat++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
caddy, 2, 0, do_caddy,
|
||||
"Start Caddy server.",
|
||||
"Start Caddy server with Data structure a given addr\n"
|
||||
);
|
||||
@@ -0,0 +1,59 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
|
||||
* Copyright (c) 2009 esd gmbh.
|
||||
*
|
||||
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
*/
|
||||
|
||||
#ifndef __CADDY_H__
|
||||
#define __CADDY_H__
|
||||
|
||||
#define CMD_SIZE 1024
|
||||
#define ANSWER_SIZE 1024
|
||||
#define CADDY_MAGIC "esd vme8349 V1.0"
|
||||
|
||||
enum caddy_cmds {
|
||||
CADDY_CMD_IO_READ_8,
|
||||
CADDY_CMD_IO_READ_16,
|
||||
CADDY_CMD_IO_READ_32,
|
||||
CADDY_CMD_IO_WRITE_8,
|
||||
CADDY_CMD_IO_WRITE_16,
|
||||
CADDY_CMD_IO_WRITE_32,
|
||||
CADDY_CMD_CONFIG_READ_8,
|
||||
CADDY_CMD_CONFIG_READ_16,
|
||||
CADDY_CMD_CONFIG_READ_32,
|
||||
CADDY_CMD_CONFIG_WRITE_8,
|
||||
CADDY_CMD_CONFIG_WRITE_16,
|
||||
CADDY_CMD_CONFIG_WRITE_32,
|
||||
};
|
||||
|
||||
struct caddy_cmd {
|
||||
uint32_t cmd;
|
||||
uint32_t issue;
|
||||
uint32_t addr;
|
||||
uint32_t par[5];
|
||||
};
|
||||
|
||||
struct caddy_answer {
|
||||
uint32_t answer;
|
||||
uint32_t issue;
|
||||
uint32_t status;
|
||||
uint32_t par[5];
|
||||
};
|
||||
|
||||
struct caddy_interface {
|
||||
uint8_t magic[16];
|
||||
uint32_t cmd_in;
|
||||
uint32_t cmd_out;
|
||||
uint32_t heartbeat;
|
||||
uint32_t reserved1;
|
||||
struct caddy_cmd cmd[CMD_SIZE];
|
||||
uint32_t answer_in;
|
||||
uint32_t answer_out;
|
||||
uint32_t reserved2;
|
||||
uint32_t reserved3;
|
||||
struct caddy_answer answer[CMD_SIZE];
|
||||
};
|
||||
|
||||
#endif /* of __CADDY_H__ */
|
||||
@@ -0,0 +1,117 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* pci.c -- esd VME8349 PCI board support.
|
||||
* Copyright (c) 2006 Wind River Systems, Inc.
|
||||
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
|
||||
* Copyright (c) 2009 esd gmbh.
|
||||
*
|
||||
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
*
|
||||
* Based on MPC8349 PCI support but w/o PIB related code.
|
||||
*/
|
||||
|
||||
#include <init.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <mpc83xx.h>
|
||||
#include <pci.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/fsl_i2c.h>
|
||||
#include "vme8349pin.h"
|
||||
|
||||
static struct pci_region pci1_regions[] = {
|
||||
{
|
||||
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
|
||||
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
|
||||
size: CONFIG_SYS_PCI1_MEM_SIZE,
|
||||
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||
},
|
||||
{
|
||||
bus_start: CONFIG_SYS_PCI1_IO_BASE,
|
||||
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
|
||||
size: CONFIG_SYS_PCI1_IO_SIZE,
|
||||
flags: PCI_REGION_IO
|
||||
},
|
||||
{
|
||||
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
|
||||
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
|
||||
size: CONFIG_SYS_PCI1_MMIO_SIZE,
|
||||
flags: PCI_REGION_MEM
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* pci_init_board()
|
||||
*
|
||||
* NOTICE: PCI2 is not supported. There is only one
|
||||
* physical PCI slot on the board.
|
||||
*
|
||||
*/
|
||||
void
|
||||
pci_init_board(void)
|
||||
{
|
||||
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||
struct pci_region *reg[] = { pci1_regions };
|
||||
u8 reg8;
|
||||
int monarch = 0;
|
||||
|
||||
i2c_set_bus_num(1);
|
||||
/* Read the PCI_M66EN jumper setting */
|
||||
if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, 1) == 0) ||
|
||||
(i2c_read(0x38 , 0, 0, ®8, 1) == 0)) {
|
||||
if (reg8 & 0x40) {
|
||||
clk->occr = 0xff000000; /* 66 MHz PCI */
|
||||
printf("PCI: 66MHz\n");
|
||||
} else {
|
||||
clk->occr = 0xffff0003; /* 33 MHz PCI */
|
||||
printf("PCI: 33MHz\n");
|
||||
}
|
||||
if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
|
||||
monarch = 1;
|
||||
} else {
|
||||
clk->occr = 0xffff0003; /* 33 MHz PCI */
|
||||
printf("PCI: 33MHz (I2C read failed)\n");
|
||||
}
|
||||
udelay(2000);
|
||||
|
||||
/*
|
||||
* Assert/deassert VME reset
|
||||
*/
|
||||
clrsetbits_be32(&immr->gpio[1].dat,
|
||||
GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
|
||||
GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
|
||||
setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
|
||||
GPIO2_TSI_POWERUP_RESET_N |
|
||||
GPIO2_VME_RESET_N |
|
||||
GPIO2_L_RESET_EN_N);
|
||||
clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
|
||||
udelay(200);
|
||||
setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
|
||||
udelay(200);
|
||||
setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
|
||||
udelay(600000);
|
||||
clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
|
||||
|
||||
/* Configure PCI Local Access Windows */
|
||||
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
|
||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
|
||||
|
||||
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
|
||||
|
||||
udelay(2000);
|
||||
|
||||
if (monarch == 0) {
|
||||
mpc83xx_pci_init(1, reg);
|
||||
} else {
|
||||
/*
|
||||
* Release PCI RST Output signal
|
||||
*/
|
||||
out_be32(&immr->pci_ctrl[0].gcr, 0);
|
||||
udelay(2000);
|
||||
out_be32(&immr->pci_ctrl[0].gcr, 1);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,209 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* vme8349.c -- esd VME8349 board support
|
||||
*
|
||||
* Copyright (c) 2008-2009 esd gmbh.
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
* Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ioports.h>
|
||||
#include <mpc83xx.h>
|
||||
#include <asm/mpc8349_pci.h>
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
#include <linux/libfdt.h>
|
||||
#endif
|
||||
#include <asm/io.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <spd.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <i2c.h>
|
||||
#include <netdev.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void ddr_enable_ecc(unsigned int dram_size);
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
u32 msize = 0;
|
||||
|
||||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
|
||||
return -ENXIO;
|
||||
|
||||
/* DDR SDRAM - Main memory */
|
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
|
||||
|
||||
msize = spd_sdram();
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
/*
|
||||
* Initialize and enable DDR ECC.
|
||||
*/
|
||||
ddr_enable_ecc(msize * 1024 * 1024);
|
||||
#endif
|
||||
|
||||
/* Now check memory size (after ECC is initialized) */
|
||||
msize = get_ram_size(0, msize);
|
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
gd->ram_size = msize * 1024 * 1024;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
puts("Board: esd VME-CADDY/2\n");
|
||||
#else
|
||||
puts("Board: esd VME-CPU/8349\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int misc_init_r()
|
||||
{
|
||||
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
|
||||
clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
|
||||
* and VME-CADDY/2) have different SDRAM configurations.
|
||||
*/
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
#define SMALL_RAM 0xff
|
||||
#define LARGE_RAM 0x00
|
||||
#else
|
||||
#define SMALL_RAM 0x00
|
||||
#define LARGE_RAM 0xff
|
||||
#endif
|
||||
|
||||
#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
|
||||
|
||||
static spd_eeprom_t default_spd_eeprom = {
|
||||
SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
|
||||
SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
|
||||
SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
|
||||
SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
|
||||
SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
|
||||
SPD_VAL(0x00, 0x00), /* 05 */
|
||||
SPD_VAL(0x40, 0x40), /* 06 */
|
||||
SPD_VAL(0x00, 0x00), /* 07 */
|
||||
SPD_VAL(0x05, 0x05), /* 08 */
|
||||
SPD_VAL(0x30, 0x30), /* 09 */
|
||||
SPD_VAL(0x45, 0x45), /* 10 */
|
||||
SPD_VAL(0x02, 0x02), /* 11 ecc used */
|
||||
SPD_VAL(0x82, 0x82), /* 12 */
|
||||
SPD_VAL(0x10, 0x10), /* 13 */
|
||||
SPD_VAL(0x08, 0x08), /* 14 */
|
||||
SPD_VAL(0x00, 0x00), /* 15 */
|
||||
SPD_VAL(0x0c, 0x0c), /* 16 */
|
||||
SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
|
||||
SPD_VAL(0x38, 0x38), /* 18 */
|
||||
SPD_VAL(0x00, 0x00), /* 19 */
|
||||
SPD_VAL(0x02, 0x02), /* 20 */
|
||||
SPD_VAL(0x00, 0x00), /* 21 */
|
||||
SPD_VAL(0x03, 0x03), /* 22 */
|
||||
SPD_VAL(0x3d, 0x3d), /* 23 */
|
||||
SPD_VAL(0x45, 0x45), /* 24 */
|
||||
SPD_VAL(0x50, 0x50), /* 25 */
|
||||
SPD_VAL(0x45, 0x45), /* 26 */
|
||||
SPD_VAL(0x3c, 0x3c), /* 27 */
|
||||
SPD_VAL(0x28, 0x28), /* 28 */
|
||||
SPD_VAL(0x3c, 0x3c), /* 29 */
|
||||
SPD_VAL(0x2d, 0x2d), /* 30 */
|
||||
SPD_VAL(0x20, 0x80), /* 31 */
|
||||
SPD_VAL(0x20, 0x20), /* 32 */
|
||||
SPD_VAL(0x27, 0x27), /* 33 */
|
||||
SPD_VAL(0x10, 0x10), /* 34 */
|
||||
SPD_VAL(0x17, 0x17), /* 35 */
|
||||
SPD_VAL(0x3c, 0x3c), /* 36 */
|
||||
SPD_VAL(0x1e, 0x1e), /* 37 */
|
||||
SPD_VAL(0x1e, 0x1e), /* 38 */
|
||||
SPD_VAL(0x00, 0x00), /* 39 */
|
||||
SPD_VAL(0x00, 0x06), /* 40 */
|
||||
SPD_VAL(0x37, 0x37), /* 41 */
|
||||
SPD_VAL(0x4b, 0x7f), /* 42 */
|
||||
SPD_VAL(0x80, 0x80), /* 43 */
|
||||
SPD_VAL(0x18, 0x18), /* 44 */
|
||||
SPD_VAL(0x22, 0x22), /* 45 */
|
||||
SPD_VAL(0x00, 0x00), /* 46 */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
SPD_VAL(0x10, 0x10), /* 62 */
|
||||
SPD_VAL(0x7e, 0x1d), /* 63 */
|
||||
{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
|
||||
SPD_VAL(0x00, 0x00), /* 72 */
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
{ "vme-caddy/2 ram " }
|
||||
#else
|
||||
{ "vme-cpu/2 ram " }
|
||||
#endif
|
||||
};
|
||||
|
||||
int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
int old_bus = i2c_get_bus_num();
|
||||
unsigned int l, sum;
|
||||
int valid = 0;
|
||||
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
if (i2c_read(chip, addr, alen, buffer, len) == 0)
|
||||
if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
|
||||
sum = 0;
|
||||
for (l = 0; l < 63; l++)
|
||||
sum = (sum + buffer[l]) & 0xff;
|
||||
if (sum == buffer[63])
|
||||
valid = 1;
|
||||
else
|
||||
printf("Invalid checksum in EEPROM %02x %02x\n",
|
||||
sum, buffer[63]);
|
||||
}
|
||||
|
||||
if (valid == 0) {
|
||||
memcpy(buffer, (void *)&default_spd_eeprom, len);
|
||||
sum = 0;
|
||||
for (l = 0; l < 63; l++)
|
||||
sum = (sum + buffer[l]) & 0xff;
|
||||
if (sum != buffer[63])
|
||||
printf("Invalid checksum in FLASH %02x %02x\n",
|
||||
sum, buffer[63]);
|
||||
buffer[63] = sum;
|
||||
}
|
||||
|
||||
i2c_set_bus_num(old_bus);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
|
||||
* Copyright (c) 2009 esd gmbh.
|
||||
*
|
||||
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
*/
|
||||
|
||||
#ifndef __VME8349PIN_H__
|
||||
#define __VME8349PIN_H__
|
||||
|
||||
#define GPIO2_V_SCON 0x80000000 /* In: from tsi148 1: is syscon */
|
||||
#define GPIO2_VME_RESET_N 0x20000000 /* Out: to tsi148 */
|
||||
#define GPIO2_TSI_PLL_RESET_N 0x08000000 /* Out: to tsi148 */
|
||||
#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148 */
|
||||
#define GPIO2_L_RESET_EN_N 0x00100000 /* Out: 0:vme can assert cpu lrst*/
|
||||
|
||||
#endif /* of ifndef __VME8349PIN_H__ */
|
||||
Reference in New Issue
Block a user