GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,25 @@
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if TARGET_VME8349
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config SYS_BOARD
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default "vme8349"
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config SYS_VENDOR
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default "esd"
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config SYS_CONFIG_NAME
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default "vme8349"
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endif
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if TARGET_CADDY2
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config SYS_BOARD
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default "vme8349"
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config SYS_VENDOR
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default "esd"
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config SYS_CONFIG_NAME
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default "caddy2"
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endif
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@@ -0,0 +1,7 @@
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VME8349 BOARD
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M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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S: Maintained
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F: board/esd/vme8349/
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F: include/configs/vme8349.h
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F: configs/caddy2_defconfig
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F: configs/vme8349_defconfig
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@@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (c) 2009 esd gmbh hannover germany.
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obj-y += vme8349.o caddy.o
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obj-$(CONFIG_PCI) += pci.o
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@@ -0,0 +1,177 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
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* Copyright (c) 2009 esd gmbh.
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*
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* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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*/
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#include <common.h>
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#include <console.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#include <pci.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include "caddy.h"
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static struct caddy_interface *caddy_interface;
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void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
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{
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struct caddy_answer *answer;
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uint32_t ptr;
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answer = &caddy_interface->answer[caddy_interface->answer_in];
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memset((void *)answer, 0, sizeof(struct caddy_answer));
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answer->answer = cmd->cmd;
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answer->issue = cmd->issue;
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answer->status = status;
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memcpy(answer->par, result, 5 * sizeof(result[0]));
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ptr = caddy_interface->answer_in + 1;
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ptr = ptr & (ANSWER_SIZE - 1);
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if (ptr != caddy_interface->answer_out)
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caddy_interface->answer_in = ptr;
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}
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int do_caddy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned long base_addr;
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uint32_t ptr;
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struct caddy_cmd *caddy_cmd;
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uint32_t result[5];
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uint16_t data16;
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uint8_t data8;
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uint32_t status;
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pci_dev_t dev;
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void *pci_ptr;
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if (argc < 2) {
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puts("Missing parameter\n");
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return 1;
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}
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base_addr = simple_strtoul(argv[1], NULL, 16);
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caddy_interface = (struct caddy_interface *) base_addr;
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memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
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memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
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while (ctrlc() == 0) {
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if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
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memset(result, 0, 5 * sizeof(result[0]));
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status = 0;
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caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
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pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
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(caddy_cmd->addr & 0x001fffff);
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switch (caddy_cmd->cmd) {
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case CADDY_CMD_IO_READ_8:
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result[0] = in_8(pci_ptr);
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break;
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case CADDY_CMD_IO_READ_16:
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result[0] = in_be16(pci_ptr);
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break;
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case CADDY_CMD_IO_READ_32:
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result[0] = in_be32(pci_ptr);
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break;
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case CADDY_CMD_IO_WRITE_8:
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data8 = caddy_cmd->par[0] & 0x000000ff;
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out_8(pci_ptr, data8);
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break;
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case CADDY_CMD_IO_WRITE_16:
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data16 = caddy_cmd->par[0] & 0x0000ffff;
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out_be16(pci_ptr, data16);
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break;
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case CADDY_CMD_IO_WRITE_32:
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out_be32(pci_ptr, caddy_cmd->par[0]);
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break;
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case CADDY_CMD_CONFIG_READ_8:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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status = pci_read_config_byte(dev,
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caddy_cmd->addr,
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&data8);
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result[0] = data8;
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break;
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case CADDY_CMD_CONFIG_READ_16:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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status = pci_read_config_word(dev,
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caddy_cmd->addr,
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&data16);
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result[0] = data16;
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break;
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case CADDY_CMD_CONFIG_READ_32:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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status = pci_read_config_dword(dev,
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caddy_cmd->addr,
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&result[0]);
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break;
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case CADDY_CMD_CONFIG_WRITE_8:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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data8 = caddy_cmd->par[3] & 0x000000ff;
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status = pci_write_config_byte(dev,
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caddy_cmd->addr,
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data8);
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break;
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case CADDY_CMD_CONFIG_WRITE_16:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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data16 = caddy_cmd->par[3] & 0x0000ffff;
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status = pci_write_config_word(dev,
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caddy_cmd->addr,
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data16);
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break;
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case CADDY_CMD_CONFIG_WRITE_32:
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dev = PCI_BDF(caddy_cmd->par[0],
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caddy_cmd->par[1],
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caddy_cmd->par[2]);
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status = pci_write_config_dword(dev,
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caddy_cmd->addr,
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caddy_cmd->par[3]);
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break;
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default:
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status = 0xffffffff;
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break;
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}
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generate_answer(caddy_cmd, status, &result[0]);
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ptr = caddy_interface->cmd_out + 1;
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ptr = ptr & (CMD_SIZE - 1);
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caddy_interface->cmd_out = ptr;
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}
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caddy_interface->heartbeat++;
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}
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return 0;
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}
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U_BOOT_CMD(
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caddy, 2, 0, do_caddy,
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"Start Caddy server.",
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"Start Caddy server with Data structure a given addr\n"
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);
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@@ -0,0 +1,59 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
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* Copyright (c) 2009 esd gmbh.
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*
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* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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*/
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#ifndef __CADDY_H__
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#define __CADDY_H__
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#define CMD_SIZE 1024
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#define ANSWER_SIZE 1024
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#define CADDY_MAGIC "esd vme8349 V1.0"
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enum caddy_cmds {
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CADDY_CMD_IO_READ_8,
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CADDY_CMD_IO_READ_16,
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CADDY_CMD_IO_READ_32,
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CADDY_CMD_IO_WRITE_8,
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CADDY_CMD_IO_WRITE_16,
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CADDY_CMD_IO_WRITE_32,
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CADDY_CMD_CONFIG_READ_8,
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CADDY_CMD_CONFIG_READ_16,
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CADDY_CMD_CONFIG_READ_32,
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CADDY_CMD_CONFIG_WRITE_8,
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CADDY_CMD_CONFIG_WRITE_16,
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CADDY_CMD_CONFIG_WRITE_32,
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};
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struct caddy_cmd {
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uint32_t cmd;
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uint32_t issue;
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uint32_t addr;
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uint32_t par[5];
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};
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struct caddy_answer {
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uint32_t answer;
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uint32_t issue;
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uint32_t status;
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uint32_t par[5];
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};
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struct caddy_interface {
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uint8_t magic[16];
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uint32_t cmd_in;
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uint32_t cmd_out;
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uint32_t heartbeat;
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uint32_t reserved1;
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struct caddy_cmd cmd[CMD_SIZE];
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uint32_t answer_in;
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uint32_t answer_out;
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uint32_t reserved2;
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uint32_t reserved3;
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struct caddy_answer answer[CMD_SIZE];
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};
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#endif /* of __CADDY_H__ */
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@@ -0,0 +1,117 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* pci.c -- esd VME8349 PCI board support.
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* Copyright (c) 2006 Wind River Systems, Inc.
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* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 esd gmbh.
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*
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* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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*
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* Based on MPC8349 PCI support but w/o PIB related code.
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*/
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#include <init.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <common.h>
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#include <mpc83xx.h>
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#include <pci.h>
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#include <i2c.h>
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#include <asm/fsl_i2c.h>
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#include "vme8349pin.h"
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static struct pci_region pci1_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI1_MEM_BASE,
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
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size: CONFIG_SYS_PCI1_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI1_IO_BASE,
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phys_start: CONFIG_SYS_PCI1_IO_PHYS,
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size: CONFIG_SYS_PCI1_IO_SIZE,
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flags: PCI_REGION_IO
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},
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{
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bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
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size: CONFIG_SYS_PCI1_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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};
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/*
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* pci_init_board()
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*
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* NOTICE: PCI2 is not supported. There is only one
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* physical PCI slot on the board.
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*
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*/
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void
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pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci1_regions };
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u8 reg8;
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int monarch = 0;
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i2c_set_bus_num(1);
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/* Read the PCI_M66EN jumper setting */
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if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, 1) == 0) ||
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(i2c_read(0x38 , 0, 0, ®8, 1) == 0)) {
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if (reg8 & 0x40) {
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clk->occr = 0xff000000; /* 66 MHz PCI */
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printf("PCI: 66MHz\n");
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} else {
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clk->occr = 0xffff0003; /* 33 MHz PCI */
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printf("PCI: 33MHz\n");
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}
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if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
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monarch = 1;
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} else {
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clk->occr = 0xffff0003; /* 33 MHz PCI */
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printf("PCI: 33MHz (I2C read failed)\n");
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}
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udelay(2000);
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/*
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* Assert/deassert VME reset
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*/
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clrsetbits_be32(&immr->gpio[1].dat,
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GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
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GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
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setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
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GPIO2_TSI_POWERUP_RESET_N |
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GPIO2_VME_RESET_N |
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GPIO2_L_RESET_EN_N);
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clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
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udelay(200);
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setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
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udelay(200);
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setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
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udelay(600000);
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clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
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udelay(2000);
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if (monarch == 0) {
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mpc83xx_pci_init(1, reg);
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} else {
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/*
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* Release PCI RST Output signal
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*/
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out_be32(&immr->pci_ctrl[0].gcr, 0);
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udelay(2000);
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out_be32(&immr->pci_ctrl[0].gcr, 1);
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}
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}
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@@ -0,0 +1,209 @@
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// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* vme8349.c -- esd VME8349 board support
|
||||
*
|
||||
* Copyright (c) 2008-2009 esd gmbh.
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
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* Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
|
||||
*/
|
||||
|
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#include <common.h>
|
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#include <ioports.h>
|
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#include <mpc83xx.h>
|
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#include <asm/mpc8349_pci.h>
|
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#if defined(CONFIG_OF_LIBFDT)
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#include <linux/libfdt.h>
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#endif
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <spd.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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void ddr_enable_ecc(unsigned int dram_size);
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int dram_init(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -ENXIO;
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/* DDR SDRAM - Main memory */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
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msize = spd_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
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/*
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* Initialize and enable DDR ECC.
|
||||
*/
|
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ddr_enable_ecc(msize * 1024 * 1024);
|
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#endif
|
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/* Now check memory size (after ECC is initialized) */
|
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msize = get_ram_size(0, msize);
|
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
gd->ram_size = msize * 1024 * 1024;
|
||||
|
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return 0;
|
||||
}
|
||||
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||||
int checkboard(void)
|
||||
{
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
puts("Board: esd VME-CADDY/2\n");
|
||||
#else
|
||||
puts("Board: esd VME-CPU/8349\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int misc_init_r()
|
||||
{
|
||||
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
|
||||
clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
|
||||
* and VME-CADDY/2) have different SDRAM configurations.
|
||||
*/
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
#define SMALL_RAM 0xff
|
||||
#define LARGE_RAM 0x00
|
||||
#else
|
||||
#define SMALL_RAM 0x00
|
||||
#define LARGE_RAM 0xff
|
||||
#endif
|
||||
|
||||
#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
|
||||
|
||||
static spd_eeprom_t default_spd_eeprom = {
|
||||
SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
|
||||
SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
|
||||
SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
|
||||
SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
|
||||
SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
|
||||
SPD_VAL(0x00, 0x00), /* 05 */
|
||||
SPD_VAL(0x40, 0x40), /* 06 */
|
||||
SPD_VAL(0x00, 0x00), /* 07 */
|
||||
SPD_VAL(0x05, 0x05), /* 08 */
|
||||
SPD_VAL(0x30, 0x30), /* 09 */
|
||||
SPD_VAL(0x45, 0x45), /* 10 */
|
||||
SPD_VAL(0x02, 0x02), /* 11 ecc used */
|
||||
SPD_VAL(0x82, 0x82), /* 12 */
|
||||
SPD_VAL(0x10, 0x10), /* 13 */
|
||||
SPD_VAL(0x08, 0x08), /* 14 */
|
||||
SPD_VAL(0x00, 0x00), /* 15 */
|
||||
SPD_VAL(0x0c, 0x0c), /* 16 */
|
||||
SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
|
||||
SPD_VAL(0x38, 0x38), /* 18 */
|
||||
SPD_VAL(0x00, 0x00), /* 19 */
|
||||
SPD_VAL(0x02, 0x02), /* 20 */
|
||||
SPD_VAL(0x00, 0x00), /* 21 */
|
||||
SPD_VAL(0x03, 0x03), /* 22 */
|
||||
SPD_VAL(0x3d, 0x3d), /* 23 */
|
||||
SPD_VAL(0x45, 0x45), /* 24 */
|
||||
SPD_VAL(0x50, 0x50), /* 25 */
|
||||
SPD_VAL(0x45, 0x45), /* 26 */
|
||||
SPD_VAL(0x3c, 0x3c), /* 27 */
|
||||
SPD_VAL(0x28, 0x28), /* 28 */
|
||||
SPD_VAL(0x3c, 0x3c), /* 29 */
|
||||
SPD_VAL(0x2d, 0x2d), /* 30 */
|
||||
SPD_VAL(0x20, 0x80), /* 31 */
|
||||
SPD_VAL(0x20, 0x20), /* 32 */
|
||||
SPD_VAL(0x27, 0x27), /* 33 */
|
||||
SPD_VAL(0x10, 0x10), /* 34 */
|
||||
SPD_VAL(0x17, 0x17), /* 35 */
|
||||
SPD_VAL(0x3c, 0x3c), /* 36 */
|
||||
SPD_VAL(0x1e, 0x1e), /* 37 */
|
||||
SPD_VAL(0x1e, 0x1e), /* 38 */
|
||||
SPD_VAL(0x00, 0x00), /* 39 */
|
||||
SPD_VAL(0x00, 0x06), /* 40 */
|
||||
SPD_VAL(0x37, 0x37), /* 41 */
|
||||
SPD_VAL(0x4b, 0x7f), /* 42 */
|
||||
SPD_VAL(0x80, 0x80), /* 43 */
|
||||
SPD_VAL(0x18, 0x18), /* 44 */
|
||||
SPD_VAL(0x22, 0x22), /* 45 */
|
||||
SPD_VAL(0x00, 0x00), /* 46 */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
SPD_VAL(0x10, 0x10), /* 62 */
|
||||
SPD_VAL(0x7e, 0x1d), /* 63 */
|
||||
{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
|
||||
SPD_VAL(0x00, 0x00), /* 72 */
|
||||
#ifdef CONFIG_TARGET_CADDY2
|
||||
{ "vme-caddy/2 ram " }
|
||||
#else
|
||||
{ "vme-cpu/2 ram " }
|
||||
#endif
|
||||
};
|
||||
|
||||
int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
int old_bus = i2c_get_bus_num();
|
||||
unsigned int l, sum;
|
||||
int valid = 0;
|
||||
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
if (i2c_read(chip, addr, alen, buffer, len) == 0)
|
||||
if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
|
||||
sum = 0;
|
||||
for (l = 0; l < 63; l++)
|
||||
sum = (sum + buffer[l]) & 0xff;
|
||||
if (sum == buffer[63])
|
||||
valid = 1;
|
||||
else
|
||||
printf("Invalid checksum in EEPROM %02x %02x\n",
|
||||
sum, buffer[63]);
|
||||
}
|
||||
|
||||
if (valid == 0) {
|
||||
memcpy(buffer, (void *)&default_spd_eeprom, len);
|
||||
sum = 0;
|
||||
for (l = 0; l < 63; l++)
|
||||
sum = (sum + buffer[l]) & 0xff;
|
||||
if (sum != buffer[63])
|
||||
printf("Invalid checksum in FLASH %02x %02x\n",
|
||||
sum, buffer[63]);
|
||||
buffer[63] = sum;
|
||||
}
|
||||
|
||||
i2c_set_bus_num(old_bus);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
|
||||
* Copyright (c) 2009 esd gmbh.
|
||||
*
|
||||
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
*/
|
||||
|
||||
#ifndef __VME8349PIN_H__
|
||||
#define __VME8349PIN_H__
|
||||
|
||||
#define GPIO2_V_SCON 0x80000000 /* In: from tsi148 1: is syscon */
|
||||
#define GPIO2_VME_RESET_N 0x20000000 /* Out: to tsi148 */
|
||||
#define GPIO2_TSI_PLL_RESET_N 0x08000000 /* Out: to tsi148 */
|
||||
#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148 */
|
||||
#define GPIO2_L_RESET_EN_N 0x00100000 /* Out: 0:vme can assert cpu lrst*/
|
||||
|
||||
#endif /* of ifndef __VME8349PIN_H__ */
|
||||
Reference in New Issue
Block a user