GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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if TARGET_IMX8MM_EVK
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config SYS_BOARD
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default "imx8mm_evk"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "imx8mm_evk"
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endif
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i.MX8MM EVK BOARD
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M: Peng Fan <peng.fan@nxp.com>
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S: Maintained
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F: board/freescale/imx8mm_evk/
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F: include/configs/imx8mm_evk.h
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F: configs/imx8mm_evk_defconfig
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#
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# Copyright 2018 NXP
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += imx8mm_evk.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
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endif
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U-Boot for the NXP i.MX8MM EVK board
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Quick Start
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===========
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- Build the ARM Trusted firmware binary
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- Get ddr fimware
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- Build U-Boot
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- Boot
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Get and Build the ARM Trusted firmware
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======================================
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Note: srctree is U-Boot source directory
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Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
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branch: imx_4.19.35_1.0.0
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$ make PLAT=imx8mm bl31
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$ cp build/imx8mm/release/bl31.bin $(srctree)
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Get the ddr and hdmi firmware
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=============================
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$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
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$ chmod +x firmware-imx-8.0.bin
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$ ./firmware-imx-8.0
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$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
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Build U-Boot
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============
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$ export CROSS_COMPILE=aarch64-poky-linux-
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$ make imx8mm_evk_defconfig
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$ export ATF_LOAD_ADDR=0x920000
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$ make flash.bin
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Burn the flash.bin to MicroSD card offset 33KB
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$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
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Boot
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====
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Set Boot switch to SD boot
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#if IS_ENABLED(CONFIG_FEC_MXC)
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Use 125M anatop REF_CLK1 for ENET1, not from external */
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clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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if (IS_ENABLED(CONFIG_FEC_MXC))
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setup_fec();
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return 0;
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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env_set("board_name", "EVK");
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env_set("board_rev", "iMX8MM");
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#endif
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return 0;
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}
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File diff suppressed because it is too large
Load Diff
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8mm_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/arch/ddr.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <dm/uclass-internal.h>
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#include <dm/device-internal.h>
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#include <power/pmic.h>
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#include <power/bd71837.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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switch (boot_dev_spl) {
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case SD2_BOOT:
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case MMC2_BOOT:
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return BOOT_DEVICE_MMC1;
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case SD3_BOOT:
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case MMC3_BOOT:
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return BOOT_DEVICE_MMC2;
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default:
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return BOOT_DEVICE_NONE;
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}
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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void spl_board_init(void)
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{
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puts("Normal Boot\n");
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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static iomux_v3_cfg_t const uart_pads[] = {
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IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_pads[] = {
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IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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return 0;
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}
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret;
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ret = pmic_get("pmic@4b", &dev);
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if (ret == -ENODEV) {
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puts("No pmic\n");
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return 0;
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}
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if (ret != 0)
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return ret;
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/* decrease RESET key long push time from the default 10s to 10ms */
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pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
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/* unlock the PMIC regs */
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pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
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/* increase VDD_SOC to typical value 0.85v before first DRAM access */
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pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
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/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
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pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
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#ifndef CONFIG_IMX8M_LPDDR4
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/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
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pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
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#endif
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/* lock the PMIC regs */
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pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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arch_cpu_init();
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init_uart_clk(1);
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board_early_init_f();
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timer_init();
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preloader_console_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device_by_name(UCLASS_CLK,
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"clock-controller@30380000",
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&dev);
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if (ret < 0) {
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printf("Failed to find clock node. Check device tree\n");
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hang();
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}
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enable_tzc380();
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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board_init_r(NULL, 0);
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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puts ("resetting ...\n");
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reset_cpu(WDOG1_BASE_ADDR);
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return 0;
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}
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