GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,17 @@
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if TARGET_LS1021AIOT
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config SYS_BOARD
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default "ls1021aiot"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "ls102xa"
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config SYS_CONFIG_NAME
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default "ls1021aiot"
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source "board/freescale/common/Kconfig"
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endif
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@@ -0,0 +1,7 @@
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LS1021AIOT BOARD
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M: Feng Li <feng.li_2@nxp.com>
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S: Maintained
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F: board/freescale/ls1021aiot/
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F: include/configs/ls1021aiot.h
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F: configs/ls1021aiot_sdcard_defconfig
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F: configs/ls1021aiot_qspi_defconfig
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@@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2016 Freescale Semiconductor, Inc.
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obj-y += ls1021aiot.o
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obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
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obj-$(CONFIG_ARMV7_PSCI) += psci.o
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@@ -0,0 +1,58 @@
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Overview
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--------
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The LS1021A-IOT is a Freescale reference board that hosts
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the LS1021A SoC.
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LS1021AIOT board Overview
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-------------------------
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- DDR Controller
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- Supports 1GB un-buffered DDR3L SDRAM discrete
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devices(32-bit bus) with 4 bit ECC
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- DDR power supplies 1.35V to all devices with
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automatic tracking of VTT
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- Soldered DDR chip
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- Supprot one fixed speed
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- Ethernet
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- Two on-board SGMII 10/100/1G ethernet ports
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- One Gbit Etherent RGMII interface to 4-ports switch
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with 4x 10/100/1000 RJ145 ports
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- CPLD
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- 8-bit registers in CPLD for system configuration
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- connected to IFC_AD[0:7]
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- Power Supplies
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- 12V@5A DC
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- SDHC
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- SDHC port connects directly to a full 8-bit SD/MMC slot
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- Support for SDIO devices
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- USB
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- Two on-board USB 3.0
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- One on-board USB k22
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- PCIe
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- Two MiniPCIe Solts
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- SATA
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- Support SATA Connector
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- AUDIO
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- AUDIO in and out
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- I/O Expansion
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- Arduino Shield Connector
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- Port0 - CAN/GPIO/Flextimer
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- Port1 - GPIO/CPLD Expansion
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- Port2 - SPI/I2C/UART
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Memory map
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-----------
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The addresses in brackets are physical addresses.
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Start Address End Address Description Size
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0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
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0x00_4000_0000 0x00_43FF_FFFF QSPI(Chip select 0) 64MB
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0x00_4400_0000 0x00_47FF_FFFF QSPI(Chip select 1) 64MB
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0x00_6000_0000 0x00_6000_FFFF CPLD 64K
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0x00_8000_0000 0x00_BFFF_FFFF DDR 1GB
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Boot description
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-----------------
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LS1021A-IOT support two ways of boot:
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Qspi boot and SD boot
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The board doesn't support boot from another
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source without changing any switch/jumper.
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@@ -0,0 +1,47 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* FSL DCU Framebuffer driver
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*/
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#include <common.h>
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#include <fsl_dcu_fb.h>
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#include "div64.h"
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#include "../common/dcu_sii9022a.h"
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int dcu_set_pixel_clock(unsigned int pixclock)
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{
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unsigned long long div;
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div = (unsigned long long)(gd->bus_clk / 1000);
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div *= (unsigned long long)pixclock;
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do_div(div, 1000000000);
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return div;
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}
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int platform_dcu_init(struct fb_info *fbinfo,
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unsigned int xres, unsigned int yres,
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const char *port,
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struct fb_videomode *dcu_fb_videomode)
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{
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const char *name;
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unsigned int pixel_format;
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if (strncmp(port, "twr_lcd", 4) == 0) {
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name = "TWR_LCD_RGB card";
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} else {
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name = "HDMI";
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dcu_set_dvi_encoder(dcu_fb_videomode);
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}
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printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
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pixel_format = 32;
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fsl_dcu_init(fbinfo, xres, yres, pixel_format);
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return 0;
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}
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@@ -0,0 +1,237 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ls102xa_stream_id.h>
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#include <asm/arch/ls102xa_devdis.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <fsl_csu.h>
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#include <fsl_immap.h>
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#include <netdev.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <spl.h>
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#include <fsl_validate.h>
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#include "../common/sleep.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define DDR_SIZE 0x40000000
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int checkboard(void)
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{
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puts("Board: LS1021AIOT\n");
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#ifndef CONFIG_QSPI_BOOT
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struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 cpldrev;
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cpldrev = in_be32(&dcfg->gpporcr1);
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printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
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0xf));
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#endif
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return 0;
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}
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void ddrmc_init(void)
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{
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struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
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u32 temp_sdram_cfg, tmp;
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out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
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out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
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out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
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out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
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out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
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out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
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out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
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out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
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out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
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out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
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out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
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out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
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out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
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out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
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out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
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out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
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out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
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out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
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out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
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out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
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/* DDR erratum A-009942 */
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tmp = in_be32(&ddr->debug[28]);
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out_be32(&ddr->debug[28], tmp | 0x0070006f);
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udelay(500);
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temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
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out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
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}
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int dram_init(void)
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{
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#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
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ddrmc_init();
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#endif
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erratum_a008850_post();
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gd->ram_size = DDR_SIZE;
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return 0;
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}
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#ifdef CONFIG_TSEC_ENET
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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if (is_serdes_configured(SGMII_TSEC1)) {
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puts("eTSEC1 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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if (is_serdes_configured(SGMII_TSEC2)) {
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puts("eTSEC2 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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return pci_eth_init(bis);
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}
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#endif
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int board_early_init_f(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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#ifdef CONFIG_TSEC_ENET
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/* clear BD & FR bits for BE BD's and frame data */
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clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
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#endif
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arch_soc_init();
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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/* Clear the BSS */
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memset(__bss_start, 0, __bss_end - __bss_start);
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get_clocks();
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preloader_console_init();
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dram_init();
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/* Allow OCRAM access permission as R/W */
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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board_init_r(NULL, 0);
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}
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#endif
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int board_init(void)
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{
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#ifndef CONFIG_SYS_FSL_NO_SERDES
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fsl_serdes_init();
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#endif
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ls102xa_smmu_stream_id_init();
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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return 0;
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}
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#endif
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#if defined(CONFIG_MISC_INIT_R)
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int misc_init_r(void)
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{
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#ifdef CONFIG_FSL_DEVICE_DISABLE
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device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
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#endif
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#ifdef CONFIG_FSL_CAAM
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return sec_init();
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#endif
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}
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#endif
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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void flash_write16(u16 val, void *addr)
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{
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u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
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__raw_writew(shftval, addr);
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}
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u16 flash_read16(void *addr)
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{
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u16 val = __raw_readw(addr);
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return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
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}
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@@ -0,0 +1,14 @@
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#PBI commands
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09570200 ffffffff
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09570158 00000300
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8940007c 21f47300
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#Configure Scratch register
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09ee0200 10000000
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#Configure alternate space
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09570158 00001000
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#Flush PBL data
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096100c0 000FFFFF
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09ea085c 00502880
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@@ -0,0 +1,27 @@
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#PBL preamble and RCW header
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aa55aa55 01ee0100
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# serdes protocol
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#Default with 2 x SGMII (no SATA)
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0608000a 00000000 00000000 00000000
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20000000 08407900 60025a00 21046000
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00000000 00000000 00000000 20038000
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20024800 881b1340 00000000 00000000
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#SATA set-up
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#0608000a 00000000 00000000 00000000
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#70000000 08007900 60025a00 21046000
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#00000000 00000000 00000000 20038000
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#20024800 881b1340 00000000 00000000
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#HDMI set-up
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#0608000a 00000000 00000000 00000000
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#20000000 08407900 60025a00 21046000
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#00000000 00000000 00000000 20038000
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#00000000 881b1340 00000000 00000000
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#QE testing
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#0608000a 00000000 00000000 00000000
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#20000000 08407900 60025a00 21046000
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#00000000 00000000 00000000 00038000
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#20094800 881b1340 00000000 00000000
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@@ -0,0 +1,27 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 NXP Semiconductor.
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* Author: Feng Li <feng.li_2@nxp.com>
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/armv7.h>
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#include <asm/psci.h>
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.pushsection ._secure.text, "ax"
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.arch_extension sec
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.align 5
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.globl psci_system_off
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psci_system_off:
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1: wfi
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b 1b
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.globl psci_text_end
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psci_text_end:
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nop
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.popsection
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