GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/board/freescale/ls1021atsn/Kconfig

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+# SPDX-License-Identifier: GPL-2.0
+if TARGET_LS1021ATSN
+
+config SYS_BOARD
+	default "ls1021atsn"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "ls102xa"
+
+config SYS_CONFIG_NAME
+	default "ls1021atsn"
+
+source "board/freescale/common/Kconfig"
+
+endif

source/bootloader/u-boot-2020.01/board/freescale/ls1021atsn/MAINTAINERS

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+NXP LS1021A-TSN Board
+M:	Vladimir Oltean <olteanv@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/ls1021a-tsn.dts
+F:	board/freescale/ls1021atsn/
+F:	include/configs/ls1021atsn.h
+F:	configs/ls1021atsn_qspi_defconfig
+F:	configs/ls1021atsn_sdcard_defconfig

source/bootloader/u-boot-2020.01/board/freescale/ls1021atsn/Makefile

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+# SPDX-License-Identifier: GPL-2.0
+obj-y += ls1021atsn.o
+obj-$(CONFIG_ARMV7_PSCI) += ../ls1021atwr/psci.o

source/bootloader/u-boot-2020.01/board/freescale/ls1021atsn/README.rst

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+.. SPDX-License-Identifier: GPL-2.0
+
+LS1021A-TSN Board Overview
+==========================
+
+ - 1GB DDR3 at 800 MHz
+ - Spansion/Cypress 64 MB (Rev. A) / 32 MB (Rev. B and C) QSPI NOR flash
+ - Ethernet
+     - 2 SGMII 10/100/1G Ethernet ports (Atheros AR8031)
+     - One SJA1105T switch with 4 Ethernet ports (Broadcom BCM5464R)
+     - One internal RGMII port connected to the switch
+ - SDHC
+     - microSDHC/SDXC connector
+ - Other I/O
+    - One Serial port
+    - Arduino and expansion headers
+    - mPCIE slot
+    - SATA port
+    - USB3.0 port
+
+LS1021A Memory map
+==================
+
+The addresses in brackets are physical addresses.
+
+==============  ==============  ==============================  =======
+Start Address   End Address     Description                     Size
+==============  ==============  ==============================  =======
+0x00_0000_0000  0x00_000F_FFFF  Secure Boot ROM                 1MB
+0x00_0100_0000  0x00_0FFF_FFFF  CCSRBAR                         240MB
+0x00_1000_0000  0x00_1000_FFFF  OCRAM0                          64KB
+0x00_1001_0000  0x00_1001_FFFF  OCRAM1                          64KB
+0x00_2000_0000  0x00_20FF_FFFF  DCSR                            16MB
+0x00_4000_0000  0x00_5FFF_FFFF  QSPI                            512MB
+0x00_6000_0000  0x00_67FF_FFFF  IFC - NOR Flash                 128MB
+0x00_8000_0000  0x00_FFFF_FFFF  DRAM1                           2GB
+==============  ==============  ==============================  =======
+
+Compiling and flashing
+======================
+
+The LS1021A-TSN board comes along with a microSD card with OpenIL U-Boot that
+can be used to update its internal QSPI flash (which is empty out of the
+factory).
+
+To compile and flash an SD card image::
+
+  make ls1021atsn_sdcard_defconfig && make -j 8 && sudo cp u-boot-with-spl-pbl.bin /srv/tftpboot/
+  => tftp 0x82000000 u-boot-with-spl-pbl.bin && mmc rescan && mmc erase 8 0x1100 && mmc write 0x82000000 8 0x1100
+
+For the QSPI flash, first obtain the Reset Configuration Word binary for
+bootimg from the QSPI flash from the rcw project
+(https://source.codeaurora.org/external/qoriq/qoriq-components/rcw)::
+
+  make -j 8 && sudo cp ls1021atsn/SSR_PNS_30/rcw_1200_qspiboot.bin.swapped /srv/tftpboot/
+
+The above RCW binary takes care of swapping the QSPI AMBA memory, so that the
+U-Boot binary does not need to be swapped when flashing it.
+
+To compile and flash a U-Boot image for QSPI::
+
+  make ls1021atsn_qspi_defconfig && make -j 8 && sudo cp u-boot.bin /srv/tftpboot/
+
+Then optionally create a custom uboot-env.txt file (although the default
+environment already supports distro boot) and convert it to binary format::
+
+  mkenvimage -s 2M -o /srv/tftpboot/uboot-env.bin uboot-env.txt
+
+To program the QSPI flash with the images::
+
+  => tftp 0x82000000 rcw_1200_qspiboot.bin.swapped && sf probe && sf erase 0x0 +${filesize} && sf write 0x82000000 0x0 ${filesize}
+  => tftp 0x82000000 u-boot.bin && sf probe && sf erase 0x100000 +${filesize} && sf write 0x82000000 0x100000 ${filesize}
+  => tftp 0x82000000 uboot-env.bin && sf probe && sf erase 0x400000 +${filesize} && sf write 0x82000000 0x400000 ${filesize}
+
+The boards contain an AT24 I2C EEPROM that is supposed to hold the MAC
+addresses of the Ethernet interfaces, however the EEPROM comes blank out of
+the factory, and the MAC addresses are printed on a label on the bottom of
+the boards.
+
+To write the MAC addresses to the EEPROM, the following needs to be done once::
+
+  => mac id
+  => mac 0 00:1F:7B:xx:xx:xx
+  => mac 1 00:1F:7B:xx:xx:xx
+  => mac 2 00:1F:7B:xx:xx:xx
+  => mac save
+
+The switch ports do not have their own MAC address - they inherit it from the
+master enet2 port.
+
+Known issues and limitations
+============================
+
+- The 4 SJA1105 switch ports are not functional in U-Boot for now.
+- Since the IFC pins are multiplexed with QSPI on LS1021A, currently there is
+  no way to talk to the CPLD for e.g. running the "qixis_reset" command, or
+  turning the fan on, etc.

source/bootloader/u-boot-2020.01/board/freescale/ls1021atsn/ls1021atsn.c

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+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2016-2019 NXP Semiconductors
+ */
+#include <common.h>
+#include <init.h>
+#include <asm/arch-ls102xa/ls102xa_soc.h>
+#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <asm/arch/fsl_serdes.h>
+#include "../common/sleep.h"
+#include <fsl_validate.h>
+#include <fsl_immap.h>
+#include <fsl_csu.h>
+#include <netdev.h>
+#include <spl.h>
+#ifdef CONFIG_U_QE
+#include <fsl_qe.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ddrmc_init(void)
+{
+#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+	u32 temp_sdram_cfg, tmp;
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
+
+	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
+	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
+	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
+	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
+	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
+	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
+
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		out_be32(&ddr->sdram_cfg_2,
+			 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
+		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+		out_be32(&ddr->init_ext_addr, (1 << 31));
+
+		/* DRAM VRef will not be trained */
+		out_be32(&ddr->ddr_cdr2,
+			 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
+	} else
+#endif
+	{
+		out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+		out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+	}
+
+	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
+	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
+
+	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
+	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
+
+	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
+
+	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
+	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
+
+	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+	/* DDR erratum A-009942 */
+	tmp = in_be32(&ddr->debug[28]);
+	out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
+	udelay(1);
+
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* enter self-refresh */
+		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+
+		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
+	} else
+#endif
+		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* exit self-refresh */
+		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+	}
+#endif
+#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
+}
+
+int dram_init(void)
+{
+	ddrmc_init();
+
+	erratum_a008850_post();
+
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+	fsl_dp_resume();
+#endif
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_TSEC_ENET
+	/*
+	 * Clear BD & FR bits for big endian BD's and frame data (aka set
+	 * correct eTSEC endianness). This is crucial in ensuring that it does
+	 * not report Data Parity Errors in its RX/TX FIFOs when attempting to
+	 * send traffic.
+	 */
+	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	/* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
+	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+#endif
+
+	arch_soc_init();
+
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot()) {
+		timer_init();
+		dram_init();
+	}
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	void (*second_uboot)(void);
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	get_clocks();
+
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
+	preloader_console_init();
+
+	dram_init();
+
+	/* Allow OCRAM access permission as R/W */
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+	enable_layerscape_ns_access();
+#endif
+
+	/*
+	 * if it is woken up from deep sleep, then jump to second
+	 * stage U-Boot and continue executing without recopying
+	 * it from SD since it has already been reserved in memory
+	 * in last boot.
+	 */
+	if (is_warm_boot()) {
+		second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
+		second_uboot();
+	}
+
+	board_init_r(NULL, 0);
+}
+#endif
+
+int board_init(void)
+{
+#ifndef CONFIG_SYS_FSL_NO_SERDES
+	fsl_serdes_init();
+#endif
+	ls102xa_smmu_stream_id_init();
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_U_QE
+	u_qe_init();
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void spl_board_init(void)
+{
+	ls102xa_smmu_stream_id_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_CHAIN_OF_TRUST
+	fsl_setenv_chain_of_trust();
+#endif
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	return sec_init();
+#endif
+}
+#endif
+
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}

source/bootloader/u-boot-2020.01/board/freescale/ls1021atsn/ls102xa_pbi.cfg

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+# PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+# Configure Scratch register
+09ee0200 10000000
+# Configure alternate space
+09570158 00001000
+# Flush PBL data
+096100c0 000FFFFF
+
+09ea085c 00502880
+09ea0560 80800000

source/bootloader/u-boot-2020.01/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg

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+# PBL preamble and RCW header
+aa55aa55 01ee0100
+
+# Disable IFC, enable QSPI and DSPI
+0608000c 00000000 00000000 00000000
+30000000 08007900 40105a00 21046000
+00000000 00000000 00000000 10002000
+20124801 8804b340 00000000 00000000