GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,65 @@
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if TARGET_LS1028AQDS
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config SYS_BOARD
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default "ls1028a"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1028aqds"
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config EMMC_BOOT
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bool "Support for booting from EMMC"
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default n
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config SYS_TEXT_BASE
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default 0x96000000 if SD_BOOT || EMMC_BOOT
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default 0x82000000 if TFABOOT
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default 0x20100000
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if FSL_LS_PPA
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config SYS_LS_PPA_FW_ADDR
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hex "PPA Firmware Addr"
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default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
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default 0x400000 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A
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if CHAIN_OF_TRUST
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config SYS_LS_PPA_ESBC_ADDR
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hex "PPA header Addr"
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default 0x20600000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
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endif
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endif
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source "board/freescale/common/Kconfig"
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endif
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if TARGET_LS1028ARDB
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config SYS_BOARD
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default "ls1028a"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1028ardb"
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config EMMC_BOOT
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bool "Support for booting from EMMC"
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default n
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config SYS_TEXT_BASE
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default 0x96000000 if SD_BOOT || EMMC_BOOT
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default 0x82000000 if TFABOOT
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default 0x20100000
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source "board/freescale/common/Kconfig"
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endif
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@@ -0,0 +1,31 @@
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LS1028AQDS BOARD
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M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
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M: Rai Harninder <harninder.rai@nxp.com>
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M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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M: Tang Yuantian <andy.tang@nxp.com>
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S: Maintained
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F: board/freescale/ls1028a/
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F: include/configs/ls1028a_common.h
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F: include/configs/ls1028aqds.h
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F: configs/ls1028aqds_tfa_defconfig
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LS1028ARDB BOARD
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M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
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M: Rai Harninder <harninder.rai@nxp.com>
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M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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M: Tang Yuantian <andy.tang@nxp.com>
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S: Maintained
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F: board/freescale/ls1028a/
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F: include/configs/ls1028a_common.h
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F: include/configs/ls1028ardb.h
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F: configs/ls1028ardb_tfa_defconfig
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LS1028AQDS_SECURE_BOOT BOARD
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M: Tang Yuantian <andy.tang@nxp.com>
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S: Maintained
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F: configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
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LS1028ARDB_SECURE_BOOT BOARD
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M: Tang Yuantian <andy.tang@nxp.com>
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S: Maintained
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F: configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
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@@ -0,0 +1,8 @@
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#
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# Copyright 2019 NXP
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += ls1028a.o
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obj-y += ddr.o
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@@ -0,0 +1,164 @@
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Overview
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--------
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The LS1028A Reference Design (RDB) is a high-performance computing,
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evaluation, and development platform that supports ARM SoC LS1028A and its
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derivatives.
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LS1028A SoC Overview
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--------------------------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
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RDB Default Switch Settings (1: ON; 0: OFF)
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-------------------------------------------
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For XSPI NOR boot (default)
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SW2: 1111_1000
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SW3: 1111_0000
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SW5: 0011_1001
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For SD Boot
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SW2: 1000_1000
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SW3: 1111_0000
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SW5: 0011_1001
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For eMMC Boot
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SW2: 1001_1000
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SW3: 1111_0000
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SW5: 0011_1001
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LS1028ARDB board Overview
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-------------------------
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Processor
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Two Arm Cortex- A72 processor cores:
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- Based on 64-bit ARMv8 architecture
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- Up to 1.3 GHz operation
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- Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
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data cache
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- Arranged as a single cluster of two cores sharing a single 1 MB L2
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cache
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DDR memory
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- Five onboard 1G x8 discrete memory modules (Four data byte lanes
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ECC)
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- 32-bit data and 4-bit ECC
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- One chip select
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- Data transfer rates of up to 1.6 GT/s
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- Single-bit error correction and double-bit error detection ECC (4-bit
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check word across 32-bit data)
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High-speed serial ports(SerDes)
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- Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
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Qualcomm AR8033 PHY
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- Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
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through the NXP F104S8A PHY
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- Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
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(8 Gbit/s) cards
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- Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
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slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
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SATA Gen 3 cards (6 Gbit/s) at a time
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eSDHC
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- eSDHC1, eSDHC2
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SPI
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- Connects to two mikroBUS sockets to support mikro-click modules,
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such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
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field communications (NFC) controller
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Octal SPI (XSPI)
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- One 256 MB onboard XSPI serial NOR flash memory
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- One 512 MB onboard XSPI serial NAND flash memory
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- Supports a QSPI emulator for offboard QSPI emulation
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I2C
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- All system devices are accessed via I2C1, which is multiplexed on
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I2C multiplexer PCA9848 to isolate address conflicts and reduce
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capacitive load
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- I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
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thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
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1 and 2
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CAN
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- The two CAN DB9 ports can support CAN FD fast phase at data rates of
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up to 5 Mbit/s
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Serial audio interface(SAI)
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- Audio codec SGTL5000 provides headphone and audio LINEOUT for
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stereo speakers
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- IEEE1588 interface to support audio on SAI4
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QDS Default Switch Settings (1: ON; 0: OFF)
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-------------------------------------------
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For SD Boot
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SW1 : 1000_0000
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SW2 : 1110_0110
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SW3 : 0000_0010
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SW4 : 0000_0000
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SW5 : 0000_0000
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SW6 : 0000_0000
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SW7 : 1111_0011
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SW8 : 1110_0000
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SW9 : 1000_0001
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SW10: 1110_0000
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For XSPI Boot
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SW1 : 1111_0000
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SW2 : 0000_0110
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SW3 : 0000_0010
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SW4 : 0000_0000
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SW5 : 0110_0000
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SW6 : 0101_0000
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SW7 : 1111_0011
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SW8 : 1110_0000
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SW9 : 1000_0000
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SW10: 1110_0000
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LS1028AQDS board Overview
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-------------------------
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Processor
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Two Arm Cortex- A72 processor cores:
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- Based on 64-bit ARMv8 architecture
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- Up to 1.3 GHz operation
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- Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
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data cache
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- Arranged as a single cluster of two cores sharing a single 1 MB L2
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cache
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DDR memory
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- Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L
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- Supports a single- or dual-ranked SODIMM or UDIMM connector
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- 32-bit data and 4-bit ECC
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- Supports x8/x16 devices
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- Supports ECC error detection and correction
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- 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to
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all devices in case of DDR3L or DDR4, respectively. Power can
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switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or
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DDR4 devices, respectively
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SerDes (Serializer/Deserializer)
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- Four-lane (0-3) SerDes:
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- Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
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Gbit SXGMII, 1 Gbit SGMII
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- Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
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SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII
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- Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
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SGMII
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- Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
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SGMII, SATA 2.0/3.0
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- Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII
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add-in cards
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- Lane 1 connects to a 2x10 connector with SFP+ through a retimer;
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lane 2 (TX lines) connects to an SMA connector
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Lane 3 connects to 1x7 header to support SATA devices
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eSDHC
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- eSDHC1, eSDHC2
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SPI
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- SPI1 and SPI2 support three onboard SPI flash memory devices:
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512 Mbit high-speed flash (with speed of up to 108/54 MHz)
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memory for storage
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4 Mbit low-speed flash memory (with speed of up to 40 MHz)
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64 Mbit high-speed flash memory (with speed of up to 104/80
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MHz)
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- SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of
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up to 104/80 MHz)
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- All memories operate at 1.8 V
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- A header is provided on SPI1 to test SPI slave mode
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I2C
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- LS1028A supports eight I2C controllers
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Serial audio interface(SAI)
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Two SAI ports with audio codec SGTL5000:
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- Include stereo LINEIN with support for external analog input
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- Provide headphone and line output
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Display
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- DisplayPort connector to connect the DP data to a 4K display device
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(computer monitor)
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- eDP connector to connect the DP data to a 4K display panel
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@@ -0,0 +1,20 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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DECLARE_GLOBAL_DATA_PTR;
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int fsl_initdram(void)
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{
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gd->ram_size = tfa_get_dram_size();
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if (!gd->ram_size)
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gd->ram_size = fsl_ddr_sdram_size();
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return 0;
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}
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@@ -0,0 +1,246 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <fsl_ddr.h>
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#include <asm/io.h>
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#include <hwconfig.h>
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#include <fdt_support.h>
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#include <linux/libfdt.h>
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#include <env_internal.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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#include <asm/arch-fsl-layerscape/fsl_icid.h>
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#include <i2c.h>
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#include <asm/arch/soc.h>
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#ifdef CONFIG_FSL_LS_PPA
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#include <asm/arch/ppa.h>
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#endif
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#include <fsl_immap.h>
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#include <netdev.h>
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#include <fdtdec.h>
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#include <miiphy.h>
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#include "../common/qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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int config_board_mux(void)
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{
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#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
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u8 reg;
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reg = QIXIS_READ(brdcfg[13]);
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/* Field| Function
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* 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
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* I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
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* 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
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* I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
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*/
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reg &= ~(0xf0);
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reg |= 0xb0;
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QIXIS_WRITE(brdcfg[13], reg);
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reg = QIXIS_READ(brdcfg[15]);
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/* Field| Function
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* 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
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* CAN1 | 0= CAN #1 transceiver enabled
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* 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
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* CAN2 | 0= CAN #2 transceiver enabled
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*/
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reg &= ~(0xc0);
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QIXIS_WRITE(brdcfg[15], reg);
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#endif
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return 0;
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}
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|
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int board_init(void)
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{
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
|
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#endif
|
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|
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#ifdef CONFIG_FSL_CAAM
|
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sec_init();
|
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#endif
|
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|
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#ifdef CONFIG_FSL_LS_PPA
|
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ppa_init();
|
||||
#endif
|
||||
|
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#ifndef CONFIG_SYS_EARLY_PCI_INIT
|
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pci_init();
|
||||
#endif
|
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|
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#if defined(CONFIG_TARGET_LS1028ARDB)
|
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u8 val = I2C_MUX_CH_DEFAULT;
|
||||
|
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#ifndef CONFIG_DM_I2C
|
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i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
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#else
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struct udevice *dev;
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|
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if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
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dm_i2c_write(dev, 0x0b, &val, 1);
|
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#endif
|
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|
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#endif
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return 0;
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}
|
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int board_eth_init(bd_t *bis)
|
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{
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return pci_eth_init(bis);
|
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}
|
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|
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
|
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{
|
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config_board_mux();
|
||||
|
||||
return 0;
|
||||
}
|
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#endif
|
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|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_I2C_EARLY_INIT
|
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i2c_early_init_f();
|
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#endif
|
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|
||||
fsl_lsch3_early_init_f();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void detail_board_ddr_info(void)
|
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{
|
||||
puts("\nDDR ");
|
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
|
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print_ddr_info(0);
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||||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
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u64 base[CONFIG_NR_DRAM_BANKS];
|
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u64 size[CONFIG_NR_DRAM_BANKS];
|
||||
|
||||
ft_cpu_setup(blob, bd);
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||||
|
||||
/* fixup DT for the two GPP DDR banks */
|
||||
base[0] = gd->bd->bi_dram[0].start;
|
||||
size[0] = gd->bd->bi_dram[0].size;
|
||||
base[1] = gd->bd->bi_dram[1].start;
|
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size[1] = gd->bd->bi_dram[1].size;
|
||||
|
||||
#ifdef CONFIG_RESV_RAM
|
||||
/* reduce size if reserved memory is within this bank */
|
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if (gd->arch.resv_ram >= base[0] &&
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gd->arch.resv_ram < base[0] + size[0])
|
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size[0] = gd->arch.resv_ram - base[0];
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else if (gd->arch.resv_ram >= base[1] &&
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gd->arch.resv_ram < base[1] + size[1])
|
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size[1] = gd->arch.resv_ram - base[1];
|
||||
#endif
|
||||
|
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fdt_fixup_memory_banks(blob, base, size, 2);
|
||||
|
||||
fdt_fixup_icid(blob);
|
||||
|
||||
return 0;
|
||||
}
|
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#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QIXIS
|
||||
int checkboard(void)
|
||||
{
|
||||
#ifdef CONFIG_TFABOOT
|
||||
enum boot_src src = get_boot_src();
|
||||
#endif
|
||||
u8 sw;
|
||||
|
||||
int clock;
|
||||
char *board;
|
||||
char buf[64] = {0};
|
||||
static const char *freq[6] = {"100.00", "125.00", "156.25",
|
||||
"161.13", "322.26", "100.00 SS"};
|
||||
|
||||
cpu_name(buf);
|
||||
/* find the board details */
|
||||
sw = QIXIS_READ(id);
|
||||
|
||||
switch (sw) {
|
||||
case 0x46:
|
||||
board = "QDS";
|
||||
break;
|
||||
case 0x47:
|
||||
board = "RDB";
|
||||
break;
|
||||
case 0x49:
|
||||
board = "HSSI";
|
||||
break;
|
||||
default:
|
||||
board = "unknown";
|
||||
break;
|
||||
}
|
||||
|
||||
sw = QIXIS_READ(arch);
|
||||
printf("Board: %s-%s, Version: %c, boot from ",
|
||||
buf, board, (sw & 0xf) + 'A' - 1);
|
||||
|
||||
sw = QIXIS_READ(brdcfg[0]);
|
||||
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
|
||||
|
||||
#ifdef CONFIG_TFABOOT
|
||||
if (src == BOOT_SOURCE_SD_MMC) {
|
||||
puts("SD\n");
|
||||
} else if (src == BOOT_SOURCE_SD_MMC2) {
|
||||
puts("eMMC\n");
|
||||
} else {
|
||||
#endif
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
puts("SD\n");
|
||||
#elif defined(CONFIG_EMMC_BOOT)
|
||||
puts("eMMC\n");
|
||||
#else
|
||||
switch (sw) {
|
||||
case 0:
|
||||
case 4:
|
||||
printf("NOR\n");
|
||||
break;
|
||||
case 1:
|
||||
printf("NAND\n");
|
||||
break;
|
||||
default:
|
||||
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_TFABOOT
|
||||
}
|
||||
#endif
|
||||
|
||||
printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
|
||||
puts("SERDES1 Reference : ");
|
||||
|
||||
sw = QIXIS_READ(brdcfg[2]);
|
||||
#ifdef CONFIG_TARGET_LS1028ARDB
|
||||
clock = (sw >> 6) & 3;
|
||||
#else
|
||||
clock = (sw >> 4) & 0xf;
|
||||
#endif
|
||||
|
||||
printf("Clock1 = %sMHz ", freq[clock]);
|
||||
#ifdef CONFIG_TARGET_LS1028ARDB
|
||||
clock = (sw >> 4) & 3;
|
||||
#else
|
||||
clock = sw & 0xf;
|
||||
#endif
|
||||
printf("Clock2 = %sMHz\n", freq[clock]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user