GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,41 @@
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if TARGET_LS1043ARDB
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config SYS_BOARD
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default "ls1043ardb"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1043ardb"
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config SYS_HAS_ARMV8_SECURE_BASE
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bool "Enable secure address for PSCI image"
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depends on ARMV8_PSCI
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default n
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help
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PSCI image can be re-located to secure RAM.
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If enabled, please also define the value for ARMV8_SECURE_BASE,
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for LS1043ARDB, it could be some address in OCRAM.
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if FSL_LS_PPA
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config SYS_LS_PPA_FW_ADDR
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hex "PPA Firmware Addr"
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default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
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default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
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if CHAIN_OF_TRUST
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config SYS_LS_PPA_ESBC_ADDR
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hex "PPA Firmware HDR Addr"
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default 0x60680000 if SYS_LS_PPA_FW_IN_XIP
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default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
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endif
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endif
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source "board/freescale/common/Kconfig"
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endif
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@@ -0,0 +1,19 @@
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LS1043A BOARD
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M: Mingkai Hu <mingkai.hu@nxp.com>
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M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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S: Maintained
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F: board/freescale/ls1043ardb/
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F: board/freescale/ls1043ardb/ls1043ardb.c
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F: include/configs/ls1043ardb.h
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F: configs/ls1043ardb_defconfig
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F: configs/ls1043ardb_nand_defconfig
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F: configs/ls1043ardb_sdcard_defconfig
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F: configs/ls1043ardb_tfa_defconfig
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F: configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
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LS1043A_SECURE_BOOT BOARD
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M: Ruchika Gupta <ruchika.gupta@nxp.com>
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S: Maintained
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F: configs/ls1043ardb_SECURE_BOOT_defconfig
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F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
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F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig
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@@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2015 Freescale Semiconductor
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obj-y += ddr.o
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obj-y += ls1043ardb.o
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_NET) += eth.o
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obj-y += cpld.o
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endif
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@@ -0,0 +1,54 @@
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Overview
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--------
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The LS1043A Reference Design Board (RDB) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS1043A
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LayerScape Architecture processor. The LS1043ARDB provides SW development
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platform for the Freescale LS1043A processor series, with a complete
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debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
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LS1043A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
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SoC overview.
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LS1043ARDB board Overview
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-----------------------
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- SERDES Connections, 4 lanes supporting:
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- PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
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standard PCIe card
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- QSGMII with x4 RJ45 connector
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- XFI with x1 RJ45 connector
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- DDR Controller
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- 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
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-IFC/Local Bus
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- One 128MB NOR flash 16-bit data bus
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- One 512 MB NAND flash with ECC support
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- CPLD connection
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- USB 3.0
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- Two super speed USB 3.0 Type A ports
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- SDHC: connects directly to a full SD/MMC slot
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- DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
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- 4 I2C controllers
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- UART
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- Two 4-pin serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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Start Address End Address Description Size
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0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
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0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
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0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
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0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
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0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
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0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
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0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
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0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
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0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
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Booting Options
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---------------
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a) NOR boot
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b) NAND boot
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c) SD boot
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@@ -0,0 +1,173 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor
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*
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* Freescale LS1043ARDB board-specific CPLD controlling supports.
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include "cpld.h"
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u8 cpld_read(unsigned int reg)
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{
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void *p = (void *)CONFIG_SYS_CPLD_BASE;
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return in_8(p + reg);
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}
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void cpld_write(unsigned int reg, u8 value)
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{
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void *p = (void *)CONFIG_SYS_CPLD_BASE;
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out_8(p + reg, value);
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}
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/* Set the boot bank to the alternate bank */
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void cpld_set_altbank(void)
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{
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u16 reg = CPLD_CFG_RCW_SRC_NOR;
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u8 reg4 = CPLD_READ(soft_mux_on);
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u8 reg5 = (u8)(reg >> 1);
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u8 reg6 = (u8)(reg & 1);
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u8 reg7 = CPLD_READ(vbank);
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cpld_rev_bit(®5);
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CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
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CPLD_WRITE(cfg_rcw_src1, reg5);
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CPLD_WRITE(cfg_rcw_src2, reg6);
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reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
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CPLD_WRITE(vbank, reg7);
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CPLD_WRITE(system_rst, 1);
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}
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/* Set the boot bank to the default bank */
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void cpld_set_defbank(void)
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{
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u16 reg = CPLD_CFG_RCW_SRC_NOR;
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u8 reg4 = CPLD_READ(soft_mux_on);
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u8 reg5 = (u8)(reg >> 1);
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u8 reg6 = (u8)(reg & 1);
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cpld_rev_bit(®5);
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CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
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CPLD_WRITE(cfg_rcw_src1, reg5);
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CPLD_WRITE(cfg_rcw_src2, reg6);
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CPLD_WRITE(vbank, 0);
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CPLD_WRITE(system_rst, 1);
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}
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void cpld_set_nand(void)
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{
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u16 reg = CPLD_CFG_RCW_SRC_NAND;
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u8 reg5 = (u8)(reg >> 1);
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u8 reg6 = (u8)(reg & 1);
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cpld_rev_bit(®5);
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CPLD_WRITE(soft_mux_on, 1);
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CPLD_WRITE(cfg_rcw_src1, reg5);
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CPLD_WRITE(cfg_rcw_src2, reg6);
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CPLD_WRITE(system_rst, 1);
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}
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void cpld_set_sd(void)
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{
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u16 reg = CPLD_CFG_RCW_SRC_SD;
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u8 reg5 = (u8)(reg >> 1);
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u8 reg6 = (u8)(reg & 1);
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cpld_rev_bit(®5);
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CPLD_WRITE(soft_mux_on, 1);
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CPLD_WRITE(cfg_rcw_src1, reg5);
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CPLD_WRITE(cfg_rcw_src2, reg6);
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CPLD_WRITE(system_rst, 1);
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}
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#ifdef DEBUG
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static void cpld_dump_regs(void)
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{
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printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
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printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
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printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
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printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
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printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
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printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
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printf("vbank = %x\n", CPLD_READ(vbank));
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printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
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printf("uart_sel = %x\n", CPLD_READ(uart_sel));
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printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
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printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel));
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printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel));
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printf("status_led = %x\n", CPLD_READ(status_led));
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putc('\n');
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}
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#endif
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void cpld_rev_bit(unsigned char *value)
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{
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u8 rev_val, val;
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int i;
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val = *value;
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rev_val = val & 1;
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for (i = 1; i <= 7; i++) {
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val >>= 1;
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rev_val <<= 1;
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rev_val |= val & 1;
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}
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*value = rev_val;
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}
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int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int rc = 0;
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if (argc <= 1)
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return cmd_usage(cmdtp);
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if (strcmp(argv[1], "reset") == 0) {
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if (strcmp(argv[2], "altbank") == 0)
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cpld_set_altbank();
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else if (strcmp(argv[2], "nand") == 0)
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cpld_set_nand();
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else if (strcmp(argv[2], "sd") == 0)
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cpld_set_sd();
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else
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cpld_set_defbank();
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#ifdef DEBUG
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} else if (strcmp(argv[1], "dump") == 0) {
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cpld_dump_regs();
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#endif
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} else {
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rc = cmd_usage(cmdtp);
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}
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return rc;
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}
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U_BOOT_CMD(
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cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
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"Reset the board or alternate bank",
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"reset: reset to default bank\n"
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"cpld reset altbank: reset to alternate bank\n"
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"cpld reset nand: reset to boot from NAND flash\n"
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"cpld reset sd: reset to boot from SD card\n"
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#ifdef DEBUG
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"cpld dump - display the CPLD registers\n"
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#endif
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);
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@@ -0,0 +1,45 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015 Freescale Semiconductor
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*/
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#ifndef __CPLD_H__
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#define __CPLD_H__
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/*
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* CPLD register set of LS1043ARDB board-specific.
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*/
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struct cpld_data {
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u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
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u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
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u8 pcba_ver; /* 0x2 - PCBA Revision Register */
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u8 system_rst; /* 0x3 - system reset register */
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u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
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u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */
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u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */
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u8 vbank; /* 0x7 - Flash bank selection Control */
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u8 sysclk_sel; /* 0x8 - */
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u8 uart_sel; /* 0x9 - */
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u8 sd1refclk_sel; /* 0xA - */
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u8 tdmclk_mux_sel; /* 0xB - */
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u8 sdhc_spics_sel; /* 0xC - */
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u8 status_led; /* 0xD - */
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u8 global_rst; /* 0xE - */
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};
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u8 cpld_read(unsigned int reg);
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void cpld_write(unsigned int reg, u8 value);
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void cpld_rev_bit(unsigned char *value);
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
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#define CPLD_WRITE(reg, value) \
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cpld_write(offsetof(struct cpld_data, reg), value)
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/* CPLD on IFC */
|
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#define CPLD_SW_MUX_BANK_SEL 0x40
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#define CPLD_BANK_SEL_MASK 0x07
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#define CPLD_BANK_SEL_ALTBANK 0x04
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#define CPLD_CFG_RCW_SRC_NOR 0x025
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#define CPLD_CFG_RCW_SRC_NAND 0x106
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#define CPLD_CFG_RCW_SRC_SD 0x040
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#endif
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@@ -0,0 +1,253 @@
|
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// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
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* Copyright 2015 Freescale Semiconductor, Inc.
|
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*/
|
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|
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#include <common.h>
|
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#include <fsl_ddr_sdram.h>
|
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#include <fsl_ddr_dimm_params.h>
|
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#include "ddr.h"
|
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#include <vsprintf.h>
|
||||
#ifdef CONFIG_FSL_DEEP_SLEEP
|
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#include <fsl_sleep.h>
|
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#endif
|
||||
#include <asm/arch/clock.h>
|
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|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
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void fsl_ddr_board_options(memctl_options_t *popts,
|
||||
dimm_params_t *pdimm,
|
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unsigned int ctrl_num)
|
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{
|
||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
|
||||
ulong ddr_freq;
|
||||
|
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if (ctrl_num > 1) {
|
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printf("Not supported controller number %d\n", ctrl_num);
|
||||
return;
|
||||
}
|
||||
if (!pdimm->n_ranks)
|
||||
return;
|
||||
|
||||
pbsp = udimms[0];
|
||||
|
||||
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
|
||||
* freqency and n_banks specified in board_specific_parameters table.
|
||||
*/
|
||||
ddr_freq = get_ddr_freq(0) / 1000000;
|
||||
while (pbsp->datarate_mhz_high) {
|
||||
if (pbsp->n_ranks == pdimm->n_ranks) {
|
||||
if (ddr_freq <= pbsp->datarate_mhz_high) {
|
||||
popts->clk_adjust = pbsp->clk_adjust;
|
||||
popts->wrlvl_start = pbsp->wrlvl_start;
|
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
|
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
|
||||
popts->cpo_override = pbsp->cpo_override;
|
||||
popts->write_data_delay =
|
||||
pbsp->write_data_delay;
|
||||
goto found;
|
||||
}
|
||||
pbsp_highest = pbsp;
|
||||
}
|
||||
pbsp++;
|
||||
}
|
||||
|
||||
if (pbsp_highest) {
|
||||
printf("Error: board specific timing not found for %lu MT/s\n",
|
||||
ddr_freq);
|
||||
printf("Trying to use the highest speed (%u) parameters\n",
|
||||
pbsp_highest->datarate_mhz_high);
|
||||
popts->clk_adjust = pbsp_highest->clk_adjust;
|
||||
popts->wrlvl_start = pbsp_highest->wrlvl_start;
|
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
|
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
|
||||
} else {
|
||||
panic("DIMM is not supported by this board");
|
||||
}
|
||||
found:
|
||||
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
|
||||
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
|
||||
|
||||
/* force DDR bus width to 32 bits */
|
||||
popts->data_bus_width = 1;
|
||||
popts->otf_burst_chop_en = 0;
|
||||
popts->burst_length = DDR_BL8;
|
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable:
|
||||
* - number of DIMMs installed
|
||||
*/
|
||||
popts->half_strength_driver_enable = 1;
|
||||
/*
|
||||
* Write leveling override
|
||||
*/
|
||||
popts->wrlvl_override = 1;
|
||||
popts->wrlvl_sample = 0xf;
|
||||
|
||||
/*
|
||||
* Rtt and Rtt_WR override
|
||||
*/
|
||||
popts->rtt_override = 0;
|
||||
|
||||
/* Enable ZQ calibration */
|
||||
popts->zq_en = 1;
|
||||
|
||||
/* optimize cpo for erratum A-009942 */
|
||||
popts->cpo_sample = 0x46;
|
||||
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
|
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
|
||||
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
|
||||
}
|
||||
|
||||
/* DDR model number: MT40A512M8HX-093E */
|
||||
#ifdef CONFIG_SYS_DDR_RAW_TIMING
|
||||
dimm_params_t ddr_raw_timing = {
|
||||
.n_ranks = 1,
|
||||
.rank_density = 2147483648u,
|
||||
.capacity = 2147483648u,
|
||||
.primary_sdram_width = 32,
|
||||
.ec_sdram_width = 0,
|
||||
.registered_dimm = 0,
|
||||
.mirrored_dimm = 0,
|
||||
.n_row_addr = 15,
|
||||
.n_col_addr = 10,
|
||||
.bank_addr_bits = 0,
|
||||
.bank_group_bits = 2,
|
||||
.edc_config = 0,
|
||||
.burst_lengths_bitmask = 0x0c,
|
||||
|
||||
.tckmin_x_ps = 938,
|
||||
.tckmax_ps = 1500,
|
||||
.caslat_x = 0x000DFA00,
|
||||
.taa_ps = 13500,
|
||||
.trcd_ps = 13500,
|
||||
.trp_ps = 13500,
|
||||
.tras_ps = 33000,
|
||||
.trc_ps = 46500,
|
||||
.trfc1_ps = 260000,
|
||||
.trfc2_ps = 160000,
|
||||
.trfc4_ps = 110000,
|
||||
.tfaw_ps = 21000,
|
||||
.trrds_ps = 3700,
|
||||
.trrdl_ps = 5300,
|
||||
.tccdl_ps = 5355,
|
||||
.refresh_rate_ps = 7800000,
|
||||
.dq_mapping[0] = 0x0,
|
||||
.dq_mapping[1] = 0x0,
|
||||
.dq_mapping[2] = 0x0,
|
||||
.dq_mapping[3] = 0x0,
|
||||
.dq_mapping[4] = 0x0,
|
||||
.dq_mapping[5] = 0x0,
|
||||
.dq_mapping[6] = 0x0,
|
||||
.dq_mapping[7] = 0x0,
|
||||
.dq_mapping[8] = 0x0,
|
||||
.dq_mapping[9] = 0x0,
|
||||
.dq_mapping[10] = 0x0,
|
||||
.dq_mapping[11] = 0x0,
|
||||
.dq_mapping[12] = 0x0,
|
||||
.dq_mapping[13] = 0x0,
|
||||
.dq_mapping[14] = 0x0,
|
||||
.dq_mapping[15] = 0x0,
|
||||
.dq_mapping[16] = 0x0,
|
||||
.dq_mapping[17] = 0x0,
|
||||
.dq_mapping_ors = 0,
|
||||
};
|
||||
|
||||
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
|
||||
unsigned int controller_number,
|
||||
unsigned int dimm_number)
|
||||
{
|
||||
static const char dimm_model[] = "Fixed DDR on board";
|
||||
|
||||
if (((controller_number == 0) && (dimm_number == 0)) ||
|
||||
((controller_number == 1) && (dimm_number == 0))) {
|
||||
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
|
||||
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
|
||||
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
|
||||
phys_size_t fixed_sdram(void)
|
||||
{
|
||||
int i;
|
||||
char buf[32];
|
||||
fsl_ddr_cfg_regs_t ddr_cfg_regs;
|
||||
phys_size_t ddr_size;
|
||||
ulong ddr_freq, ddr_freq_mhz;
|
||||
|
||||
ddr_freq = get_ddr_freq(0);
|
||||
ddr_freq_mhz = ddr_freq / 1000000;
|
||||
|
||||
printf("Configuring DDR for %s MT/s data rate\n",
|
||||
strmhz(buf, ddr_freq));
|
||||
|
||||
for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
|
||||
if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
|
||||
(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
|
||||
memcpy(&ddr_cfg_regs,
|
||||
fixed_ddr_parm_0[i].ddr_settings,
|
||||
sizeof(ddr_cfg_regs));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (fixed_ddr_parm_0[i].max_freq == 0)
|
||||
panic("Unsupported DDR data rate %s MT/s data rate\n",
|
||||
strmhz(buf, ddr_freq));
|
||||
|
||||
ddr_size = (phys_size_t)2048 * 1024 * 1024;
|
||||
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
|
||||
|
||||
return ddr_size;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TFABOOT
|
||||
int fsl_initdram(void)
|
||||
{
|
||||
gd->ram_size = tfa_get_dram_size();
|
||||
if (!gd->ram_size)
|
||||
#ifdef CONFIG_SYS_DDR_RAW_TIMING
|
||||
gd->ram_size = fsl_ddr_sdram_size();
|
||||
#else
|
||||
gd->ram_size = 0x80000000;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
int fsl_initdram(void)
|
||||
{
|
||||
phys_size_t dram_size;
|
||||
|
||||
#ifdef CONFIG_SYS_DDR_RAW_TIMING
|
||||
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
|
||||
puts("Initializing DDR....\n");
|
||||
dram_size = fsl_ddr_sdram();
|
||||
#else
|
||||
dram_size = fsl_ddr_sdram_size();
|
||||
#endif
|
||||
#else
|
||||
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
|
||||
puts("Initialzing DDR using fixed setting\n");
|
||||
dram_size = fixed_sdram();
|
||||
#else
|
||||
gd->ram_size = 0x80000000;
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
#endif
|
||||
erratum_a008850_post();
|
||||
|
||||
#ifdef CONFIG_FSL_DEEP_SLEEP
|
||||
fsl_dp_ddr_restore();
|
||||
#endif
|
||||
|
||||
gd->ram_size = dram_size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,116 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DDR_H__
|
||||
#define __DDR_H__
|
||||
|
||||
extern void erratum_a008850_post(void);
|
||||
|
||||
struct board_specific_parameters {
|
||||
u32 n_ranks;
|
||||
u32 datarate_mhz_high;
|
||||
u32 rank_gb;
|
||||
u32 clk_adjust;
|
||||
u32 wrlvl_start;
|
||||
u32 wrlvl_ctl_2;
|
||||
u32 wrlvl_ctl_3;
|
||||
u32 cpo_override;
|
||||
u32 write_data_delay;
|
||||
u32 force_2t;
|
||||
};
|
||||
|
||||
/*
|
||||
* These tables contain all valid speeds we want to override with board
|
||||
* specific parameters. datarate_mhz_high values need to be in ascending order
|
||||
* for each n_ranks group.
|
||||
*/
|
||||
static const struct board_specific_parameters udimm0[] = {
|
||||
/*
|
||||
* memory controller 0
|
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
|
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
|
||||
*/
|
||||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
{1, 1666, 0, 12, 7, 0x07090800, 0x00000000,},
|
||||
{1, 1900, 0, 12, 7, 0x07090800, 0x00000000,},
|
||||
{1, 2200, 0, 12, 7, 0x07090800, 0x00000000,},
|
||||
#endif
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_specific_parameters *udimms[] = {
|
||||
udimm0,
|
||||
};
|
||||
|
||||
#ifndef CONFIG_SYS_DDR_RAW_TIMING
|
||||
fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {
|
||||
.cs[0].bnds = 0x0000007F,
|
||||
.cs[1].bnds = 0,
|
||||
.cs[2].bnds = 0,
|
||||
.cs[3].bnds = 0,
|
||||
.cs[0].config = 0x80040322,
|
||||
.cs[0].config_2 = 0,
|
||||
.cs[1].config = 0,
|
||||
.cs[1].config_2 = 0,
|
||||
.cs[2].config = 0,
|
||||
.cs[3].config = 0,
|
||||
.timing_cfg_3 = 0x010C1000,
|
||||
.timing_cfg_0 = 0x91550018,
|
||||
.timing_cfg_1 = 0xBBB48C42,
|
||||
.timing_cfg_2 = 0x0048C111,
|
||||
.ddr_sdram_cfg = 0xC50C0008,
|
||||
.ddr_sdram_cfg_2 = 0x00401100,
|
||||
.ddr_sdram_cfg_3 = 0,
|
||||
.ddr_sdram_mode = 0x03010210,
|
||||
.ddr_sdram_mode_2 = 0,
|
||||
.ddr_sdram_mode_3 = 0x00010210,
|
||||
.ddr_sdram_mode_4 = 0,
|
||||
.ddr_sdram_mode_5 = 0x00010210,
|
||||
.ddr_sdram_mode_6 = 0,
|
||||
.ddr_sdram_mode_7 = 0x00010210,
|
||||
.ddr_sdram_mode_8 = 0,
|
||||
.ddr_sdram_mode_9 = 0x00000500,
|
||||
.ddr_sdram_mode_10 = 0x04000000,
|
||||
.ddr_sdram_mode_11 = 0x00000400,
|
||||
.ddr_sdram_mode_12 = 0x04000000,
|
||||
.ddr_sdram_mode_13 = 0x00000400,
|
||||
.ddr_sdram_mode_14 = 0x04000000,
|
||||
.ddr_sdram_mode_15 = 0x00000400,
|
||||
.ddr_sdram_mode_16 = 0x04000000,
|
||||
.ddr_sdram_interval = 0x18600618,
|
||||
.ddr_data_init = 0xDEADBEEF,
|
||||
.ddr_sdram_clk_cntl = 0x03000000,
|
||||
.ddr_init_addr = 0,
|
||||
.ddr_init_ext_addr = 0,
|
||||
.timing_cfg_4 = 0x00000002,
|
||||
.timing_cfg_5 = 0x03401400,
|
||||
.timing_cfg_6 = 0,
|
||||
.timing_cfg_7 = 0x13300000,
|
||||
.timing_cfg_8 = 0x02115600,
|
||||
.timing_cfg_9 = 0,
|
||||
.ddr_zq_cntl = 0x8A090705,
|
||||
.ddr_wrlvl_cntl = 0x8675F607,
|
||||
.ddr_wrlvl_cntl_2 = 0x07090800,
|
||||
.ddr_wrlvl_cntl_3 = 0,
|
||||
.ddr_sr_cntr = 0,
|
||||
.ddr_sdram_rcw_1 = 0,
|
||||
.ddr_sdram_rcw_2 = 0,
|
||||
.ddr_cdr1 = 0x80040000,
|
||||
.ddr_cdr2 = 0x0000A181,
|
||||
.dq_map_0 = 0,
|
||||
.dq_map_1 = 0,
|
||||
.dq_map_2 = 0,
|
||||
.dq_map_3 = 0,
|
||||
.debug[28] = 0x00700046,
|
||||
|
||||
};
|
||||
|
||||
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
|
||||
{1550, 1650, &ddr_cfg_regs_1600},
|
||||
{0, 0, NULL}
|
||||
};
|
||||
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,76 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <netdev.h>
|
||||
#include <fm_eth.h>
|
||||
#include <fsl_dtsec.h>
|
||||
#include <fsl_mdio.h>
|
||||
#include <malloc.h>
|
||||
|
||||
#include "../common/fman.h"
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
int i;
|
||||
struct memac_mdio_info dtsec_mdio_info;
|
||||
struct memac_mdio_info tgec_mdio_info;
|
||||
struct mii_dev *dev;
|
||||
u32 srds_s1;
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
|
||||
srds_s1 = in_be32(&gur->rcwsr[4]) &
|
||||
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
|
||||
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
dtsec_mdio_info.regs =
|
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
|
||||
|
||||
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
|
||||
|
||||
/* Register the 1G MDIO bus */
|
||||
fm_memac_mdio_init(bis, &dtsec_mdio_info);
|
||||
|
||||
tgec_mdio_info.regs =
|
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
|
||||
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
|
||||
|
||||
/* Register the 10G MDIO bus */
|
||||
fm_memac_mdio_init(bis, &tgec_mdio_info);
|
||||
|
||||
/* Set the two on-board RGMII PHY address */
|
||||
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
|
||||
|
||||
/* QSGMII on lane B, MAC 1/2/5/6 */
|
||||
fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);
|
||||
|
||||
switch (srds_s1) {
|
||||
case 0x1455:
|
||||
break;
|
||||
default:
|
||||
printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n",
|
||||
srds_s1);
|
||||
break;
|
||||
}
|
||||
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
|
||||
fm_info_set_mdio(i, dev);
|
||||
|
||||
/* XFI on lane A, MAC 9 */
|
||||
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
|
||||
fm_info_set_mdio(FM1_10GEC1, dev);
|
||||
|
||||
cpu_eth_init(bis);
|
||||
#endif
|
||||
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
@@ -0,0 +1,331 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch-fsl-layerscape/fsl_icid.h>
|
||||
#include <fdt_support.h>
|
||||
#include <hwconfig.h>
|
||||
#include <ahci.h>
|
||||
#include <mmc.h>
|
||||
#include <scsi.h>
|
||||
#include <fm_eth.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <fsl_ifc.h>
|
||||
#include <fsl_sec.h>
|
||||
#include "cpld.h"
|
||||
#ifdef CONFIG_U_QE
|
||||
#include <fsl_qe.h>
|
||||
#endif
|
||||
#include <asm/arch/ppa.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_TFABOOT
|
||||
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
|
||||
{
|
||||
"nor",
|
||||
CONFIG_SYS_NOR_CSPR,
|
||||
CONFIG_SYS_NOR_CSPR_EXT,
|
||||
CONFIG_SYS_NOR_AMASK,
|
||||
CONFIG_SYS_NOR_CSOR,
|
||||
{
|
||||
CONFIG_SYS_NOR_FTIM0,
|
||||
CONFIG_SYS_NOR_FTIM1,
|
||||
CONFIG_SYS_NOR_FTIM2,
|
||||
CONFIG_SYS_NOR_FTIM3
|
||||
},
|
||||
|
||||
},
|
||||
{
|
||||
"nand",
|
||||
CONFIG_SYS_NAND_CSPR,
|
||||
CONFIG_SYS_NAND_CSPR_EXT,
|
||||
CONFIG_SYS_NAND_AMASK,
|
||||
CONFIG_SYS_NAND_CSOR,
|
||||
{
|
||||
CONFIG_SYS_NAND_FTIM0,
|
||||
CONFIG_SYS_NAND_FTIM1,
|
||||
CONFIG_SYS_NAND_FTIM2,
|
||||
CONFIG_SYS_NAND_FTIM3
|
||||
},
|
||||
},
|
||||
{
|
||||
"cpld",
|
||||
CONFIG_SYS_CPLD_CSPR,
|
||||
CONFIG_SYS_CPLD_CSPR_EXT,
|
||||
CONFIG_SYS_CPLD_AMASK,
|
||||
CONFIG_SYS_CPLD_CSOR,
|
||||
{
|
||||
CONFIG_SYS_CPLD_FTIM0,
|
||||
CONFIG_SYS_CPLD_FTIM1,
|
||||
CONFIG_SYS_CPLD_FTIM2,
|
||||
CONFIG_SYS_CPLD_FTIM3
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
|
||||
{
|
||||
"nand",
|
||||
CONFIG_SYS_NAND_CSPR,
|
||||
CONFIG_SYS_NAND_CSPR_EXT,
|
||||
CONFIG_SYS_NAND_AMASK,
|
||||
CONFIG_SYS_NAND_CSOR,
|
||||
{
|
||||
CONFIG_SYS_NAND_FTIM0,
|
||||
CONFIG_SYS_NAND_FTIM1,
|
||||
CONFIG_SYS_NAND_FTIM2,
|
||||
CONFIG_SYS_NAND_FTIM3
|
||||
},
|
||||
},
|
||||
{
|
||||
"nor",
|
||||
CONFIG_SYS_NOR_CSPR,
|
||||
CONFIG_SYS_NOR_CSPR_EXT,
|
||||
CONFIG_SYS_NOR_AMASK,
|
||||
CONFIG_SYS_NOR_CSOR,
|
||||
{
|
||||
CONFIG_SYS_NOR_FTIM0,
|
||||
CONFIG_SYS_NOR_FTIM1,
|
||||
CONFIG_SYS_NOR_FTIM2,
|
||||
CONFIG_SYS_NOR_FTIM3
|
||||
},
|
||||
},
|
||||
{
|
||||
"cpld",
|
||||
CONFIG_SYS_CPLD_CSPR,
|
||||
CONFIG_SYS_CPLD_CSPR_EXT,
|
||||
CONFIG_SYS_CPLD_AMASK,
|
||||
CONFIG_SYS_CPLD_CSOR,
|
||||
{
|
||||
CONFIG_SYS_CPLD_FTIM0,
|
||||
CONFIG_SYS_CPLD_FTIM1,
|
||||
CONFIG_SYS_CPLD_FTIM2,
|
||||
CONFIG_SYS_CPLD_FTIM3
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
|
||||
{
|
||||
enum boot_src src = get_boot_src();
|
||||
|
||||
if (src == BOOT_SOURCE_IFC_NAND)
|
||||
regs_info->regs = ifc_cfg_nand_boot;
|
||||
else
|
||||
regs_info->regs = ifc_cfg_nor_boot;
|
||||
regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
|
||||
}
|
||||
|
||||
#endif
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
fsl_lsch2_early_init_f();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
#ifdef CONFIG_TFABOOT
|
||||
enum boot_src src = get_boot_src();
|
||||
#endif
|
||||
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
|
||||
#ifndef CONFIG_SD_BOOT
|
||||
u8 cfg_rcw_src1, cfg_rcw_src2;
|
||||
u16 cfg_rcw_src;
|
||||
#endif
|
||||
u8 sd1refclk_sel;
|
||||
|
||||
printf("Board: LS1043ARDB, boot from ");
|
||||
|
||||
#ifdef CONFIG_TFABOOT
|
||||
if (src == BOOT_SOURCE_SD_MMC)
|
||||
puts("SD\n");
|
||||
else {
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
puts("SD\n");
|
||||
#else
|
||||
cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
|
||||
cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
|
||||
cpld_rev_bit(&cfg_rcw_src1);
|
||||
cfg_rcw_src = cfg_rcw_src1;
|
||||
cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
|
||||
|
||||
if (cfg_rcw_src == 0x25)
|
||||
printf("vBank %d\n", CPLD_READ(vbank));
|
||||
else if (cfg_rcw_src == 0x106)
|
||||
puts("NAND\n");
|
||||
else
|
||||
printf("Invalid setting of SW4\n");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TFABOOT
|
||||
}
|
||||
#endif
|
||||
printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
|
||||
CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
|
||||
|
||||
puts("SERDES Reference Clocks:\n");
|
||||
sd1refclk_sel = CPLD_READ(sd1refclk_sel);
|
||||
printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
|
||||
erratum_a010315();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_IFC
|
||||
init_final_memctl_regs();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NXP_ESBC
|
||||
/* In case of Secure Boot, the IBR configures the SMMU
|
||||
* to allow only Secure transactions.
|
||||
* SMMU must be reset in bypass mode.
|
||||
* Set the ClientPD bit and Clear the USFCFG Bit
|
||||
*/
|
||||
u32 val;
|
||||
val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
|
||||
out_le32(SMMU_SCR0, val);
|
||||
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
|
||||
out_le32(SMMU_NSCR0, val);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_CAAM
|
||||
sec_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LS_PPA
|
||||
ppa_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_U_QE
|
||||
u_qe_init();
|
||||
#endif
|
||||
/* invert AQR105 IRQ pins polarity */
|
||||
out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int config_board_mux(void)
|
||||
{
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
u32 usb_pwrfault;
|
||||
|
||||
if (hwconfig("qe-hdlc")) {
|
||||
out_be32(&scfg->rcwpmuxcr0,
|
||||
(in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
|
||||
printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
|
||||
in_be32(&scfg->rcwpmuxcr0));
|
||||
} else {
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
out_be32(&scfg->rcwpmuxcr0, 0x3333);
|
||||
out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
|
||||
usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
|
||||
SCFG_USBPWRFAULT_USB3_SHIFT) |
|
||||
(SCFG_USBPWRFAULT_DEDICATED <<
|
||||
SCFG_USBPWRFAULT_USB2_SHIFT) |
|
||||
(SCFG_USBPWRFAULT_SHARED <<
|
||||
SCFG_USBPWRFAULT_USB1_SHIFT);
|
||||
out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
|
||||
#endif
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MISC_INIT_R)
|
||||
int misc_init_r(void)
|
||||
{
|
||||
config_board_mux();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void fdt_del_qe(void *blob)
|
||||
{
|
||||
int nodeoff = 0;
|
||||
|
||||
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
|
||||
"fsl,qe")) >= 0) {
|
||||
fdt_del_node(blob, nodeoff);
|
||||
}
|
||||
}
|
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u64 base[CONFIG_NR_DRAM_BANKS];
|
||||
u64 size[CONFIG_NR_DRAM_BANKS];
|
||||
|
||||
/* fixup DT for the two DDR banks */
|
||||
base[0] = gd->bd->bi_dram[0].start;
|
||||
size[0] = gd->bd->bi_dram[0].size;
|
||||
base[1] = gd->bd->bi_dram[1].start;
|
||||
size[1] = gd->bd->bi_dram[1].size;
|
||||
|
||||
fdt_fixup_memory_banks(blob, base, size, 2);
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
fdt_fixup_fman_ethernet(blob);
|
||||
#endif
|
||||
|
||||
fdt_fixup_icid(blob);
|
||||
|
||||
/*
|
||||
* qe-hdlc and usb multi-use the pins,
|
||||
* when set hwconfig to qe-hdlc, delete usb node.
|
||||
*/
|
||||
if (hwconfig("qe-hdlc"))
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
fdt_del_node_and_alias(blob, "usb1");
|
||||
#endif
|
||||
/*
|
||||
* qe just support qe-uart and qe-hdlc,
|
||||
* if qe-uart and qe-hdlc are not set in hwconfig,
|
||||
* delete qe node.
|
||||
*/
|
||||
if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
|
||||
fdt_del_qe(blob);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u8 flash_read8(void *addr)
|
||||
{
|
||||
return __raw_readb(addr + 1);
|
||||
}
|
||||
|
||||
void flash_write16(u16 val, void *addr)
|
||||
{
|
||||
u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
|
||||
|
||||
__raw_writew(shftval, addr);
|
||||
}
|
||||
|
||||
u16 flash_read16(void *addr)
|
||||
{
|
||||
u16 val = __raw_readw(addr);
|
||||
|
||||
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,14 @@
|
||||
#Configure Scratch register
|
||||
09570600 00000000
|
||||
09570604 10000000
|
||||
#Alt base register
|
||||
09570158 00001000
|
||||
#Disable CCI barrier tranaction
|
||||
09570178 0000e010
|
||||
09180000 00000008
|
||||
#USB PHY frequency sel
|
||||
09570418 0000009e
|
||||
0957041c 0000009e
|
||||
09570420 0000009e
|
||||
#flush PBI data
|
||||
096100c0 000fffff
|
||||
@@ -0,0 +1,7 @@
|
||||
#PBL preamble and RCW header
|
||||
aa55aa55 01ee0100
|
||||
# serdes protocol
|
||||
08100010 0a000000 00000000 00000000
|
||||
14550002 80004012 e0106000 c1002000
|
||||
00000000 00000000 00000000 00038800
|
||||
00000000 00001100 00000096 00000001
|
||||
@@ -0,0 +1,7 @@
|
||||
#PBL preamble and RCW header
|
||||
aa55aa55 01ee0100
|
||||
# RCW
|
||||
08100010 0a000000 00000000 00000000
|
||||
14550002 80004012 60040000 c1002000
|
||||
00000000 00000000 00000000 00038800
|
||||
00000000 00001100 00000096 00000001
|
||||
Reference in New Issue
Block a user