GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,17 @@
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if TARGET_LS1046AFRWY
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config SYS_BOARD
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default "ls1046afrwy"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1046afrwy"
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source "board/freescale/common/Kconfig"
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endif
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@@ -0,0 +1,7 @@
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LS1046AFRWY BOARD
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M: Pramod Kumar <pramod.kumar_1@nxp.com>
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S: Maintained
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F: board/freescale/ls1046afrwy/
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F: board/freescale/ls1046afrwy/ls1046afrwy.c
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F: include/configs/ls1046afrwy.h
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F: configs/ls1046afrwy_tfa_defconfig
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@@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2019 NXP
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obj-y += ddr.o
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obj-y += ls1046afrwy.o
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obj-$(CONFIG_NET) += eth.o
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@@ -0,0 +1,76 @@
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Overview
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--------
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The LS1046A Freeway Board (iFRWY) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS1046A
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LayerScape Architecture processor. The FRWY-LS1046A provides SW development
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platform for the Freescale LS1046A processor series, with a complete
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debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant.
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LS1046A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
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SoC overview.
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FRWY-LS1046A board Overview
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-----------------------
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- SERDES1 Connections, 4 lanes supporting:
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- Lane0: Unused
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- Lane1: Unused
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- Lane2: QSGMII
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- Lane3: Unused
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- SERDES2 Connections, 4 lanes supporting:
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- Lane0: Unused
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- Lane1: PCIe3 with PCIe x1 slot
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- Lane2: Unused
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- Lane3: PCIe3 with PCIe x1 slot
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- DDR Controller
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- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
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-IFC/Local Bus
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- One 512 MB NAND flash with ECC support
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- USB 3.0
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- Two Type A port
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- SDHC: connects directly to a full microSD slot
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- QSPI: 64 MB high-speed flash Memory for boot code and storage
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- 4 I2C controllers
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- UART
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- Two 4-pin serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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Start Address End Address Description Size
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0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
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0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
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0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
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0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
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0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
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0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
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0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
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0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
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0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
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0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
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0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
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0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
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0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
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0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
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QSPI flash map:
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Start Address End Address Description Size
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0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2 1MB
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0x00_4010_0000 - 0x00_404F_FFFF FIP Image
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(Bl31 + BL32(optee.
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bin) + Bl33(uboot)
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+ headers for secure
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boot) 4MB
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0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env 1MB
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0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers 3MB
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0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB
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0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB
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0x00_409C_0000 - 0x00_409F_FFFF Reserved 256KB
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0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB
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Booting Options
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---------------
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a) QSPI boot
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b) microSD boot
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@@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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DECLARE_GLOBAL_DATA_PTR;
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int fsl_initdram(void)
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{
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gd->ram_size = tfa_get_dram_size();
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if (!gd->ram_size)
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gd->ram_size = fsl_ddr_sdram_size();
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return 0;
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}
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@@ -0,0 +1,114 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <netdev.h>
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#include <fm_eth.h>
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#include <fsl_dtsec.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include "../common/fman.h"
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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struct memac_mdio_info dtsec_mdio_info;
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struct mii_dev *dev;
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u32 srds_s1;
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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dtsec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fm_memac_mdio_init(bis, &dtsec_mdio_info);
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/* QSGMII on lane B, MAC 6/5/10/1 */
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fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);
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switch (srds_s1) {
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case 0x3040:
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break;
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default:
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printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n",
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srds_s1);
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break;
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}
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dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
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fm_info_set_mdio(FM1_DTSEC6, dev);
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fm_info_set_mdio(FM1_DTSEC5, dev);
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fm_info_set_mdio(FM1_DTSEC10, dev);
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fm_info_set_mdio(FM1_DTSEC1, dev);
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cpu_eth_init(bis);
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#endif
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return pci_eth_init(bis);
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}
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#ifdef CONFIG_FMAN_ENET
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int fdt_update_ethernet_dt(void *blob)
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{
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u32 srds_s1;
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int i, prop;
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int offset, nodeoff;
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const char *path;
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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/* Cycle through all aliases */
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for (prop = 0; ; prop++) {
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const char *name;
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/* FDT might have been edited, recompute the offset */
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offset = fdt_first_property_offset(blob,
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fdt_path_offset(blob,
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"/aliases")
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);
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/* Select property number 'prop' */
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for (i = 0; i < prop; i++)
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offset = fdt_next_property_offset(blob, offset);
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if (offset < 0)
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break;
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path = fdt_getprop_by_offset(blob, offset, &name, NULL);
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nodeoff = fdt_path_offset(blob, path);
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switch (srds_s1) {
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case 0x3040:
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if (!strcmp(name, "ethernet1"))
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fdt_status_disabled(blob, nodeoff);
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if (!strcmp(name, "ethernet2"))
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fdt_status_disabled(blob, nodeoff);
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if (!strcmp(name, "ethernet3"))
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fdt_status_disabled(blob, nodeoff);
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if (!strcmp(name, "ethernet6"))
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fdt_status_disabled(blob, nodeoff);
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break;
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default:
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printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n",
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__func__, srds_s1);
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break;
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}
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}
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return 0;
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}
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#endif
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@@ -0,0 +1,223 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <i2c.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <asm/arch-fsl-layerscape/fsl_icid.h>
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#include <hwconfig.h>
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#include <ahci.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <fm_eth.h>
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#include <fsl_csu.h>
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#include <fsl_esdhc.h>
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#include <fsl_sec.h>
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#include <fsl_dspi.h>
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#define LS1046A_PORSR1_REG 0x1EE0000
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#define BOOT_SRC_SD 0x20000000
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#define BOOT_SRC_MASK 0xFF800000
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#define BOARD_REV_GPIO 13
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#define USB2_SEL_MASK 0x00000100
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#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
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(((word) & 0x00ff0000) >> 8) | \
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(((word) & 0x0000ff00) << 8) | \
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(((word) & 0x000000ff) << 24))
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#define SPI_MCR_REG 0x2100000
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DECLARE_GLOBAL_DATA_PTR;
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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static inline void demux_select_usb2(void)
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{
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u32 val;
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struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
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val = in_be32(&pgpio->gpdir);
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val |= USB2_SEL_MASK;
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out_be32(&pgpio->gpdir, val);
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val = in_be32(&pgpio->gpdat);
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val |= USB2_SEL_MASK;
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out_be32(&pgpio->gpdat, val);
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}
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static inline void set_spi_cs_signal_inactive(void)
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{
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/* default: all CS signals inactive state is high */
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uint mcr_val;
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uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
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DSPI_MCR_CRXF | DSPI_MCR_CTXF;
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mcr_val = in_be32(SPI_MCR_REG);
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mcr_val |= DSPI_MCR_HALT;
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out_be32(SPI_MCR_REG, mcr_val);
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out_be32(SPI_MCR_REG, mcr_cfg_val);
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mcr_val = in_be32(SPI_MCR_REG);
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mcr_val &= ~DSPI_MCR_HALT;
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out_be32(SPI_MCR_REG, mcr_val);
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}
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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static inline uint8_t get_board_version(void)
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{
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u8 val;
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struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
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val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03;
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return val;
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}
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int checkboard(void)
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{
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static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
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u32 boot_src;
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u8 rev;
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rev = get_board_version();
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switch (rev) {
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case 0x00:
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puts("Board: LS1046AFRWY, Rev: A, boot from ");
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break;
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case 0x01:
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puts("Board: LS1046AFRWY, Rev: B, boot from ");
|
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break;
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default:
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puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
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break;
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}
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boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
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if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
|
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puts("SD\n");
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else
|
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puts("QSPI\n");
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printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
|
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return 0;
|
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}
|
||||
|
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int board_init(void)
|
||||
{
|
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#ifdef CONFIG_NXP_ESBC
|
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/*
|
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* In case of Secure Boot, the IBR configures the SMMU
|
||||
* to allow only Secure transactions.
|
||||
* SMMU must be reset in bypass mode.
|
||||
* Set the ClientPD bit and Clear the USFCFG Bit
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*/
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u32 val;
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val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
|
||||
out_le32(SMMU_SCR0, val);
|
||||
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
|
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out_le32(SMMU_NSCR0, val);
|
||||
#endif
|
||||
|
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#ifdef CONFIG_FSL_CAAM
|
||||
sec_init();
|
||||
#endif
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||||
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_setup_core_volt(u32 vdd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void config_board_mux(void)
|
||||
{
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
u32 usb_pwrfault;
|
||||
/*
|
||||
* USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
|
||||
* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
|
||||
*/
|
||||
out_be32(&scfg->rcwpmuxcr0, 0x3300);
|
||||
#ifdef CONFIG_HAS_FSL_IIC3
|
||||
/* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
|
||||
out_be32(&scfg->rcwpmuxcr0, 0x0000);
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||||
#endif
|
||||
out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
|
||||
usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
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||||
SCFG_USBPWRFAULT_USB3_SHIFT) |
|
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(SCFG_USBPWRFAULT_DEDICATED <<
|
||||
SCFG_USBPWRFAULT_USB2_SHIFT) |
|
||||
(SCFG_USBPWRFAULT_SHARED <<
|
||||
SCFG_USBPWRFAULT_USB1_SHIFT);
|
||||
out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
|
||||
#ifndef CONFIG_HAS_FSL_IIC3
|
||||
/*
|
||||
* LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
|
||||
* to select I2C3_USB2_SEL_IO
|
||||
* I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
|
||||
* I2C3 header (default)
|
||||
* I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
|
||||
* USB2 port
|
||||
* programmed to select USB2 by setting GPIO3_23 output to one
|
||||
*/
|
||||
demux_select_usb2();
|
||||
#endif
|
||||
#endif
|
||||
set_spi_cs_signal_inactive();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MISC_INIT_R
|
||||
int misc_init_r(void)
|
||||
{
|
||||
config_board_mux();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u64 base[CONFIG_NR_DRAM_BANKS];
|
||||
u64 size[CONFIG_NR_DRAM_BANKS];
|
||||
|
||||
/* fixup DT for the two DDR banks */
|
||||
base[0] = gd->bd->bi_dram[0].start;
|
||||
size[0] = gd->bd->bi_dram[0].size;
|
||||
base[1] = gd->bd->bi_dram[1].start;
|
||||
size[1] = gd->bd->bi_dram[1].size;
|
||||
|
||||
fdt_fixup_memory_banks(blob, base, size, 2);
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
fdt_fixup_fman_ethernet(blob);
|
||||
#endif
|
||||
|
||||
fdt_fixup_icid(blob);
|
||||
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user