GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,31 @@
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if TARGET_LS1046ARDB
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config SYS_BOARD
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default "ls1046ardb"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1046ardb"
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if FSL_LS_PPA
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config SYS_LS_PPA_FW_ADDR
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hex "PPA Firmware Addr"
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default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
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default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
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if CHAIN_OF_TRUST
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config SYS_LS_PPA_ESBC_ADDR
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hex "PPA Firmware HDR Addr"
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default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
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default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
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endif
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endif
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source "board/freescale/common/Kconfig"
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endif
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@@ -0,0 +1,23 @@
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LS1046A BOARD
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M: Mingkai Hu <mingkai.hu@nxp.com>
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M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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S: Maintained
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F: board/freescale/ls1046ardb/
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F: board/freescale/ls1046ardb/ls1046ardb.c
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F: include/configs/ls1046ardb.h
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F: configs/ls1046ardb_qspi_defconfig
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F: configs/ls1046ardb_qspi_spl_defconfig
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F: configs/ls1046ardb_sdcard_defconfig
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F: configs/ls1046ardb_emmc_defconfig
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F: configs/ls1046ardb_tfa_defconfig
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F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
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LS1046A_SECURE_BOOT BOARD
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M: Ruchika Gupta <ruchika.gupta@nxp.com>
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S: Maintained
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F: configs/ls1046ardb_SECURE_BOOT_defconfig
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F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
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M: Sumit Garg <sumit.garg@nxp.com>
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S: Maintained
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F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
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@@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2016 Freescale Semiconductor
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obj-y += ddr.o
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obj-y += ls1046ardb.o
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_NET) += eth.o
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obj-y += cpld.o
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endif
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@@ -0,0 +1,76 @@
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Overview
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--------
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The LS1046A Reference Design Board (RDB) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS1046A
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LayerScape Architecture processor. The LS1046ARDB provides SW development
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platform for the Freescale LS1046A processor series, with a complete
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debugging environment. The LS1046A RDB is lead-free and RoHS-compliant.
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LS1046A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
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SoC overview.
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LS1046ARDB board Overview
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-----------------------
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- SERDES1 Connections, 4 lanes supporting:
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- Lane0: XFI with x1 RJ45 connector
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- Lane1: XFI Cage
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- Lane2: SGMII.5
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- Lane3: SGMII.6
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- SERDES2 Connections, 4 lanes supporting:
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- Lane0: PCIe1 with miniPCIe slot
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- Lane1: PCIe2 with PCIe x2 slot
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- Lane2: PCIe3 with PCIe x4 slot
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- Lane3: SATA
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- DDR Controller
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- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
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-IFC/Local Bus
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- One 512 MB NAND flash with ECC support
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- CPLD connection
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- USB 3.0
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- one Type A port, one Micro-AB port
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- SDHC: connects directly to a full SD/MMC slot
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- DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
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- 4 I2C controllers
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- UART
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- Two 4-pin serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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Start Address End Address Description Size
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0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
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0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
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0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
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0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
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0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
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0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
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0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
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0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
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0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
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0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
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0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
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0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
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0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
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0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
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QSPI flash map:
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Start Address End Address Description Size
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0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB
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0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB
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0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB
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0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB
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0x00_4060_0000 - 0x00_408F_FFFF Secure boot header
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+ bootscript 3MB
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0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB
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0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB
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0x00_4098_0000 - 0x00_40FF_FFFF Reserved 6MB
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0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB
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Booting Options
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---------------
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a) QSPI boot
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b) SD boot
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c) eMMC boot
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@@ -0,0 +1,166 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor
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*
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* Freescale LS1046ARDB board-specific CPLD controlling supports.
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include "cpld.h"
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u8 cpld_read(unsigned int reg)
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{
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void *p = (void *)CONFIG_SYS_CPLD_BASE;
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return in_8(p + reg);
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}
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void cpld_write(unsigned int reg, u8 value)
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{
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void *p = (void *)CONFIG_SYS_CPLD_BASE;
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out_8(p + reg, value);
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}
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/* Set the boot bank to the alternate bank */
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void cpld_set_altbank(void)
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{
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u16 reg = CPLD_CFG_RCW_SRC_QSPI;
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u8 reg4 = CPLD_READ(soft_mux_on);
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u8 reg5 = (u8)(reg >> 1);
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u8 reg6 = (u8)(reg & 1);
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u8 reg7 = CPLD_READ(vbank);
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cpld_rev_bit(®5);
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CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
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CPLD_WRITE(cfg_rcw_src1, reg5);
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CPLD_WRITE(cfg_rcw_src2, reg6);
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reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
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CPLD_WRITE(vbank, reg7);
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CPLD_WRITE(system_rst, 1);
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}
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/* Set the boot bank to the default bank */
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void cpld_set_defbank(void)
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{
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u16 reg = CPLD_CFG_RCW_SRC_QSPI;
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u8 reg4 = CPLD_READ(soft_mux_on);
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u8 reg5 = (u8)(reg >> 1);
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u8 reg6 = (u8)(reg & 1);
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cpld_rev_bit(®5);
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CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
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CPLD_WRITE(cfg_rcw_src1, reg5);
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CPLD_WRITE(cfg_rcw_src2, reg6);
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CPLD_WRITE(vbank, 0);
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CPLD_WRITE(system_rst, 1);
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}
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void cpld_set_sd(void)
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{
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u16 reg = CPLD_CFG_RCW_SRC_SD;
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u8 reg5 = (u8)(reg >> 1);
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u8 reg6 = (u8)(reg & 1);
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cpld_rev_bit(®5);
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CPLD_WRITE(soft_mux_on, 1);
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CPLD_WRITE(cfg_rcw_src1, reg5);
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CPLD_WRITE(cfg_rcw_src2, reg6);
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CPLD_WRITE(system_rst, 1);
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}
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void cpld_select_core_volt(bool en_0v9)
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{
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u8 reg17 = en_0v9;
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CPLD_WRITE(vdd_en, 1);
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CPLD_WRITE(vdd_sel, reg17);
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}
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#ifdef DEBUG
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static void cpld_dump_regs(void)
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{
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printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
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printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
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printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
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printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
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printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
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printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
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printf("vbank = %x\n", CPLD_READ(vbank));
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printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
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printf("uart_sel = %x\n", CPLD_READ(uart_sel));
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printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
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printf("rgmii_1588_sel = %x\n", CPLD_READ(rgmii_1588_sel));
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printf("1588_clk_sel = %x\n", CPLD_READ(reg_1588_clk_sel));
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printf("status_led = %x\n", CPLD_READ(status_led));
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printf("sd_emmc = %x\n", CPLD_READ(sd_emmc));
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printf("vdd_en = %x\n", CPLD_READ(vdd_en));
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printf("vdd_sel = %x\n", CPLD_READ(vdd_sel));
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putc('\n');
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}
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#endif
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void cpld_rev_bit(unsigned char *value)
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{
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u8 rev_val, val;
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int i;
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val = *value;
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rev_val = val & 1;
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for (i = 1; i <= 7; i++) {
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val >>= 1;
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rev_val <<= 1;
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rev_val |= val & 1;
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}
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*value = rev_val;
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}
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int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int rc = 0;
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if (argc <= 1)
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return cmd_usage(cmdtp);
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if (strcmp(argv[1], "reset") == 0) {
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if (strcmp(argv[2], "altbank") == 0)
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cpld_set_altbank();
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else if (strcmp(argv[2], "sd") == 0)
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cpld_set_sd();
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else
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cpld_set_defbank();
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#ifdef DEBUG
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} else if (strcmp(argv[1], "dump") == 0) {
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cpld_dump_regs();
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#endif
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} else {
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rc = cmd_usage(cmdtp);
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}
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return rc;
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}
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U_BOOT_CMD(
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cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
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"Reset the board or alternate bank",
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"reset: reset to default bank\n"
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"cpld reset altbank: reset to alternate bank\n"
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"cpld reset sd: reset to boot from SD card\n"
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#ifdef DEBUG
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"cpld dump - display the CPLD registers\n"
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#endif
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);
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@@ -0,0 +1,49 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 Freescale Semiconductor
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*/
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#ifndef __CPLD_H__
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#define __CPLD_H__
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/*
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* CPLD register set of LS1046ARDB board-specific.
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* CPLD Revision: V2.1
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*/
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struct cpld_data {
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u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
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u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
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u8 pcba_ver; /* 0x2 - PCBA Revision Register */
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u8 system_rst; /* 0x3 - system reset register */
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u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
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u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */
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u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */
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u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */
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u8 sysclk_sel; /* 0x8 - System clock POR Register */
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u8 uart_sel; /* 0x9 - UART1 Connection Control Register */
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u8 sd1refclk_sel; /* 0xA - */
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u8 rgmii_1588_sel; /* 0xB - */
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u8 reg_1588_clk_sel; /* 0xC - */
|
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u8 status_led; /* 0xD - */
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u8 global_rst; /* 0xE - */
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u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */
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u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */
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u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */
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};
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|
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u8 cpld_read(unsigned int reg);
|
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void cpld_write(unsigned int reg, u8 value);
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void cpld_rev_bit(unsigned char *value);
|
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void cpld_select_core_volt(bool en_0v9);
|
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|
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
|
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#define CPLD_WRITE(reg, value) \
|
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cpld_write(offsetof(struct cpld_data, reg), value)
|
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|
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/* CPLD on IFC */
|
||||
#define CPLD_SW_MUX_BANK_SEL 0x40
|
||||
#define CPLD_BANK_SEL_MASK 0x07
|
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#define CPLD_BANK_SEL_ALTBANK 0x04
|
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#define CPLD_CFG_RCW_SRC_QSPI 0x044
|
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#define CPLD_CFG_RCW_SRC_SD 0x040
|
||||
#endif
|
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@@ -0,0 +1,131 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fsl_ddr_sdram.h>
|
||||
#include <fsl_ddr_dimm_params.h>
|
||||
#include "ddr.h"
|
||||
#ifdef CONFIG_FSL_DEEP_SLEEP
|
||||
#include <fsl_sleep.h>
|
||||
#endif
|
||||
#include <asm/arch/clock.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
||||
dimm_params_t *pdimm,
|
||||
unsigned int ctrl_num)
|
||||
{
|
||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
|
||||
ulong ddr_freq;
|
||||
|
||||
if (ctrl_num > 1) {
|
||||
printf("Not supported controller number %d\n", ctrl_num);
|
||||
return;
|
||||
}
|
||||
if (!pdimm->n_ranks)
|
||||
return;
|
||||
|
||||
if (popts->registered_dimm_en)
|
||||
pbsp = rdimms[0];
|
||||
else
|
||||
pbsp = udimms[0];
|
||||
|
||||
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
|
||||
* freqency and n_banks specified in board_specific_parameters table.
|
||||
*/
|
||||
ddr_freq = get_ddr_freq(0) / 1000000;
|
||||
while (pbsp->datarate_mhz_high) {
|
||||
if (pbsp->n_ranks == pdimm->n_ranks) {
|
||||
if (ddr_freq <= pbsp->datarate_mhz_high) {
|
||||
popts->clk_adjust = pbsp->clk_adjust;
|
||||
popts->wrlvl_start = pbsp->wrlvl_start;
|
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
|
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
|
||||
goto found;
|
||||
}
|
||||
pbsp_highest = pbsp;
|
||||
}
|
||||
pbsp++;
|
||||
}
|
||||
|
||||
if (pbsp_highest) {
|
||||
printf("Error: board specific timing not found for %lu MT/s\n",
|
||||
ddr_freq);
|
||||
printf("Trying to use the highest speed (%u) parameters\n",
|
||||
pbsp_highest->datarate_mhz_high);
|
||||
popts->clk_adjust = pbsp_highest->clk_adjust;
|
||||
popts->wrlvl_start = pbsp_highest->wrlvl_start;
|
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
|
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
|
||||
} else {
|
||||
panic("DIMM is not supported by this board");
|
||||
}
|
||||
found:
|
||||
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
|
||||
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
|
||||
|
||||
popts->data_bus_width = 0; /* 64-bit data bus */
|
||||
popts->bstopre = 0; /* enable auto precharge */
|
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable:
|
||||
* - number of DIMMs installed
|
||||
*/
|
||||
popts->half_strength_driver_enable = 0;
|
||||
/*
|
||||
* Write leveling override
|
||||
*/
|
||||
popts->wrlvl_override = 1;
|
||||
popts->wrlvl_sample = 0xf;
|
||||
|
||||
/*
|
||||
* Rtt and Rtt_WR override
|
||||
*/
|
||||
popts->rtt_override = 0;
|
||||
|
||||
/* Enable ZQ calibration */
|
||||
popts->zq_en = 1;
|
||||
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
|
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
|
||||
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
|
||||
|
||||
/* optimize cpo for erratum A-009942 */
|
||||
popts->cpo_sample = 0x61;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TFABOOT
|
||||
int fsl_initdram(void)
|
||||
{
|
||||
gd->ram_size = tfa_get_dram_size();
|
||||
|
||||
if (!gd->ram_size)
|
||||
gd->ram_size = fsl_ddr_sdram_size();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
int fsl_initdram(void)
|
||||
{
|
||||
phys_size_t dram_size;
|
||||
|
||||
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
|
||||
gd->ram_size = fsl_ddr_sdram_size();
|
||||
|
||||
return 0;
|
||||
#else
|
||||
puts("Initializing DDR....using SPD\n");
|
||||
|
||||
dram_size = fsl_ddr_sdram();
|
||||
#endif
|
||||
|
||||
erratum_a008850_post();
|
||||
|
||||
gd->ram_size = dram_size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DDR_H__
|
||||
#define __DDR_H__
|
||||
|
||||
void erratum_a008850_post(void);
|
||||
|
||||
struct board_specific_parameters {
|
||||
u32 n_ranks;
|
||||
u32 datarate_mhz_high;
|
||||
u32 rank_gb;
|
||||
u32 clk_adjust;
|
||||
u32 wrlvl_start;
|
||||
u32 wrlvl_ctl_2;
|
||||
u32 wrlvl_ctl_3;
|
||||
};
|
||||
|
||||
/*
|
||||
* These tables contain all valid speeds we want to override with board
|
||||
* specific parameters. datarate_mhz_high values need to be in ascending order
|
||||
* for each n_ranks group.
|
||||
*/
|
||||
static const struct board_specific_parameters udimm0[] = {
|
||||
/*
|
||||
* memory controller 0
|
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
|
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
|
||||
*/
|
||||
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
|
||||
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
|
||||
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
|
||||
{2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_specific_parameters *udimms[] = {
|
||||
udimm0,
|
||||
};
|
||||
|
||||
static const struct board_specific_parameters rdimm0[] = {
|
||||
/*
|
||||
* memory controller 0
|
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
|
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
|
||||
*/
|
||||
{2, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,},
|
||||
{2, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,},
|
||||
{2, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,},
|
||||
{1, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,},
|
||||
{1, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,},
|
||||
{1, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_specific_parameters *rdimms[] = {
|
||||
rdimm0,
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,127 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <netdev.h>
|
||||
#include <fm_eth.h>
|
||||
#include <fsl_dtsec.h>
|
||||
#include <fsl_mdio.h>
|
||||
#include <malloc.h>
|
||||
|
||||
#include "../common/fman.h"
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
int i;
|
||||
struct memac_mdio_info dtsec_mdio_info;
|
||||
struct memac_mdio_info tgec_mdio_info;
|
||||
struct mii_dev *dev;
|
||||
u32 srds_s1;
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
|
||||
srds_s1 = in_be32(&gur->rcwsr[4]) &
|
||||
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
|
||||
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
dtsec_mdio_info.regs =
|
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
|
||||
|
||||
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
|
||||
|
||||
/* Register the 1G MDIO bus */
|
||||
fm_memac_mdio_init(bis, &dtsec_mdio_info);
|
||||
|
||||
tgec_mdio_info.regs =
|
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
|
||||
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
|
||||
|
||||
/* Register the 10G MDIO bus */
|
||||
fm_memac_mdio_init(bis, &tgec_mdio_info);
|
||||
|
||||
/* Set the two on-board RGMII PHY address */
|
||||
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
|
||||
|
||||
/* Set the two on-board SGMII PHY address */
|
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
|
||||
|
||||
/* Set the on-board AQ PHY address */
|
||||
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
|
||||
|
||||
switch (srds_s1) {
|
||||
case 0x1133:
|
||||
break;
|
||||
default:
|
||||
printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
|
||||
srds_s1);
|
||||
break;
|
||||
}
|
||||
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
|
||||
fm_info_set_mdio(i, dev);
|
||||
|
||||
/* XFI on lane A, MAC 9 */
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
|
||||
fm_info_set_mdio(FM1_10GEC1, dev);
|
||||
|
||||
cpu_eth_init(bis);
|
||||
#endif
|
||||
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
int fdt_update_ethernet_dt(void *blob)
|
||||
{
|
||||
u32 srds_s1;
|
||||
int i, prop;
|
||||
int offset, nodeoff;
|
||||
const char *path;
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
|
||||
srds_s1 = in_be32(&gur->rcwsr[4]) &
|
||||
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
|
||||
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
/* Cycle through all aliases */
|
||||
for (prop = 0; ; prop++) {
|
||||
const char *name;
|
||||
|
||||
/* FDT might have been edited, recompute the offset */
|
||||
offset = fdt_first_property_offset(blob,
|
||||
fdt_path_offset(blob,
|
||||
"/aliases")
|
||||
);
|
||||
/* Select property number 'prop' */
|
||||
for (i = 0; i < prop; i++)
|
||||
offset = fdt_next_property_offset(blob, offset);
|
||||
|
||||
if (offset < 0)
|
||||
break;
|
||||
|
||||
path = fdt_getprop_by_offset(blob, offset, &name, NULL);
|
||||
nodeoff = fdt_path_offset(blob, path);
|
||||
|
||||
switch (srds_s1) {
|
||||
case 0x1133:
|
||||
if (!strcmp(name, "ethernet0"))
|
||||
fdt_status_disabled(blob, nodeoff);
|
||||
|
||||
if (!strcmp(name, "ethernet1"))
|
||||
fdt_status_disabled(blob, nodeoff);
|
||||
break;
|
||||
default:
|
||||
printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n",
|
||||
__func__, srds_s1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,182 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch/ppa.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch-fsl-layerscape/fsl_icid.h>
|
||||
#include <hwconfig.h>
|
||||
#include <ahci.h>
|
||||
#include <mmc.h>
|
||||
#include <scsi.h>
|
||||
#include <fm_eth.h>
|
||||
#include <fsl_csu.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <power/mc34vr500_pmic.h>
|
||||
#include "cpld.h"
|
||||
#include <fsl_sec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
fsl_lsch2_early_init_f();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
int checkboard(void)
|
||||
{
|
||||
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
|
||||
u8 cfg_rcw_src1, cfg_rcw_src2;
|
||||
u16 cfg_rcw_src;
|
||||
u8 sd1refclk_sel;
|
||||
|
||||
puts("Board: LS1046ARDB, boot from ");
|
||||
|
||||
cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
|
||||
cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
|
||||
cpld_rev_bit(&cfg_rcw_src1);
|
||||
cfg_rcw_src = cfg_rcw_src1;
|
||||
cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
|
||||
|
||||
if (cfg_rcw_src == 0x44)
|
||||
printf("QSPI vBank %d\n", CPLD_READ(vbank));
|
||||
else if (cfg_rcw_src == 0x40)
|
||||
puts("SD\n");
|
||||
else
|
||||
puts("Invalid setting of SW5\n");
|
||||
|
||||
printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
|
||||
CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
|
||||
|
||||
puts("SERDES Reference Clocks:\n");
|
||||
sd1refclk_sel = CPLD_READ(sd1refclk_sel);
|
||||
printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
|
||||
#ifdef CONFIG_NXP_ESBC
|
||||
/*
|
||||
* In case of Secure Boot, the IBR configures the SMMU
|
||||
* to allow only Secure transactions.
|
||||
* SMMU must be reset in bypass mode.
|
||||
* Set the ClientPD bit and Clear the USFCFG Bit
|
||||
*/
|
||||
u32 val;
|
||||
val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
|
||||
out_le32(SMMU_SCR0, val);
|
||||
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
|
||||
out_le32(SMMU_NSCR0, val);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_CAAM
|
||||
sec_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LS_PPA
|
||||
ppa_init();
|
||||
#endif
|
||||
|
||||
/* invert AQR105 IRQ pins polarity */
|
||||
out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_setup_core_volt(u32 vdd)
|
||||
{
|
||||
bool en_0v9;
|
||||
|
||||
en_0v9 = (vdd == 900) ? true : false;
|
||||
cpld_select_core_volt(en_0v9);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int get_serdes_volt(void)
|
||||
{
|
||||
return mc34vr500_get_sw_volt(SW4);
|
||||
}
|
||||
|
||||
int set_serdes_volt(int svdd)
|
||||
{
|
||||
return mc34vr500_set_sw_volt(SW4, svdd);
|
||||
}
|
||||
|
||||
int power_init_board(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = power_mc34vr500_init(0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
setup_chip_volt();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void config_board_mux(void)
|
||||
{
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
u32 usb_pwrfault;
|
||||
|
||||
/* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
|
||||
out_be32(&scfg->rcwpmuxcr0, 0x3300);
|
||||
out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
|
||||
usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
|
||||
SCFG_USBPWRFAULT_USB3_SHIFT) |
|
||||
(SCFG_USBPWRFAULT_DEDICATED <<
|
||||
SCFG_USBPWRFAULT_USB2_SHIFT) |
|
||||
(SCFG_USBPWRFAULT_SHARED <<
|
||||
SCFG_USBPWRFAULT_USB1_SHIFT);
|
||||
out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MISC_INIT_R
|
||||
int misc_init_r(void)
|
||||
{
|
||||
config_board_mux();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u64 base[CONFIG_NR_DRAM_BANKS];
|
||||
u64 size[CONFIG_NR_DRAM_BANKS];
|
||||
|
||||
/* fixup DT for the two DDR banks */
|
||||
base[0] = gd->bd->bi_dram[0].start;
|
||||
size[0] = gd->bd->bi_dram[0].size;
|
||||
base[1] = gd->bd->bi_dram[1].start;
|
||||
size[1] = gd->bd->bi_dram[1].size;
|
||||
|
||||
fdt_fixup_memory_banks(blob, base, size, 2);
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
fdt_fixup_fman_ethernet(blob);
|
||||
#endif
|
||||
|
||||
fdt_fixup_icid(blob);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,22 @@
|
||||
#Configure Scratch register
|
||||
09570600 00000000
|
||||
09570604 10000000
|
||||
#Disable CCI barrier tranaction
|
||||
09570178 0000e010
|
||||
09180000 00000008
|
||||
#USB PHY frequency sel
|
||||
09570418 0000009e
|
||||
0957041c 0000009e
|
||||
09570420 0000009e
|
||||
#Serdes SATA
|
||||
09eb1300 80104e20
|
||||
09eb08dc 00502880
|
||||
#PEX gen3 link
|
||||
09570158 00000300
|
||||
89400890 01048000
|
||||
89500890 01048000
|
||||
89600890 01048000
|
||||
#Alt base register
|
||||
09570158 00001000
|
||||
#flush PBI data
|
||||
096100c0 000fffff
|
||||
@@ -0,0 +1,26 @@
|
||||
#QSPI clk
|
||||
0957015c 40100000
|
||||
#Configure Scratch register
|
||||
09570600 00000000
|
||||
09570604 10000000
|
||||
#Disable CCI barrier tranaction
|
||||
09570178 0000e010
|
||||
09180000 00000008
|
||||
#USB PHY frequency sel
|
||||
09570418 0000009e
|
||||
0957041c 0000009e
|
||||
09570420 0000009e
|
||||
#Serdes SATA
|
||||
09eb1300 80104e20
|
||||
09eb08dc 00502880
|
||||
#PEX gen3 link
|
||||
09570158 00000300
|
||||
89400890 01048000
|
||||
89500890 01048000
|
||||
89600890 01048000
|
||||
#Alt base register
|
||||
09570158 00001000
|
||||
#flush PBI data
|
||||
096100c0 000fffff
|
||||
#Change endianness
|
||||
09550000 000f400c
|
||||
@@ -0,0 +1,7 @@
|
||||
#PBL preamble and RCW header
|
||||
aa55aa55 01ee0100
|
||||
# RCW
|
||||
0c150012 0e000000 00000000 00000000
|
||||
11335559 40000012 60040000 c1000000
|
||||
00000000 00000000 00000000 00238800
|
||||
20124000 00003000 00000096 00000001
|
||||
@@ -0,0 +1,7 @@
|
||||
#PBL preamble and RCW header
|
||||
aa55aa55 01ee0100
|
||||
# RCW
|
||||
0c150010 0e000000 00000000 00000000
|
||||
11335559 40005012 40025000 c1000000
|
||||
00000000 00000000 00000000 00238800
|
||||
20124000 00003101 00000096 00000001
|
||||
@@ -0,0 +1,7 @@
|
||||
#PBL preamble and RCW header
|
||||
aa55aa55 01ee0100
|
||||
# RCW
|
||||
0c150012 0e000000 00000000 00000000
|
||||
11335559 40005012 60040000 c1000000
|
||||
00000000 00000000 00000000 00238800
|
||||
20124000 00003101 00000096 00000001
|
||||
Reference in New Issue
Block a user