GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,35 @@
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if TARGET_LS2080ARDB || TARGET_LS2081ARDB
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config SYS_BOARD
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default "ls2080ardb"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls2080ardb"
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source "board/freescale/common/Kconfig"
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if FSL_LS_PPA
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config SYS_LS_PPA_FW_ADDR
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hex "PPA Firmware Addr"
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default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
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default 0x580400000 if SYS_LS_PPA_FW_IN_XIP
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default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
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if CHAIN_OF_TRUST
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config SYS_LS_PPA_ESBC_ADDR
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hex "PPA Firmware HDR Addr"
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default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
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default 0x580680000 if SYS_LS_PPA_FW_IN_XIP
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default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
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endif
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endif
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source "board/freescale/common/Kconfig"
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endif
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@@ -0,0 +1,31 @@
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LS2080A BOARD
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M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
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S: Maintained
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F: board/freescale/ls2080ardb/
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F: board/freescale/ls2080a/ls2080ardb.c
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F: include/configs/ls2080ardb.h
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F: configs/ls2080ardb_defconfig
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F: configs/ls2080ardb_nand_defconfig
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LS2088A_QSPI-boot BOARD
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M: Priyanka Jain <priyanka.jain@nxp.com>
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M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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S: Maintained
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F: configs/ls2088ardb_qspi_defconfig
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F: configs/ls2088ardb_tfa_defconfig
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F: configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
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LS2081ARDB BOARD
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M: Priyanka Jain <priyanka.jain@nxp.com>
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S: Maintained
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F: configs/ls2081ardb_defconfig
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LS2080A_SECURE_BOOT BOARD
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#M: Saksham Jain <saksham.jain@nxp.freescale.com>
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S: Orphan (since 2018-05)
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F: configs/ls2080ardb_SECURE_BOOT_defconfig
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LS2088A_QSPI_SECURE_BOOT BOARD
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M: Udit Agarwal <udit.agarwal@nxp.com>
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S: Maintained
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F: configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
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@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2015 Freescale Semiconductor
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obj-y += ls2080ardb.o eth_ls2080rdb.o
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obj-y += ddr.o
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@@ -0,0 +1,135 @@
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Overview
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--------
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The LS2080A Reference Design (RDB) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
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Layerscape Architecture processor.
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The LS2081A Reference Design (RDB) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS2081A
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Layerscape Architecture processor.More details in below sections
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LS2080A, LS2088A, LS2081A SoC Overview
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--------------------------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
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LS2081A, LS2088A SoC overview.
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LS2080ARDB board Overview
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-----------------------
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- SERDES Connections, 16 lanes supporting:
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- PCI Express - 3.0
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- SATA 3.0
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- XFI
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- DDR Controller
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- Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
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chip-selects and two DIMM connectors. Support is up to 2133MT/s.
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- One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
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and two DIMM connectors. Support is up to 1600MT/s.
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-IFC/Local Bus
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- IFC rev. 2.0 implementation supporting Little Endian connection scheme.
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- 128 MB NOR flash 16-bit data bus
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- One 2 GB NAND flash with ECC support
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- CPLD connection
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- USB 3.0
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- Two high speed USB 3.0 ports
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- First USB 3.0 port configured as Host with Type-A connector
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- Second USB 3.0 port configured as OTG with micro-AB connector
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- SDHC adapter
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- SD Card Rev 2.0 and Rev 3.0
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- DSPI
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- 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)
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- 4 I2C controllers
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- Two SATA onboard connectors
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- UART
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- ARM JTAG support
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LS2081ARDB board Overview
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-------------------------
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LS2081ARDB board is similar to LS2080ARDB board
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with few differences like
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- Hosts LS2081A SoC
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- Default boot source is QSPI-boot
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- Does not have IFC interface
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- RTC and QSPI flash devices are different
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- Provides QIXIS access via I2C
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Memory map from core's view
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----------------------------
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0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
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0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
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0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
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0x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1
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0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
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0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
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0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
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0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
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Other addresses are either reserved, or not used directly by U-Boot.
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This list should be updated when more addresses are used.
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IFC region map from core's view
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-------------------------------
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During boot i.e. IFC Region #1:-
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0x30000000 - 0x37ffffff : 128MB : NOR flash
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0x3C000000 - 0x40000000 : 64MB : CPLD
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After relocate to DDR i.e. IFC Region #2:-
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0x5_1000_0000..0x5_1fff_ffff Memory Hole
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0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB)
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0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
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0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
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0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
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Booting Options
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---------------
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a) NOR boot
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b) NAND boot
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c) QSPI boot
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Memory map for NOR boot
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-------------------------
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Image Flash Offset
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RCW+PBI 0x00000000
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Boot firmware (U-Boot) 0x00100000
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Boot firmware Environment 0x00300000
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PPA firmware 0x00400000
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Secure Headers 0x00600000
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Cortina PHY firmware 0x00980000
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DPAA2 MC 0x00A00000
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DPAA2 DPL 0x00D00000
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DPAA2 DPC 0x00E00000
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Kernel.itb 0x01000000
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cfg_rcw_src switches needs to be changed for booting from different option.
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Refer to board documentation for correct switch setting.
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QSPI boot details
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===================
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Supported only for
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LS2088ARDB RevF board with LS2088A SoC.
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Images needs to be copied to QSPI flash
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as per memory map given below.
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Memory map for QSPI flash
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-------------------------
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Image Flash Offset
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RCW+PBI 0x00000000
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Boot firmware (U-Boot) 0x00100000
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Boot firmware Environment 0x00300000
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PPA firmware 0x00400000
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Cortina PHY firmware 0x00980000
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DPAA2 MC 0x00A00000
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DPAA2 DPL 0x00D00000
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DPAA2 DPC 0x00E00000
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Kernel.itb 0x01000000
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Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
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-------------------------------------------------------------------
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One needs to use appropriate bootargs to boot Linux flavors which do
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not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
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below:
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=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
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earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
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hugepages=16 mem=2048M'
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@@ -0,0 +1,186 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/clock.h>
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#include "ddr.h"
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DECLARE_GLOBAL_DATA_PTR;
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
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#endif
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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int slot;
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if (ctrl_num > 2) {
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printf("Not supported controller number %d\n", ctrl_num);
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return;
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}
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for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
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if (pdimm[slot].n_ranks)
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break;
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}
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if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
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return;
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/*
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* we use identical timing for all slots. If needed, change the code
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* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
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*/
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if (popts->registered_dimm_en)
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pbsp = rdimms[ctrl_num];
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else
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pbsp = udimms[ctrl_num];
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/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm[slot].n_ranks &&
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(pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found for data rate %lu MT/s\n"
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"Trying to use the highest speed (%u) parameters\n",
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ddr_freq, pbsp_highest->datarate_mhz_high);
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->wrlvl_start = pbsp_highest->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
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"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
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pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
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pbsp->wrlvl_ctl_3);
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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if (ctrl_num == CONFIG_DP_DDR_CTRL) {
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if (popts->registered_dimm_en)
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printf("WARN: RDIMM not supported.\n");
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/* force DDR bus width to 32 bits */
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popts->data_bus_width = 1;
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popts->otf_burst_chop_en = 0;
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popts->burst_length = DDR_BL8;
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popts->bstopre = 0; /* enable auto precharge */
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/*
|
||||
* Layout optimization results byte mapping
|
||||
* Byte 0 -> Byte ECC
|
||||
* Byte 1 -> Byte 3
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||||
* Byte 2 -> Byte 2
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||||
* Byte 3 -> Byte 1
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||||
* Byte ECC -> Byte 0
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||||
*/
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||||
dq_mapping_0 = pdimm[slot].dq_mapping[0];
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||||
dq_mapping_2 = pdimm[slot].dq_mapping[2];
|
||||
dq_mapping_3 = pdimm[slot].dq_mapping[3];
|
||||
pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
|
||||
pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
|
||||
pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
|
||||
pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
|
||||
pdimm[slot].dq_mapping[6] = dq_mapping_2;
|
||||
pdimm[slot].dq_mapping[7] = dq_mapping_3;
|
||||
pdimm[slot].dq_mapping[8] = dq_mapping_0;
|
||||
pdimm[slot].dq_mapping[9] = 0;
|
||||
pdimm[slot].dq_mapping[10] = 0;
|
||||
pdimm[slot].dq_mapping[11] = 0;
|
||||
pdimm[slot].dq_mapping[12] = 0;
|
||||
pdimm[slot].dq_mapping[13] = 0;
|
||||
pdimm[slot].dq_mapping[14] = 0;
|
||||
pdimm[slot].dq_mapping[15] = 0;
|
||||
pdimm[slot].dq_mapping[16] = 0;
|
||||
pdimm[slot].dq_mapping[17] = 0;
|
||||
}
|
||||
#endif
|
||||
/* To work at higher than 1333MT/s */
|
||||
popts->half_strength_driver_enable = 0;
|
||||
/*
|
||||
* Write leveling override
|
||||
*/
|
||||
popts->wrlvl_override = 1;
|
||||
popts->wrlvl_sample = 0x0; /* 32 clocks */
|
||||
|
||||
/*
|
||||
* Rtt and Rtt_WR override
|
||||
*/
|
||||
popts->rtt_override = 0;
|
||||
|
||||
/* Enable ZQ calibration */
|
||||
popts->zq_en = 1;
|
||||
|
||||
/* optimize cpo for erratum A-009942 */
|
||||
popts->cpo_sample = 0x6e;
|
||||
|
||||
if (ddr_freq < 2350) {
|
||||
if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
|
||||
/* four chip-selects */
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
|
||||
DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
|
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
|
||||
popts->twot_en = 1; /* enable 2T timing */
|
||||
} else {
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
|
||||
DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
|
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
|
||||
DDR_CDR2_VREF_RANGE_2;
|
||||
}
|
||||
} else {
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
|
||||
DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
|
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
|
||||
DDR_CDR2_VREF_RANGE_2;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TFABOOT
|
||||
int fsl_initdram(void)
|
||||
{
|
||||
gd->ram_size = tfa_get_dram_size();
|
||||
|
||||
if (!gd->ram_size)
|
||||
gd->ram_size = fsl_ddr_sdram_size();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
int fsl_initdram(void)
|
||||
{
|
||||
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
|
||||
gd->ram_size = fsl_ddr_sdram_size();
|
||||
#else
|
||||
puts("Initializing DDR....using SPD\n");
|
||||
|
||||
gd->ram_size = fsl_ddr_sdram();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_TFABOOT */
|
||||
@@ -0,0 +1,76 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DDR_H__
|
||||
#define __DDR_H__
|
||||
struct board_specific_parameters {
|
||||
u32 n_ranks;
|
||||
u32 datarate_mhz_high;
|
||||
u32 rank_gb;
|
||||
u32 clk_adjust;
|
||||
u32 wrlvl_start;
|
||||
u32 wrlvl_ctl_2;
|
||||
u32 wrlvl_ctl_3;
|
||||
};
|
||||
|
||||
/*
|
||||
* These tables contain all valid speeds we want to override with board
|
||||
* specific parameters. datarate_mhz_high values need to be in ascending order
|
||||
* for each n_ranks group.
|
||||
*/
|
||||
|
||||
static const struct board_specific_parameters udimm0[] = {
|
||||
/*
|
||||
* memory controller 0
|
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
|
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
|
||||
*/
|
||||
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
|
||||
{2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,},
|
||||
{2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,},
|
||||
{2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,},
|
||||
{}
|
||||
};
|
||||
|
||||
/* DP-DDR DIMM */
|
||||
static const struct board_specific_parameters udimm2[] = {
|
||||
/*
|
||||
* memory controller 2
|
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
|
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
|
||||
*/
|
||||
{2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
|
||||
{2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
|
||||
{2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
|
||||
{2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_specific_parameters rdimm0[] = {
|
||||
/*
|
||||
* memory controller 0
|
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
|
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
|
||||
*/
|
||||
{2, 1666, 0, 8, 0x0F, 0x0D0C0A09, 0x0B0C0E08,},
|
||||
{2, 1900, 0, 8, 0x10, 0x0F0D0B0A, 0x0B0E0F09,},
|
||||
{2, 2200, 0, 8, 0x13, 0x120F0E0B, 0x0D10110B,},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_specific_parameters *udimms[] = {
|
||||
udimm0,
|
||||
udimm0,
|
||||
udimm2,
|
||||
};
|
||||
|
||||
static const struct board_specific_parameters *rdimms[] = {
|
||||
rdimm0,
|
||||
rdimm0,
|
||||
udimm2, /* DP-DDR doesn't support RDIMM */
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,122 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <netdev.h>
|
||||
#include <malloc.h>
|
||||
#include <fsl_mdio.h>
|
||||
#include <miiphy.h>
|
||||
#include <phy.h>
|
||||
#include <fm_eth.h>
|
||||
#include <asm/io.h>
|
||||
#include <exports.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <fsl-mc/fsl_mc.h>
|
||||
#include <fsl-mc/ldpaa_wriop.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
int i, interface;
|
||||
struct memac_mdio_info mdio_info;
|
||||
struct mii_dev *dev;
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 srds_s1;
|
||||
struct memac_mdio_controller *reg;
|
||||
|
||||
srds_s1 = in_le32(&gur->rcwsr[28]) &
|
||||
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
|
||||
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
|
||||
mdio_info.regs = reg;
|
||||
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
|
||||
|
||||
/* Register the EMI 1 */
|
||||
fm_memac_mdio_init(bis, &mdio_info);
|
||||
|
||||
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
|
||||
mdio_info.regs = reg;
|
||||
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
|
||||
|
||||
/* Register the EMI 2 */
|
||||
fm_memac_mdio_init(bis, &mdio_info);
|
||||
|
||||
switch (srds_s1) {
|
||||
case 0x2A:
|
||||
wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4);
|
||||
|
||||
break;
|
||||
case 0x4B:
|
||||
wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
|
||||
|
||||
break;
|
||||
default:
|
||||
printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
|
||||
srds_s1);
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
|
||||
interface = wriop_get_enet_if(i);
|
||||
switch (interface) {
|
||||
case PHY_INTERFACE_MODE_XGMII:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
|
||||
wriop_set_mdio(i, dev);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
|
||||
switch (wriop_get_enet_if(i)) {
|
||||
case PHY_INTERFACE_MODE_XGMII:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
|
||||
wriop_set_mdio(i, dev);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
cpu_eth_init(bis);
|
||||
#endif /* CONFIG_FSL_MC_ENET */
|
||||
|
||||
#ifdef CONFIG_PHY_AQUANTIA
|
||||
/*
|
||||
* Export functions to be used by AQ firmware
|
||||
* upload application
|
||||
*/
|
||||
gd->jt->strcpy = strcpy;
|
||||
gd->jt->mdelay = mdelay;
|
||||
gd->jt->mdio_get_current_dev = mdio_get_current_dev;
|
||||
gd->jt->phy_find_by_mask = phy_find_by_mask;
|
||||
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
|
||||
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
|
||||
#endif
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_RESET_PHY_R)
|
||||
void reset_phy(void)
|
||||
{
|
||||
mc_env_boot();
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
@@ -0,0 +1,525 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <malloc.h>
|
||||
#include <errno.h>
|
||||
#include <netdev.h>
|
||||
#include <fsl_ifc.h>
|
||||
#include <fsl_ddr.h>
|
||||
#include <asm/io.h>
|
||||
#include <hwconfig.h>
|
||||
#include <fdt_support.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <fsl-mc/fsl_mc.h>
|
||||
#include <env_internal.h>
|
||||
#include <efi_loader.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/mmu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch/ppa.h>
|
||||
#include <fsl_sec.h>
|
||||
#include <asm/arch-fsl-layerscape/fsl_icid.h>
|
||||
|
||||
#ifdef CONFIG_FSL_QIXIS
|
||||
#include "../common/qixis.h"
|
||||
#include "ls2080ardb_qixis.h"
|
||||
#endif
|
||||
#include "../common/vid.h"
|
||||
|
||||
#define PIN_MUX_SEL_SDHC 0x00
|
||||
#define PIN_MUX_SEL_DSPI 0x0a
|
||||
|
||||
#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
enum {
|
||||
MUX_TYPE_SDHC,
|
||||
MUX_TYPE_DSPI,
|
||||
};
|
||||
|
||||
unsigned long long get_qixis_addr(void)
|
||||
{
|
||||
unsigned long long addr;
|
||||
|
||||
if (gd->flags & GD_FLG_RELOC)
|
||||
addr = QIXIS_BASE_PHYS;
|
||||
else
|
||||
addr = QIXIS_BASE_PHYS_EARLY;
|
||||
|
||||
/*
|
||||
* IFC address under 256MB is mapped to 0x30000000, any address above
|
||||
* is mapped to 0x5_10000000 up to 4GB.
|
||||
*/
|
||||
addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
#ifdef CONFIG_FSL_QIXIS
|
||||
u8 sw;
|
||||
#endif
|
||||
char buf[15];
|
||||
|
||||
cpu_name(buf);
|
||||
printf("Board: %s-RDB, ", buf);
|
||||
|
||||
#ifdef CONFIG_TARGET_LS2081ARDB
|
||||
#ifdef CONFIG_FSL_QIXIS
|
||||
sw = QIXIS_READ(arch);
|
||||
printf("Board version: %c, ", (sw & 0xf) + 'A');
|
||||
|
||||
sw = QIXIS_READ(brdcfg[0]);
|
||||
sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
|
||||
switch (sw) {
|
||||
case 0:
|
||||
puts("boot from QSPI DEV#0\n");
|
||||
puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
|
||||
break;
|
||||
case 1:
|
||||
puts("boot from QSPI DEV#1\n");
|
||||
puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
|
||||
break;
|
||||
case 2:
|
||||
puts("boot from QSPI EMU\n");
|
||||
puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
|
||||
break;
|
||||
case 3:
|
||||
puts("boot from QSPI EMU\n");
|
||||
puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
|
||||
break;
|
||||
case 4:
|
||||
puts("boot from QSPI DEV#0\n");
|
||||
puts("QSPI_CSA_1 mapped to QSPI EMU\n");
|
||||
break;
|
||||
default:
|
||||
printf("invalid setting of SW%u\n", sw);
|
||||
break;
|
||||
}
|
||||
printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
|
||||
#endif
|
||||
puts("SERDES1 Reference : ");
|
||||
printf("Clock1 = 100MHz ");
|
||||
printf("Clock2 = 161.13MHz");
|
||||
#else
|
||||
#ifdef CONFIG_FSL_QIXIS
|
||||
sw = QIXIS_READ(arch);
|
||||
printf("Board Arch: V%d, ", sw >> 4);
|
||||
printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
|
||||
|
||||
sw = QIXIS_READ(brdcfg[0]);
|
||||
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
|
||||
|
||||
if (sw < 0x8)
|
||||
printf("vBank: %d\n", sw);
|
||||
else if (sw == 0x9)
|
||||
puts("NAND\n");
|
||||
else
|
||||
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
|
||||
|
||||
printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
|
||||
#endif
|
||||
puts("SERDES1 Reference : ");
|
||||
printf("Clock1 = 156.25MHz ");
|
||||
printf("Clock2 = 156.25MHz");
|
||||
#endif
|
||||
|
||||
puts("\nSERDES2 Reference : ");
|
||||
printf("Clock1 = 100MHz ");
|
||||
printf("Clock2 = 100MHz\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long get_board_sys_clk(void)
|
||||
{
|
||||
#ifdef CONFIG_FSL_QIXIS
|
||||
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
|
||||
|
||||
switch (sysclk_conf & 0x0F) {
|
||||
case QIXIS_SYSCLK_83:
|
||||
return 83333333;
|
||||
case QIXIS_SYSCLK_100:
|
||||
return 100000000;
|
||||
case QIXIS_SYSCLK_125:
|
||||
return 125000000;
|
||||
case QIXIS_SYSCLK_133:
|
||||
return 133333333;
|
||||
case QIXIS_SYSCLK_150:
|
||||
return 150000000;
|
||||
case QIXIS_SYSCLK_160:
|
||||
return 160000000;
|
||||
case QIXIS_SYSCLK_166:
|
||||
return 166666666;
|
||||
}
|
||||
#endif
|
||||
return 100000000;
|
||||
}
|
||||
|
||||
int select_i2c_ch_pca9547(u8 ch)
|
||||
{
|
||||
int ret;
|
||||
|
||||
#ifndef CONFIG_DM_I2C
|
||||
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
|
||||
#else
|
||||
struct udevice *dev;
|
||||
|
||||
ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
|
||||
if (!ret)
|
||||
ret = dm_i2c_write(dev, 0, &ch, 1);
|
||||
#endif
|
||||
|
||||
if (ret) {
|
||||
puts("PCA: failed to select proper channel\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_multiplexer_select_vid_channel(u8 channel)
|
||||
{
|
||||
return select_i2c_ch_pca9547(channel);
|
||||
}
|
||||
|
||||
int config_board_mux(int ctrl_type)
|
||||
{
|
||||
#ifdef CONFIG_FSL_QIXIS
|
||||
u8 reg5;
|
||||
|
||||
reg5 = QIXIS_READ(brdcfg[5]);
|
||||
|
||||
switch (ctrl_type) {
|
||||
case MUX_TYPE_SDHC:
|
||||
reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
|
||||
break;
|
||||
case MUX_TYPE_DSPI:
|
||||
reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
|
||||
break;
|
||||
default:
|
||||
printf("Wrong mux interface type\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
QIXIS_WRITE(brdcfg[5], reg5);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
|
||||
#endif
|
||||
|
||||
init_final_memctl_regs();
|
||||
|
||||
#ifdef CONFIG_ENV_IS_NOWHERE
|
||||
gd->env_addr = (ulong)&default_environment[0];
|
||||
#endif
|
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
||||
|
||||
#ifdef CONFIG_FSL_QIXIS
|
||||
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_CAAM
|
||||
sec_init();
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_LS_PPA
|
||||
ppa_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
/* invert AQR405 IRQ pins polarity */
|
||||
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_CAAM
|
||||
sec_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_I2C_EARLY_INIT
|
||||
i2c_early_init_f();
|
||||
#endif
|
||||
fsl_lsch3_early_init_f();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
char *env_hwconfig;
|
||||
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
|
||||
u32 val;
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 svr = gur_in32(&gur->svr);
|
||||
|
||||
val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
|
||||
|
||||
env_hwconfig = env_get("hwconfig");
|
||||
|
||||
if (hwconfig_f("dspi", env_hwconfig) &&
|
||||
DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
|
||||
config_board_mux(MUX_TYPE_DSPI);
|
||||
else
|
||||
config_board_mux(MUX_TYPE_SDHC);
|
||||
|
||||
/*
|
||||
* LS2081ARDB RevF board has smart voltage translator
|
||||
* which needs to be programmed to enable high speed SD interface
|
||||
* by setting GPIO4_10 output to zero
|
||||
*/
|
||||
#ifdef CONFIG_TARGET_LS2081ARDB
|
||||
out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
|
||||
in_le32(GPIO4_GPDIR_ADDR)));
|
||||
out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
|
||||
in_le32(GPIO4_GPDAT_ADDR)));
|
||||
#endif
|
||||
if (hwconfig("sdhc"))
|
||||
config_board_mux(MUX_TYPE_SDHC);
|
||||
|
||||
if (adjust_vdd(0))
|
||||
printf("Warning: Adjusting core voltage failed.\n");
|
||||
/*
|
||||
* Default value of board env is based on filename which is
|
||||
* ls2080ardb. Modify board env for other supported SoCs
|
||||
*/
|
||||
if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
|
||||
(SVR_SOC_VER(svr) == SVR_LS2048A))
|
||||
env_set("board", "ls2088ardb");
|
||||
else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
|
||||
(SVR_SOC_VER(svr) == SVR_LS2041A))
|
||||
env_set("board", "ls2081ardb");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void detail_board_ddr_info(void)
|
||||
{
|
||||
puts("\nDDR ");
|
||||
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
|
||||
print_ddr_info(0);
|
||||
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
||||
if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
|
||||
puts("\nDP-DDR ");
|
||||
print_size(gd->bd->bi_dram[2].size, "");
|
||||
print_ddr_info(CONFIG_DP_DDR_CTRL);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_MISC_INIT)
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
void fdt_fixup_board_enet(void *fdt)
|
||||
{
|
||||
int offset;
|
||||
|
||||
offset = fdt_path_offset(fdt, "/soc/fsl-mc");
|
||||
|
||||
if (offset < 0)
|
||||
offset = fdt_path_offset(fdt, "/fsl-mc");
|
||||
|
||||
if (offset < 0) {
|
||||
printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
|
||||
__func__, offset);
|
||||
return;
|
||||
}
|
||||
|
||||
if (get_mc_boot_status() == 0 &&
|
||||
(is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
|
||||
fdt_status_okay(fdt, offset);
|
||||
else
|
||||
fdt_status_fail(fdt, offset);
|
||||
}
|
||||
|
||||
void board_quiesce_devices(void)
|
||||
{
|
||||
fsl_mc_ldpaa_exit(gd->bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
void fsl_fdt_fixup_flash(void *fdt)
|
||||
{
|
||||
int offset;
|
||||
#ifdef CONFIG_TFABOOT
|
||||
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
|
||||
u32 val;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IFC and QSPI are muxed on board.
|
||||
* So disable IFC node in dts if QSPI is enabled or
|
||||
* disable QSPI node in dts in case QSPI is not enabled.
|
||||
*/
|
||||
#ifdef CONFIG_TFABOOT
|
||||
enum boot_src src = get_boot_src();
|
||||
bool disable_ifc = false;
|
||||
|
||||
switch (src) {
|
||||
case BOOT_SOURCE_IFC_NOR:
|
||||
disable_ifc = false;
|
||||
break;
|
||||
case BOOT_SOURCE_QSPI_NOR:
|
||||
disable_ifc = true;
|
||||
break;
|
||||
default:
|
||||
val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
|
||||
if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
|
||||
disable_ifc = true;
|
||||
break;
|
||||
}
|
||||
|
||||
if (disable_ifc) {
|
||||
offset = fdt_path_offset(fdt, "/soc/ifc");
|
||||
|
||||
if (offset < 0)
|
||||
offset = fdt_path_offset(fdt, "/ifc");
|
||||
} else {
|
||||
offset = fdt_path_offset(fdt, "/soc/quadspi");
|
||||
|
||||
if (offset < 0)
|
||||
offset = fdt_path_offset(fdt, "/quadspi");
|
||||
}
|
||||
|
||||
#else
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
offset = fdt_path_offset(fdt, "/soc/ifc");
|
||||
|
||||
if (offset < 0)
|
||||
offset = fdt_path_offset(fdt, "/ifc");
|
||||
#else
|
||||
offset = fdt_path_offset(fdt, "/soc/quadspi");
|
||||
|
||||
if (offset < 0)
|
||||
offset = fdt_path_offset(fdt, "/quadspi");
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (offset < 0)
|
||||
return;
|
||||
|
||||
fdt_status_disabled(fdt, offset);
|
||||
}
|
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int i;
|
||||
u16 mc_memory_bank = 0;
|
||||
|
||||
u64 *base;
|
||||
u64 *size;
|
||||
u64 mc_memory_base = 0;
|
||||
u64 mc_memory_size = 0;
|
||||
u16 total_memory_banks;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
|
||||
|
||||
if (mc_memory_base != 0)
|
||||
mc_memory_bank++;
|
||||
|
||||
total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
|
||||
|
||||
base = calloc(total_memory_banks, sizeof(u64));
|
||||
size = calloc(total_memory_banks, sizeof(u64));
|
||||
|
||||
/* fixup DT for the two GPP DDR banks */
|
||||
base[0] = gd->bd->bi_dram[0].start;
|
||||
size[0] = gd->bd->bi_dram[0].size;
|
||||
base[1] = gd->bd->bi_dram[1].start;
|
||||
size[1] = gd->bd->bi_dram[1].size;
|
||||
|
||||
#ifdef CONFIG_RESV_RAM
|
||||
/* reduce size if reserved memory is within this bank */
|
||||
if (gd->arch.resv_ram >= base[0] &&
|
||||
gd->arch.resv_ram < base[0] + size[0])
|
||||
size[0] = gd->arch.resv_ram - base[0];
|
||||
else if (gd->arch.resv_ram >= base[1] &&
|
||||
gd->arch.resv_ram < base[1] + size[1])
|
||||
size[1] = gd->arch.resv_ram - base[1];
|
||||
#endif
|
||||
|
||||
if (mc_memory_base != 0) {
|
||||
for (i = 0; i <= total_memory_banks; i++) {
|
||||
if (base[i] == 0 && size[i] == 0) {
|
||||
base[i] = mc_memory_base;
|
||||
size[i] = mc_memory_size;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
|
||||
|
||||
fdt_fsl_mc_fixup_iommu_map_entry(blob);
|
||||
|
||||
fsl_fdt_fixup_dr_usb(blob, bd);
|
||||
|
||||
fsl_fdt_fixup_flash(blob);
|
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
fdt_fixup_board_enet(blob);
|
||||
#endif
|
||||
|
||||
fdt_fixup_icid(blob);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void qixis_dump_switch(void)
|
||||
{
|
||||
#ifdef CONFIG_FSL_QIXIS
|
||||
int i, nr_of_cfgsw;
|
||||
|
||||
QIXIS_WRITE(cms[0], 0x00);
|
||||
nr_of_cfgsw = QIXIS_READ(cms[1]);
|
||||
|
||||
puts("DIP switch settings dump:\n");
|
||||
for (i = 1; i <= nr_of_cfgsw; i++) {
|
||||
QIXIS_WRITE(cms[0], i);
|
||||
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Board rev C and earlier has duplicated I2C addresses for 2nd controller.
|
||||
* Both slots has 0x54, resulting 2nd slot unusable.
|
||||
*/
|
||||
void update_spd_address(unsigned int ctrl_num,
|
||||
unsigned int slot,
|
||||
unsigned int *addr)
|
||||
{
|
||||
#ifndef CONFIG_TARGET_LS2081ARDB
|
||||
#ifdef CONFIG_FSL_QIXIS
|
||||
u8 sw;
|
||||
|
||||
sw = QIXIS_READ(arch);
|
||||
if ((sw & 0xf) < 0x3) {
|
||||
if (ctrl_num == 1 && slot == 0)
|
||||
*addr = SPD_EEPROM_ADDRESS4;
|
||||
else if (ctrl_num == 1 && slot == 1)
|
||||
*addr = SPD_EEPROM_ADDRESS3;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,19 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __LS2_RDB_QIXIS_H__
|
||||
#define __LS2_RDB_QIXIS_H__
|
||||
|
||||
/* SYSCLK */
|
||||
#define QIXIS_SYSCLK_66 0x0
|
||||
#define QIXIS_SYSCLK_83 0x1
|
||||
#define QIXIS_SYSCLK_100 0x2
|
||||
#define QIXIS_SYSCLK_125 0x3
|
||||
#define QIXIS_SYSCLK_133 0x4
|
||||
#define QIXIS_SYSCLK_150 0x5
|
||||
#define QIXIS_SYSCLK_160 0x6
|
||||
#define QIXIS_SYSCLK_166 0x7
|
||||
|
||||
#endif /*__LS2_RDB_QIXIS_H__*/
|
||||
Reference in New Issue
Block a user