GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/board/freescale/m548xevb/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_M5485EVB
+
+config SYS_CPU
+	default "mcf547x_8x"
+
+config SYS_BOARD
+	default "m548xevb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "M5485EVB"
+
+endif

source/bootloader/u-boot-2020.01/board/freescale/m548xevb/MAINTAINERS

@@ -0,0 +1,13 @@
+M548XEVB BOARD
+M:	TsiChung Liew <Tsi-Chung.Liew@nxp.com>
+S:	Maintained
+F:	board/freescale/m548xevb/
+F:	include/configs/M5485EVB.h
+F:	configs/M5485AFE_defconfig
+F:	configs/M5485BFE_defconfig
+F:	configs/M5485CFE_defconfig
+F:	configs/M5485DFE_defconfig
+F:	configs/M5485EFE_defconfig
+F:	configs/M5485FFE_defconfig
+F:	configs/M5485GFE_defconfig
+F:	configs/M5485HFE_defconfig

source/bootloader/u-boot-2020.01/board/freescale/m548xevb/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= m548xevb.o

source/bootloader/u-boot-2020.01/board/freescale/m548xevb/m548xevb.c

@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5485 EVB\n");
+	return 0;
+};
+
+int dram_init(void)
+{
+	siu_t *siu = (siu_t *) (MMAP_SIU);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+#ifdef CONFIG_SYS_DRAMSZ1
+	u32 temp;
+#endif
+
+	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
+
+	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
+
+#ifdef CONFIG_SYS_DRAMSZ1
+	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (temp == (1 << i))
+			break;
+	}
+	i--;
+	dramsize += temp;
+	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
+#endif
+
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Issue LEMR */
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
+
+	udelay(100);
+
+	gd->ram_size = dramsize;
+
+	return 0;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf547x_8x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+	pci_mcf547x_8x_init(&hose);
+}
+#endif				/* CONFIG_PCI */