GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_MPC832XEMDS
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config SYS_BOARD
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default "mpc832xemds"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "MPC832XEMDS"
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endif
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@@ -0,0 +1,10 @@
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MPC832XEMDS BOARD
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#M: Dave Liu <daveliu@freescale.com>
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S: Orphan (since 2018-05)
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F: board/freescale/mpc832xemds/
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F: include/configs/MPC832XEMDS.h
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F: configs/MPC832XEMDS_defconfig
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F: configs/MPC832XEMDS_ATM_defconfig
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F: configs/MPC832XEMDS_HOST_33_defconfig
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F: configs/MPC832XEMDS_HOST_66_defconfig
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F: configs/MPC832XEMDS_SLAVE_defconfig
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@@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += mpc832xemds.o
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obj-$(CONFIG_PCI) += pci.o
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@@ -0,0 +1,128 @@
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Freescale MPC832XEMDS Board
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-----------------------------------------
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1. Board Switches and Jumpers
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1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
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For some reason, the HW designers describe the switch settings
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in terms of 0 and 1, and then map that to physical switches where
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the label "On" refers to logic 0 and "Off" is logic 1.
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Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
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bits may contribute to signals that are numbered based at 0,
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and some of those signals may be high-bit-number-0 too. Heed
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well the names and labels and do not get confused.
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"Off" == 1
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"On" == 0
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SW3 is switch 18 as silk-screened onto the board.
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SW4[8] is the bit labeled 8 on Switch 4.
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SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
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SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
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SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
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and bits labeled 8 is set as "Off".
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1.1 For the MPC832XEMDS PROTO Board
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First, make sure the board default setting is consistent with the document
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shipped with your board. Then apply the following setting:
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SW3[1-8]= 0000_1000 (core PLL setting, core enable)
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SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
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SW5[1-8]= 0010_0110 (Boot from high end)
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SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
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SW7[1-8]= 1000_0011 (QE PLL setting)
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ENET3/4 MII mode settings:
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J1 1-2 (ETH3_TXER)
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J2 2-3 (MII mode)
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J3 2-3 (MII mode)
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J4 2-3 (ADSL clockOscillator)
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J5 1-2 (ETH4_TXER)
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J6 2-3 (ClockOscillator)
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JP1 removed (don't force PORESET)
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JP2 mounted (ETH4/2 MII)
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JP3 mounted (ETH3 MII)
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JP4 mounted (HRCW from BCSR)
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ENET3/4 RMII mode settings:
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J1 1-2 (ETH3_TXER)
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J2 1-2 (RMII mode)
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J3 1-2 (RMII mode)
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J4 2-3 (ADSL clockOscillator)
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J5 1-2 (ETH4_TXER)
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J6 2-3 (ClockOscillator)
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JP1 removed (don't force PORESET)
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JP2 removed (ETH4/2 RMII)
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JP3 removed (ETH3 RMII)
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JP4 removed (HRCW from FLASH)
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on board Oscillator: 66M
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2. Memory Map
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2.1 The memory map should look pretty much like this:
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0x0000_0000 0x7fff_ffff DDR 2G
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0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
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0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
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0xc000_0000 0xdfff_ffff Empty 512M
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0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
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0xe020_0000 0xe02f_ffff Empty 1M
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0xe030_0000 0xe03f_ffff PCI IO 1M
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0xe040_0000 0xefff_ffff Empty 252M
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0xf400_0000 0xf7ff_ffff Empty 64M
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0xf800_0000 0xf800_7fff BCSR on CS1 32K
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0xf800_8000 0xf800_ffff PIB CS2 32K
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0xf801_0000 0xf801_7fff PIB CS3 32K
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0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
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3. Definitions
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3.1 Explanation of NEW definitions in:
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include/configs/MPC832XEPB.h
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CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x
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CONFIG_MPC832x MPC832x specific
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CONFIG_MPC832XEMDS MPC832XEMDS board specific
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4. Compilation
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Assuming you're using BASH shell:
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export CROSS_COMPILE=your-cross-compile-prefix
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cd u-boot
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make distclean
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make MPC832XEMDS_config
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make
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MPC832x support PCI 33MHz and PCI 66MHz, to make U-Boot support PCI:
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1)Make sure the DIP SW support PCI mode as described in Section 1.1.
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2)To Make U-Boot image support PCI 33MHz, use
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Make MPC832XEMDS_HOST_33_config
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3)To Make U-Boot image support PCI 66MHz, use
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Make MPC832XEMDS_HOST_66M_config
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5. Downloading and Flashing Images
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5.0 Download over network:
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tftp 10000 u-boot.bin
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5.1 Reflash U-Boot Image using U-Boot
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tftp 20000 u-boot.bin
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protect off fe000000 fe0fffff
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erase fe000000 fe0fffff
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cp.b 20000 fe000000 xxxx
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You have to supply the correct byte count with 'xxxx' from the TFTP result log.
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Maybe 3ffff will work too, that corresponds to the erased sectors.
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6. Notes
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1) The console baudrate for MPC832XEMDS is 115200bps.
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@@ -0,0 +1,170 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <command.h>
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#if defined(CONFIG_PCI)
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#include <pci.h>
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#endif
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#include <asm/mmu.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <linux/libfdt.h>
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#endif
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#if defined(CONFIG_PQ_MDS_PIB)
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#include "../common/pq-mds-pib.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* ETH3 */
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{1, 0, 1, 0, 1}, /* TxD0 */
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{1, 1, 1, 0, 1}, /* TxD1 */
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{1, 2, 1, 0, 1}, /* TxD2 */
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{1, 3, 1, 0, 1}, /* TxD3 */
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{1, 9, 1, 0, 1}, /* TxER */
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{1, 12, 1, 0, 1}, /* TxEN */
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{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
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{1, 4, 2, 0, 1}, /* RxD0 */
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{1, 5, 2, 0, 1}, /* RxD1 */
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{1, 6, 2, 0, 1}, /* RxD2 */
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{1, 7, 2, 0, 1}, /* RxD3 */
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{1, 8, 2, 0, 1}, /* RxER */
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{1, 10, 2, 0, 1}, /* RxDV */
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{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
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{1, 11, 2, 0, 1}, /* COL */
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{1, 13, 2, 0, 1}, /* CRS */
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/* ETH4 */
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{1, 18, 1, 0, 1}, /* TxD0 */
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{1, 19, 1, 0, 1}, /* TxD1 */
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{1, 20, 1, 0, 1}, /* TxD2 */
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{1, 21, 1, 0, 1}, /* TxD3 */
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{1, 27, 1, 0, 1}, /* TxER */
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{1, 30, 1, 0, 1}, /* TxEN */
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{3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
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{1, 22, 2, 0, 1}, /* RxD0 */
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{1, 23, 2, 0, 1}, /* RxD1 */
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{1, 24, 2, 0, 1}, /* RxD2 */
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{1, 25, 2, 0, 1}, /* RxD3 */
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{1, 26, 1, 0, 1}, /* RxER */
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{1, 28, 2, 0, 1}, /* Rx_DV */
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{3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
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{1, 29, 2, 0, 1}, /* COL */
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{1, 31, 2, 0, 1}, /* CRS */
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{3, 4, 3, 0, 2}, /* MDIO */
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{3, 5, 1, 0, 2}, /* MDC */
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
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};
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int board_early_init_f(void)
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{
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volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
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/* Enable flash write */
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bcsr[9] &= ~0x08;
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_PQ_MDS_PIB
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pib_init();
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#endif
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return 0;
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}
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int fixed_sdram(void);
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int dram_init(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -ENXIO;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
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msize = fixed_sdram();
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/* set total bus SDRAM size(bytes) -- DDR */
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gd->ram_size = msize * 1024 * 1024;
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return 0;
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}
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CONFIG_SYS_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
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if (ddr_size & 1) {
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return -1;
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}
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}
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im->sysconf.ddrlaw[0].ar =
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CONFIG_SYS_DDR_SIZE != 128)
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#warning Currenly any ddr size other than 128 is not supported
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#endif
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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__asm__ __volatile__ ("sync");
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udelay(200);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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__asm__ __volatile__ ("sync");
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return msize;
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}
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int checkboard(void)
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{
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puts("Board: Freescale MPC832XEMDS\n");
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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#endif
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@@ -0,0 +1,144 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
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*/
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/*
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* PCI Configuration space access support for MPC83xx PCI Bridge
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*/
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#include <init.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <common.h>
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#include <mpc83xx.h>
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#include <pci.h>
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#include <i2c.h>
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#include <asm/fsl_i2c.h>
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#include "../common/pq-mds-pib.h"
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static struct pci_region pci1_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI1_MEM_BASE,
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
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size: CONFIG_SYS_PCI1_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI1_IO_BASE,
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phys_start: CONFIG_SYS_PCI1_IO_PHYS,
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size: CONFIG_SYS_PCI1_IO_SIZE,
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flags: PCI_REGION_IO
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},
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{
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bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
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size: CONFIG_SYS_PCI1_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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};
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#ifdef CONFIG_MPC83XX_PCI2
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static struct pci_region pci2_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI2_MEM_BASE,
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phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
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size: CONFIG_SYS_PCI2_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI2_IO_BASE,
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phys_start: CONFIG_SYS_PCI2_IO_PHYS,
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size: CONFIG_SYS_PCI2_IO_SIZE,
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flags: PCI_REGION_IO
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},
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{
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||||
bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
|
||||
size: CONFIG_SYS_PCI2_MMIO_SIZE,
|
||||
flags: PCI_REGION_MEM
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||||
},
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||||
};
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||||
#endif
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||||
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void pci_init_board(void)
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#ifdef CONFIG_PCISLAVE
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||||
{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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||||
volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
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||||
struct pci_region *reg[] = { pci1_regions };
|
||||
|
||||
/* Configure PCI Local Access Windows */
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||||
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
|
||||
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||||
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
|
||||
|
||||
mpc83xx_pci_init(1, reg);
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||||
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||||
/*
|
||||
* Configure PCI Inbound Translation Windows
|
||||
*/
|
||||
pci_ctrl[0].pitar0 = 0x0;
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||||
pci_ctrl[0].pibar0 = 0x0;
|
||||
pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
|
||||
PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
|
||||
|
||||
pci_ctrl[0].pitar1 = 0x0;
|
||||
pci_ctrl[0].pibar1 = 0x0;
|
||||
pci_ctrl[0].piebar1 = 0x0;
|
||||
pci_ctrl[0].piwar1 &= ~PIWAR_EN;
|
||||
|
||||
pci_ctrl[0].pitar2 = 0x0;
|
||||
pci_ctrl[0].pibar2 = 0x0;
|
||||
pci_ctrl[0].piebar2 = 0x0;
|
||||
pci_ctrl[0].piwar2 &= ~PIWAR_EN;
|
||||
|
||||
/* Unlock the configuration bit */
|
||||
mpc83xx_pcislave_unlock(0);
|
||||
printf("PCI: Agent mode enabled\n");
|
||||
}
|
||||
#else
|
||||
{
|
||||
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||
#ifndef CONFIG_MPC83XX_PCI2
|
||||
struct pci_region *reg[] = { pci1_regions };
|
||||
#else
|
||||
struct pci_region *reg[] = { pci1_regions, pci2_regions };
|
||||
#endif
|
||||
|
||||
/* initialize the PCA9555PW IO expander on the PIB board */
|
||||
pib_init();
|
||||
|
||||
#if defined(CONFIG_PCI_66M)
|
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
|
||||
printf("PCI clock is 66MHz\n");
|
||||
#elif defined(CONFIG_PCI_33M)
|
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
|
||||
OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
|
||||
printf("PCI clock is 33MHz\n");
|
||||
#else
|
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
|
||||
printf("PCI clock is 66MHz\n");
|
||||
#endif
|
||||
udelay(2000);
|
||||
|
||||
/* Configure PCI Local Access Windows */
|
||||
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
|
||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
|
||||
|
||||
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
|
||||
|
||||
udelay(2000);
|
||||
|
||||
#ifndef CONFIG_MPC83XX_PCI2
|
||||
mpc83xx_pci_init(1, reg);
|
||||
#else
|
||||
mpc83xx_pci_init(2, reg);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_PCISLAVE */
|
||||
Reference in New Issue
Block a user