GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_MPC837XERDB
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config SYS_BOARD
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default "mpc837xerdb"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "MPC837XERDB"
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endif
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@@ -0,0 +1,7 @@
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MPC837XERDB BOARD
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M: Sinan Akman <sinan@writeme.com>
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S: Maintained
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F: board/freescale/mpc837xerdb/
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F: include/configs/MPC837XERDB.h
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F: configs/MPC837XERDB_defconfig
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F: configs/MPC837XERDB_SLAVE_defconfig
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@@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += mpc837xerdb.o
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obj-$(CONFIG_PCI) += pci.o
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@@ -0,0 +1,97 @@
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Freescale MPC837xE-RDB Board
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-----------------------------------------
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1. Board Description
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The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E,
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MPC8378E, and the MPC8379E processors in a Mini-ITX form factor.
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The MPC837xE-RDB's have the following common features:
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A) 256-MBytes on-board DDR2 unbuffered SDRAM
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B) 8-Mbytes NOR Flash
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C) 32-MBytes NAND Flash
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D) 1 Secure Digital High Speed Card (SDHC) Interface
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E) 1 Gigabit Ethernet
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F) 5-port Ethernet switch (Vitesse 7385)
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G) 1 32-bit, 3.3 V, PCI slot
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H) 1 32-bit, 3.3 V, Mini-PCI slot
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I) 4-port USB 2.0 Hub
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J) 1-port OTG USB
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K) 2 serial ports (top main console)
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L) on board Oscillator: 66M
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The MPC837xE-RDB's have the following differences:
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MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB
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SATA controllers 2 0 4
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PCI-Express (mini) 2 2 0
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SGMII Ports 0 2 0
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2. Memory Map
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2.1. The memory map should look pretty much like this:
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Address Range Device Size Port Size
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(Bytes) (Bits)
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=========================== ================= ======= =========
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0x0000_0000 0x0fff_ffff DDR 256M 64
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0x1000_0000 0x7fff_ffff Empty 1.75G -
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0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32
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0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32
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0xe030_0000 0xe03f_ffff PCI I/O space 1M 32
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0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M -
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0xe060_0000 0xe060_7fff NAND Flash 32K 8
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0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16
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3. Definitions
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3.1 Explanation of NEW definitions in:
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include/configs/MPC837XERDB.h
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CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
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CONFIG_MPC837x MPC837x specific
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CONFIG_MPC837XERDB MPC837xE-RDB board specific
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4. Compilation
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Assuming you're using BASH shell:
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export CROSS_COMPILE=your-cross-compile-prefix
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cd u-boot
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make distclean
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make MPC837XERDB_config
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make
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5. Downloading and Flashing Images
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5.0 Download over serial line using Kermit:
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loadb $loadaddr
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[Drop to kermit:
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^\c
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send <u-boot-bin-image>
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c
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]
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Or via tftp:
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tftp $loadaddr u-boot.bin
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5.1 Reflash U-Boot Image using U-Boot
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tftp $loadaddr u-boot.bin
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protect off fe000000 fe0fffff
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erase fe000000 fe0fffff
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cp.b $loadaddr fe000000 $filesize
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6. Additional Notes:
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1) The console is connected to the top RS-232 connector and the
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baudrate for MPC837XE-RDB is 115200bps.
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@@ -0,0 +1,222 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Kevin Lam <kevin.lam@freescale.com>
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* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <hwconfig.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/fsl_mpc83xx_serdes.h>
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#include <fdt_support.h>
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#include <spd_sdram.h>
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#include <vsc7385.h>
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#include <fsl_esdhc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SYS_DRAM_TEST)
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int
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testdram(void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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printf("Testing DRAM from 0x%08x to 0x%08x\n",
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CONFIG_SYS_MEMTEST_START,
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CONFIG_SYS_MEMTEST_END);
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printf("DRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test passed.\n");
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return 0;
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}
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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void ddr_enable_ecc(unsigned int dram_size);
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#endif
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int fixed_sdram(void);
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int dram_init(void)
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{
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immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -ENXIO;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/* Initialize DDR ECC byte */
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* return total bus DDR size(bytes) */
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gd->ram_size = msize * 1024 * 1024;
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return 0;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
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im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
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udelay(50000);
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
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udelay(1000);
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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udelay(1000);
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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sync();
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udelay(1000);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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udelay(2000);
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return CONFIG_SYS_DDR_SIZE;
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}
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#endif /*!CONFIG_SYS_SPD_EEPROM */
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int checkboard(void)
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{
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puts("Board: Freescale MPC837xERDB\n");
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return 0;
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}
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int board_early_init_f(void)
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{
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#ifdef CONFIG_FSL_SERDES
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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u32 spridr = in_be32(&immr->sysconf.spridr);
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/* we check only part num, and don't look for CPU revisions */
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switch (PARTID_NO_E(spridr)) {
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case SPR_8377:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378:
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8379:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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default:
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printf("serdes not configured: unknown CPU part number: "
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"%04x\n", spridr >> 16);
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break;
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}
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#endif /* CONFIG_FSL_SERDES */
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return 0;
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_init(bd_t *bd)
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{
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
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char buffer[HWCONFIG_BUFFER_SIZE] = {0};
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int esdhc_hwconfig_enabled = 0;
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if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
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esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
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if (esdhc_hwconfig_enabled == 0)
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return 0;
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clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
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clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
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return fsl_esdhc_mmc_init(bd);
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}
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#endif
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/*
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* Miscellaneous late-boot configurations
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*
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* If a VSC7385 microcode image is present, then upload it.
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*/
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int misc_init_r(void)
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{
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int rc = 0;
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#ifdef CONFIG_VSC7385_IMAGE
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if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
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CONFIG_VSC7385_IMAGE_SIZE)) {
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puts("Failure uploading VSC7385 microcode.\n");
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rc = 1;
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}
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#endif
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return rc;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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ft_cpu_setup(blob, bd);
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fsl_fdt_fixup_dr_usb(blob, bd);
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fdt_fixup_esdhc(blob, bd);
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return 0;
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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@@ -0,0 +1,108 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <init.h>
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#include <mpc83xx.h>
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#include <pci.h>
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#include <asm/io.h>
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static struct pci_region pci_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI_MEM_BASE,
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phys_start: CONFIG_SYS_PCI_MEM_PHYS,
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size: CONFIG_SYS_PCI_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
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size: CONFIG_SYS_PCI_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CONFIG_SYS_PCI_IO_BASE,
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phys_start: CONFIG_SYS_PCI_IO_PHYS,
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size: CONFIG_SYS_PCI_IO_SIZE,
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flags: PCI_REGION_IO
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}
|
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};
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static struct pci_region pcie_regions_0[] = {
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{
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.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
|
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.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
|
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.size = CONFIG_SYS_PCIE1_MEM_SIZE,
|
||||
.flags = PCI_REGION_MEM,
|
||||
},
|
||||
{
|
||||
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
|
||||
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
|
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.size = CONFIG_SYS_PCIE1_IO_SIZE,
|
||||
.flags = PCI_REGION_IO,
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||||
},
|
||||
};
|
||||
|
||||
static struct pci_region pcie_regions_1[] = {
|
||||
{
|
||||
.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
|
||||
.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
|
||||
.size = CONFIG_SYS_PCIE2_MEM_SIZE,
|
||||
.flags = PCI_REGION_MEM,
|
||||
},
|
||||
{
|
||||
.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
|
||||
.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
|
||||
.size = CONFIG_SYS_PCIE2_IO_SIZE,
|
||||
.flags = PCI_REGION_IO,
|
||||
},
|
||||
};
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile sysconf83xx_t *sysconf = &immr->sysconf;
|
||||
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||
volatile law83xx_t *pcie_law = sysconf->pcielaw;
|
||||
struct pci_region *reg[] = { pci_regions };
|
||||
struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
|
||||
u32 spridr = in_be32(&immr->sysconf.spridr);
|
||||
|
||||
/* Enable all 5 PCI_CLK_OUTPUTS */
|
||||
clk->occr |= 0xf8000000;
|
||||
udelay(2000);
|
||||
|
||||
/* Configure PCI Local Access Windows */
|
||||
pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
|
||||
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
|
||||
|
||||
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
|
||||
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
|
||||
|
||||
mpc83xx_pci_init(1, reg);
|
||||
|
||||
/* There is no PEX in MPC8379 parts. */
|
||||
if (PARTID_NO_E(spridr) == SPR_8379)
|
||||
return;
|
||||
|
||||
/* Configure the clock for PCIE controller */
|
||||
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
|
||||
SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
|
||||
|
||||
/* Deassert the resets in the control register */
|
||||
out_be32(&sysconf->pecr1, 0xE0008000);
|
||||
out_be32(&sysconf->pecr2, 0xE0008000);
|
||||
udelay(2000);
|
||||
|
||||
/* Configure PCI Express Local Access Windows */
|
||||
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
|
||||
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
|
||||
|
||||
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
|
||||
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
|
||||
|
||||
mpc83xx_pcie_init(2, pcie_reg);
|
||||
}
|
||||
Reference in New Issue
Block a user