GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_MPC8555CDS
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config SYS_BOARD
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default "mpc8555cds"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "MPC8555CDS"
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endif
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@@ -0,0 +1,7 @@
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MPC8555CDS BOARD
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M: Priyanka Jain <priyanka.jain@nxp.com>
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S: Maintained
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F: board/freescale/mpc8555cds/
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F: include/configs/MPC8555CDS.h
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F: configs/MPC8555CDS_defconfig
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F: configs/MPC8555CDS_legacy_defconfig
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@@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2004 Freescale Semiconductor.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += mpc8555cds.o
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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@@ -0,0 +1,53 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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/*
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* Factors to consider for clock adjust:
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* - number of chips on bus
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* - position of slot
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* - DDR1 vs. DDR2?
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* - ???
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*
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* This needs to be determined on a board-by-board basis.
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* 0110 3/4 cycle late
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* 0111 7/8 cycle late
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*/
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popts->clk_adjust = 6;
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/*
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* Factors to consider for CPO:
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* - frequency
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* - ddr1 vs. ddr2
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*/
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popts->cpo_override = 0;
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/*
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* Factors to consider for write data delay:
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* - number of DIMMs
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*
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* 1 = 1/4 clock delay
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* 2 = 1/2 clock delay
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* 3 = 3/4 clock delay
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* 4 = 1 clock delay
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* 5 = 5/4 clock delay
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* 6 = 3/2 clock delay
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*/
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popts->write_data_delay = 3;
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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}
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@@ -0,0 +1,41 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe20f_ffff PCI1 IO 1M
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* 0xe210_0000 0xe21f_ffff PCI2 IO 1M
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
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SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
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SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
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SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@@ -0,0 +1,429 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2004, 2011 Freescale Semiconductor.
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*/
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#include <common.h>
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#include <init.h>
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#include <pci.h>
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#include <vsprintf.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <fsl_ddr_sdram.h>
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#include <ioports.h>
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#include <spd_sdram.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include "../common/cadmus.h"
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#include "../common/eeprom.h"
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#include "../common/via.h"
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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void local_bus_init(void);
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
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/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
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/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
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/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
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/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
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/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
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/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
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/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
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/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
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/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
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/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
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/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
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/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
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/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
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/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
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/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
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/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
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/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
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/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
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/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
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/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
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/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
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/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
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/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
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/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
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/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
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/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
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/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
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/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
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/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
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/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
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/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
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/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
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/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
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/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
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/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
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/* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
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/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
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/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
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/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
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/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
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/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
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/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
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/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
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/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
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/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
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/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
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/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
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/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
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/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
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/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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int checkboard (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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char buf[32];
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/* PCI slot in USER bits CSR[6:7] by convention. */
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uint pci_slot = get_pci_slot ();
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uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
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uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
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uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
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uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
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uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
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uint cpu_board_rev = get_cpu_board_revision ();
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printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
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get_board_version (), pci_slot);
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printf ("CPU Board Revision %d.%d (0x%04x)\n",
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MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
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MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
|
||||
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printf("PCI1: %d bit, %s MHz, %s\n",
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(pci1_32) ? 32 : 64,
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strmhz(buf, pci1_speed),
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pci1_clk_sel ? "sync" : "async");
|
||||
|
||||
if (pci_dual) {
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printf("PCI2: 32 bit, 66 MHz, %s\n",
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pci2_clk_sel ? "sync" : "async");
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||||
} else {
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||||
printf("PCI2: disabled\n");
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||||
}
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||||
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||||
/*
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||||
* Initialize local bus.
|
||||
*/
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||||
local_bus_init ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize Local Bus
|
||||
*/
|
||||
void
|
||||
local_bus_init(void)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
|
||||
|
||||
uint clkdiv;
|
||||
uint lbc_hz;
|
||||
sys_info_t sysinfo;
|
||||
uint temp_lbcdll;
|
||||
|
||||
/*
|
||||
* Errata LBC11.
|
||||
* Fix Local Bus clock glitch when DLL is enabled.
|
||||
*
|
||||
* If localbus freq is < 66MHz, DLL bypass mode must be used.
|
||||
* If localbus freq is > 133MHz, DLL can be safely enabled.
|
||||
* Between 66 and 133, the DLL is enabled with an override workaround.
|
||||
*/
|
||||
|
||||
get_sys_info(&sysinfo);
|
||||
clkdiv = lbc->lcrr & LCRR_CLKDIV;
|
||||
lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
|
||||
|
||||
if (lbc_hz < 66) {
|
||||
lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
|
||||
|
||||
} else if (lbc_hz >= 133) {
|
||||
lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
|
||||
|
||||
} else {
|
||||
lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
|
||||
udelay(200);
|
||||
|
||||
/*
|
||||
* Sample LBC DLL ctrl reg, upshift it to set the
|
||||
* override bits.
|
||||
*/
|
||||
temp_lbcdll = gur->lbcdllcr;
|
||||
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
|
||||
asm("sync;isync;msync");
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize SDRAM memory on the Local Bus.
|
||||
*/
|
||||
void lbc_sdram_init(void)
|
||||
{
|
||||
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
|
||||
|
||||
uint idx;
|
||||
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
|
||||
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
|
||||
uint cpu_board_rev;
|
||||
uint lsdmr_common;
|
||||
|
||||
puts("LBC SDRAM: ");
|
||||
print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
|
||||
"\n ");
|
||||
|
||||
/*
|
||||
* Setup SDRAM Base and Option Registers
|
||||
*/
|
||||
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
|
||||
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
|
||||
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
|
||||
asm("msync");
|
||||
|
||||
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
|
||||
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
|
||||
asm("msync");
|
||||
|
||||
/*
|
||||
* Determine which address lines to use baed on CPU board rev.
|
||||
*/
|
||||
cpu_board_rev = get_cpu_board_revision();
|
||||
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
|
||||
if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
|
||||
lsdmr_common |= LSDMR_BSMA1617;
|
||||
} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
|
||||
lsdmr_common |= LSDMR_BSMA1516;
|
||||
} else {
|
||||
/*
|
||||
* Assume something unable to identify itself is
|
||||
* really old, and likely has lines 16/17 mapped.
|
||||
*/
|
||||
lsdmr_common |= LSDMR_BSMA1617;
|
||||
}
|
||||
|
||||
/*
|
||||
* Issue PRECHARGE ALL command.
|
||||
*/
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(100);
|
||||
|
||||
/*
|
||||
* Issue 8 AUTO REFRESH commands.
|
||||
*/
|
||||
for (idx = 0; idx < 8; idx++) {
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
/*
|
||||
* Issue 8 MODE-set command.
|
||||
*/
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(100);
|
||||
|
||||
/*
|
||||
* Issue NORMAL OP command.
|
||||
*/
|
||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
|
||||
asm("sync;msync");
|
||||
*sdram_addr = 0xff;
|
||||
ppcDcbf((unsigned long) sdram_addr);
|
||||
udelay(200); /* Overkill. Must wait > 200 bus cycles */
|
||||
|
||||
#endif /* enable SDRAM init */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* For some reason the Tundra PCI bridge shows up on itself as a
|
||||
* different device. Work around that by refusing to configure it
|
||||
*/
|
||||
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
|
||||
|
||||
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
|
||||
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
|
||||
mpc85xx_config_via_usbide, {0,0,0}},
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
|
||||
mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
|
||||
mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
|
||||
mpc85xx_config_via_power, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
|
||||
mpc85xx_config_via_ac97, {0,0,0}},
|
||||
{},
|
||||
};
|
||||
|
||||
|
||||
static struct pci_controller hose[] = {
|
||||
{
|
||||
config_table: pci_mpc85xxcds_config_table,
|
||||
},
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
{},
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
pci_init_board(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
pci_mpc85xx_init(hose);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int node, tmp[2];
|
||||
const char *path;
|
||||
|
||||
node = fdt_path_offset(blob, "/aliases");
|
||||
tmp[0] = 0;
|
||||
if (node >= 0) {
|
||||
#ifdef CONFIG_PCI1
|
||||
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = hose[0].last_busno - hose[0].first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||
if (path) {
|
||||
tmp[1] = hose[1].last_busno - hose[1].first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,95 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded
|
||||
* 0xff000000 16M FLASH
|
||||
* Out of reset this entry is only 4K.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_16M, 1),
|
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded
|
||||
* 0x80000000 256M PCI1 MEM First half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded
|
||||
* 0x90000000 256M PCI1 MEM Second half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded
|
||||
* 0xa0000000 256M PCI2 MEM First half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded
|
||||
* 0xb0000000 256M PCI2 MEM Second half
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe200_0000 16M PCI1 IO
|
||||
* 0xe300_0000 16M PCI2 IO
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded
|
||||
* 0xf000_0000 64M LBC SDRAM
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 6, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/*
|
||||
* TLB 7: 1M Non-cacheable, guarded
|
||||
* 0xf8000000 1M CADMUS registers
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 7, BOOKE_PAGESZ_1M, 1),
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
Reference in New Issue
Block a user