GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_MPC8569MDS
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config SYS_BOARD
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default "mpc8569mds"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "MPC8569MDS"
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endif
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@@ -0,0 +1,7 @@
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MPC8569MDS BOARD
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M: Priyanka Jain <priyanka.jain@nxp.com>
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S: Maintained
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F: board/freescale/mpc8569mds/
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F: include/configs/MPC8569MDS.h
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F: configs/MPC8569MDS_defconfig
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F: configs/MPC8569MDS_ATM_defconfig
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@@ -0,0 +1,11 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2004-2009 Freescale Semiconductor.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += mpc8569mds.o
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obj-y += bcsr.o
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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@@ -0,0 +1,77 @@
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Overview
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--------
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MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform
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I/O Board). The mpc8569 PowerTM processor is mounted on PB board.
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Building U-Boot
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-----------
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make MPC8569MDS_config
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make
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Memory Map
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----------
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0x0000_0000 0x7fff_ffff DDR 2G
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0xa000_0000 0xbfff_ffff PCIe MEM 512MB
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0xe000_0000 0xe00f_ffff CCSRBAR 1M
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0xe280_0000 0xe2ff_ffff PCIe I/O 8M
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0xc000_0000 0xdfff_ffff SRIO 512MB
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0xf000_0000 0xf3ff_ffff SDRAM 64MB
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0xf800_0000 0xf800_7fff BCSR 32KB
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0xf800_8000 0xf800_ffff PIB (CS4) 32KB
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0xf801_0000 0xf801_7fff PIB (CS5) 32KB
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0xfe00_0000 0xffff_ffff Flash 32MB
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Flashing U-Boot Images
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---------------
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Use the following commands to program U-Boot image into flash:
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=> tftp 1000000 u-boot.bin
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=> protect off all
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=> erase fff80000 ffffffff
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=> cp.b 1000000 fff80000 80000
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Setting the correct MAC addresses
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-----------------------
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The command - "mac", is introduced to set on-board system EEPROM in the format
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defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC
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addresses for the MPC8569MDS's 8 Ethernet ports and save it by "mac save" when
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we first get the board. The commands are as follows:
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=> mac i NXID /* Set NXID to this EEPROM */
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=> mac e 01 /* Set Errata, this value is not defined by hardware
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designer, we can set whatever we want */
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=> mac n a0 /* Set Serial Number. This is not defined by hardware
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designer, we can set whatever we want */
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=> mac date 090512080000 /* Set the date in YYMMDDhhmmss format */
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=> mac p 8 /* Set the number of mac ports, it should be 8 */
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=> mac 0 xx:xx:xx:xx:xx:xx /* xx:xx:xx:xx:xx:xx should be the real mac
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address, you can refer to the value on
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the sticker of the rear side of the board
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*/
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.....
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=> mac 7 xx:xx:xx:xx:xx:xx
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=> mac read
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=> mac save
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After resetting the board, the ethxaddrs will be filled with the mac addresses
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if such environment variables are blank(never been set before). If the ethxaddr
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has been set but we want to update it, we can use the following commands:
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=> setenv ethxaddr /* x = "none",1,2,3,4,5,6,7 */
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=> save
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=> reset
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Programming the ucode to flash
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---------------------------------
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MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's
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IRAM so that the QE can work. The ucode binary can be downloaded from
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http://opensource.freescale.com/firmware/, and it must be programmed to
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the address 0xfff0000 in the flash. Otherwise, the QE can't work and uboot
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hangs at "Net:"
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Please note the above two steps(setting mac addresses and programming ucode) are
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very important to get the board booting up and working properly.
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@@ -0,0 +1,49 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2009 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include "bcsr.h"
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void enable_8569mds_flash_write(void)
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{
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
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}
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void disable_8569mds_flash_write(void)
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{
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
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}
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void enable_8569mds_qe_uec(void)
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{
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#if defined(CONFIG_SYS_UCC_RGMII_MODE)
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
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BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
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BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
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BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
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BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
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#elif defined(CONFIG_SYS_UCC_RMII_MODE)
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/* Set UCC1-4 working at RMII mode */
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
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BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
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BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
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BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
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BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
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#endif
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}
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void disable_8569mds_brd_eeprom_write_protect(void)
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{
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
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}
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@@ -0,0 +1,71 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2009 Freescale Semiconductor, Inc.
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*/
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#ifndef __BCSR_H_
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#define __BCSR_H_
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#include <common.h>
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/* BCSR Bit definitions*/
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/****************************************/
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/* BCSR defines */
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/****************************************/
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#define BCSR6_UPC1_EN 0x80
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#define BCSR6_UPC1_POS_EN 0x40
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#define BCSR6_UPC1_ADDR_EN 0x20
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#define BCSR6_UPC1_DEV2 0x10
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#define BCSR6_SD_CARD_1BIT 0x08
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#define BCSR6_SD_CARD_4BITS 0x04
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#define BCSR6_TDM2G_EN 0x02
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#define BCSR6_UCC7_RMII_EN 0x01
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#define BCSR7_UCC1_GETH_EN 0x80
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#define BCSR7_UCC1_RGMII_EN 0x40
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#define BCSR7_UCC1_RTBI_EN 0x20
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#define BCSR7_GETHRST_MRVL 0x04
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#define BCSR7_BRD_WRT_PROTECT 0x02
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#define BCSR8_UCC2_GETH_EN 0x80
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#define BCSR8_UCC2_RGMII_EN 0x40
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#define BCSR8_UCC2_RTBI_EN 0x20
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#define BCSR8_UEM_MARVEL_RESET 0x02
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#define BCSR9_UCC3_GETH_EN 0x80
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#define BCSR9_UCC3_RGMII_EN 0x40
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#define BCSR9_UCC3_RTBI_EN 0x20
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#define BCSR9_UCC3_RMII_EN 0x10
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#define BCSR9_UCC3_UEM_MICREL 0x01
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#define BCSR10_UCC4_GETH_EN 0x80
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#define BCSR10_UCC4_RGMII_EN 0x40
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#define BCSR10_UCC4_RTBI_EN 0x20
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#define BCSR11_LED0 0x40
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#define BCSR11_LED1 0x20
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#define BCSR11_LED2 0x10
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#define BCSR12_UCC6_RMII_EN 0x20
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#define BCSR12_UCC8_RMII_EN 0x20
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#define BCSR15_SMII6_DIS 0x08
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#define BCSR15_SMII8_DIS 0x04
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#define BCSR15_QEUART_EN 0x01
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#define BCSR16_UPC1_DEV2 0x02
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#define BCSR17_nUSBEN 0x80
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#define BCSR17_nUSBLOWSPD 0x40
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#define BCSR17_USBVCC 0x20
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#define BCSR17_USBMODE 0x10
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#define BCSR17_FLASH_nWP 0x01
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/*BCSR Utils functions*/
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void enable_8569mds_flash_write(void);
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void disable_8569mds_flash_write(void);
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void enable_8569mds_qe_uec(void);
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void disable_8569mds_brd_eeprom_write_protect(void);
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#endif /* __BCSR_H_ */
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@@ -0,0 +1,63 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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/*
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* Factors to consider for clock adjust:
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* - number of chips on bus
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* - position of slot
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* - DDR1 vs. DDR2?
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* - ???
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*
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* This needs to be determined on a board-by-board basis.
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* 0110 3/4 cycle late
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* 0111 7/8 cycle late
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*/
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popts->clk_adjust = 4;
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/*
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* Factors to consider for CPO:
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* - frequency
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* - ddr1 vs. ddr2
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*/
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popts->cpo_override = 0xff;
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/*
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* Factors to consider for write data delay:
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* - number of DIMMs
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*
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* 1 = 1/4 clock delay
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* 2 = 1/2 clock delay
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* 3 = 3/4 clock delay
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* 4 = 1 clock delay
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* 5 = 5/4 clock delay
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* 6 = 3/2 clock delay
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*/
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popts->write_data_delay = 2;
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/*
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* Enable half drive strength
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*/
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popts->half_strength_driver_enable = 1;
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/* Write leveling override */
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popts->wrlvl_en = 1;
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xa;
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popts->wrlvl_start = 0x4;
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/* Rtt and Rtt_W override */
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popts->rtt_override = 1;
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popts->rtt_override_value = DDR3_RTT_60_OHM;
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popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
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}
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@@ -0,0 +1,40 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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*0) 0x0000_0000 0x7fff_ffff DDR 2G
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*1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
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*-) 0xe000_0000 0xe00f_ffff CCSR 1M
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*2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
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*3) 0xc000_0000 0xdfff_ffff SRIO 512MB
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*4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
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*4.b) 0xf800_0000 0xf800_7fff BCSR 32KB
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*4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
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*4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
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*4.e) 0xfe00_0000 0xffff_ffff Flash 32MB
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*
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*Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*
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*/
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struct law_entry law_table[] = {
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#ifndef CONFIG_SPD_EEPROM
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
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#endif
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SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@@ -0,0 +1,586 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
|
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* Copyright 2009-2010 Freescale Semiconductor.
|
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*
|
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
|
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*/
|
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|
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#include <common.h>
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#include <console.h>
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#include <hwconfig.h>
|
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#include <init.h>
|
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#include <pci.h>
|
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#include <asm/processor.h>
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#include <asm/mmu.h>
|
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <fsl_ddr_sdram.h>
|
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#include <asm/fsl_serdes.h>
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#include <asm/io.h>
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#include <spd_sdram.h>
|
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#include <i2c.h>
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#include <ioports.h>
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#include <linux/libfdt.h>
|
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#include <fdt_support.h>
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#include <fsl_esdhc.h>
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#include <phy.h>
|
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|
||||
#include "bcsr.h"
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#if defined(CONFIG_PQ_MDS_PIB)
|
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#include "../common/pq-mds-pib.h"
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||||
#endif
|
||||
|
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const qe_iop_conf_t qe_iop_conf_tab[] = {
|
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/* QE_MUX_MDC */
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{2, 31, 1, 0, 1}, /* QE_MUX_MDC */
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|
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/* QE_MUX_MDIO */
|
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{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
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|
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#if defined(CONFIG_SYS_UCC_RGMII_MODE)
|
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/* UCC_1_RGMII */
|
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{2, 11, 2, 0, 1}, /* CLK12 */
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{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
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||||
{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
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{0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
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{0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
|
||||
{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
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{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
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||||
{0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
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{0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
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||||
{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
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||||
{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
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||||
{2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
|
||||
{2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
|
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/* UCC_2_RGMII */
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{2, 16, 2, 0, 3}, /* CLK17 */
|
||||
{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
|
||||
{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
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||||
{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
|
||||
{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
|
||||
{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
|
||||
{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
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||||
{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
|
||||
{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
|
||||
{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
|
||||
{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
|
||||
{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
|
||||
{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
|
||||
|
||||
/* UCC_3_RGMII */
|
||||
{2, 11, 2, 0, 1}, /* CLK12 */
|
||||
{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
|
||||
{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
|
||||
{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
|
||||
{1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
|
||||
{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
|
||||
{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
|
||||
{1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
|
||||
{1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
|
||||
{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
|
||||
{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
|
||||
{2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
|
||||
{2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
|
||||
|
||||
/* UCC_4_RGMII */
|
||||
{2, 16, 2, 0, 3}, /* CLK17 */
|
||||
{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
|
||||
{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
|
||||
{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
|
||||
{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
|
||||
{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
|
||||
{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
|
||||
{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
|
||||
{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
|
||||
{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
|
||||
{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
|
||||
{2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
|
||||
{2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
|
||||
|
||||
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
|
||||
/* UCC_1_RMII */
|
||||
{2, 15, 2, 0, 1}, /* CLK16 */
|
||||
{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
|
||||
{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
|
||||
{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
|
||||
{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
|
||||
{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
|
||||
{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
|
||||
|
||||
/* UCC_2_RMII */
|
||||
{2, 15, 2, 0, 1}, /* CLK16 */
|
||||
{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
|
||||
{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
|
||||
{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
|
||||
{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
|
||||
{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
|
||||
{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
|
||||
|
||||
/* UCC_3_RMII */
|
||||
{2, 15, 2, 0, 1}, /* CLK16 */
|
||||
{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
|
||||
{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
|
||||
{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
|
||||
{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
|
||||
{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
|
||||
{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
|
||||
|
||||
/* UCC_4_RMII */
|
||||
{2, 15, 2, 0, 1}, /* CLK16 */
|
||||
{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
|
||||
{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
|
||||
{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
|
||||
{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
|
||||
{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
|
||||
{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
|
||||
#endif
|
||||
|
||||
/* UART1 is muxed with QE PortF bit [9-12].*/
|
||||
{5, 12, 2, 0, 3}, /* UART1_SIN */
|
||||
{5, 9, 1, 0, 3}, /* UART1_SOUT */
|
||||
{5, 10, 2, 0, 3}, /* UART1_CTS_B */
|
||||
{5, 11, 1, 0, 2}, /* UART1_RTS_B */
|
||||
|
||||
/* QE UART */
|
||||
{0, 19, 1, 0, 2}, /* QEUART_TX */
|
||||
{1, 17, 2, 0, 3}, /* QEUART_RX */
|
||||
{0, 25, 1, 0, 1}, /* QEUART_RTS */
|
||||
{1, 23, 2, 0, 1}, /* QEUART_CTS */
|
||||
|
||||
/* QE USB */
|
||||
{5, 3, 1, 0, 1}, /* USB_OE */
|
||||
{5, 4, 1, 0, 2}, /* USB_TP */
|
||||
{5, 5, 1, 0, 2}, /* USB_TN */
|
||||
{5, 6, 2, 0, 2}, /* USB_RP */
|
||||
{5, 7, 2, 0, 1}, /* USB_RX */
|
||||
{5, 8, 2, 0, 1}, /* USB_RN */
|
||||
{2, 4, 2, 0, 2}, /* CLK5 */
|
||||
|
||||
/* SPI Flash, M25P40 */
|
||||
{4, 27, 3, 0, 1}, /* SPI_MOSI */
|
||||
{4, 28, 3, 0, 1}, /* SPI_MISO */
|
||||
{4, 29, 3, 0, 1}, /* SPI_CLK */
|
||||
{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
|
||||
|
||||
{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
|
||||
};
|
||||
|
||||
void local_bus_init(void);
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/*
|
||||
* Initialize local bus.
|
||||
*/
|
||||
local_bus_init ();
|
||||
|
||||
enable_8569mds_flash_write();
|
||||
|
||||
#ifdef CONFIG_QE
|
||||
enable_8569mds_qe_uec();
|
||||
#endif
|
||||
|
||||
#if CONFIG_SYS_I2C2_OFFSET
|
||||
/* Enable I2C2 signals instead of SD signals */
|
||||
volatile struct ccsr_gur *gur;
|
||||
gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
|
||||
gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
|
||||
gur->plppar1 |= PLPPAR1_I2C2_VAL;
|
||||
gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
|
||||
gur->plpdir1 |= PLPDIR1_I2C2_VAL;
|
||||
|
||||
disable_8569mds_brd_eeprom_write_protect();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
|
||||
const u8 flash_esel = 0;
|
||||
|
||||
/*
|
||||
* Remap Boot flash to caching-inhibited
|
||||
* so that flash can be erased properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
/* invalidate existing TLB entry for flash */
|
||||
disable_tlb(flash_esel);
|
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
|
||||
0, flash_esel, /* ts, esel */
|
||||
BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
printf ("Board: 8569 MDS\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
phys_size_t fixed_sdram(void)
|
||||
{
|
||||
struct ccsr_ddr __iomem *ddr =
|
||||
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
uint d_init;
|
||||
|
||||
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
|
||||
out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
|
||||
out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
|
||||
out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
|
||||
out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
|
||||
out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
|
||||
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
|
||||
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
|
||||
out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
|
||||
out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
|
||||
out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
|
||||
out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
|
||||
out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
|
||||
out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
|
||||
out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
|
||||
out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
|
||||
out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
|
||||
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
|
||||
#if defined (CONFIG_DDR_ECC)
|
||||
out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
|
||||
out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
|
||||
out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
|
||||
#endif
|
||||
udelay(500);
|
||||
|
||||
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
|
||||
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
d_init = 1;
|
||||
debug("DDR - 1st controller: memory initializing\n");
|
||||
/*
|
||||
* Poll until memory is initialized.
|
||||
* 512 Meg at 400 might hit this 200 times or so.
|
||||
*/
|
||||
while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
|
||||
udelay(1000);
|
||||
}
|
||||
debug("DDR: memory initialized\n\n");
|
||||
udelay(500);
|
||||
#endif
|
||||
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initialize Local Bus
|
||||
*/
|
||||
void
|
||||
local_bus_init(void)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
|
||||
|
||||
uint clkdiv;
|
||||
sys_info_t sysinfo;
|
||||
|
||||
get_sys_info(&sysinfo);
|
||||
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
|
||||
|
||||
out_be32(&gur->lbiuiplldcr1, 0x00078080);
|
||||
if (clkdiv == 16)
|
||||
out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
|
||||
else if (clkdiv == 8)
|
||||
out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
|
||||
else if (clkdiv == 4)
|
||||
out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
|
||||
|
||||
out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
|
||||
}
|
||||
|
||||
static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
|
||||
{
|
||||
const char *status = "disabled";
|
||||
int off;
|
||||
int err;
|
||||
|
||||
off = fdt_path_offset(blob, alias);
|
||||
if (off < 0) {
|
||||
printf("WARNING: could not find %s alias: %s.\n", alias,
|
||||
fdt_strerror(off));
|
||||
return;
|
||||
}
|
||||
|
||||
err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
|
||||
if (err) {
|
||||
printf("WARNING: could not set status for serial0: %s.\n",
|
||||
fdt_strerror(err));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Because of an erratum in prototype boards it is impossible to use eSDHC
|
||||
* without disabling UART0 (which makes it quite easy to 'brick' the board
|
||||
* by simply issung 'setenv hwconfig esdhc', and not able to interact with
|
||||
* U-Boot anylonger).
|
||||
*
|
||||
* So, but default we assume that the board is a prototype, which is a most
|
||||
* safe assumption. There is no way to determine board revision from a
|
||||
* register, so we use hwconfig.
|
||||
*/
|
||||
|
||||
static int prototype_board(void)
|
||||
{
|
||||
if (hwconfig_subarg("board", "rev", NULL))
|
||||
return hwconfig_subarg_cmp("board", "rev", "prototype");
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int esdhc_disables_uart0(void)
|
||||
{
|
||||
return prototype_board() ||
|
||||
hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
|
||||
}
|
||||
|
||||
static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
|
||||
{
|
||||
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
|
||||
const char *devtype = "serial";
|
||||
const char *compat = "ucc_uart";
|
||||
const char *clk = "brg9";
|
||||
u32 portnum = 0;
|
||||
int off = -1;
|
||||
|
||||
if (!hwconfig("qe_uart"))
|
||||
return;
|
||||
|
||||
if (hwconfig("esdhc") && esdhc_disables_uart0()) {
|
||||
printf("QE UART: won't enable with esdhc.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
fdt_board_disable_serial(blob, bd, "serial1");
|
||||
|
||||
while (1) {
|
||||
const u32 *idx;
|
||||
int len;
|
||||
|
||||
off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
|
||||
if (off < 0) {
|
||||
printf("WARNING: unable to fixup device tree for "
|
||||
"QE UART\n");
|
||||
return;
|
||||
}
|
||||
|
||||
idx = fdt_getprop(blob, off, "cell-index", &len);
|
||||
if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
|
||||
continue;
|
||||
break;
|
||||
}
|
||||
|
||||
fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
|
||||
fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
|
||||
fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
|
||||
fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
|
||||
fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
|
||||
|
||||
setbits_8(&bcsr[15], BCSR15_QEUART_EN);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
|
||||
int board_mmc_init(bd_t *bd)
|
||||
{
|
||||
struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
|
||||
u8 bcsr6 = BCSR6_SD_CARD_1BIT;
|
||||
|
||||
if (!hwconfig("esdhc"))
|
||||
return 0;
|
||||
|
||||
printf("Enabling eSDHC...\n"
|
||||
" For eSDHC to function, I2C2 ");
|
||||
if (esdhc_disables_uart0()) {
|
||||
printf("and UART0 should be disabled.\n");
|
||||
printf(" Redirecting stderr, stdout and stdin to UART1...\n");
|
||||
console_assign(stderr, "eserial1");
|
||||
console_assign(stdout, "eserial1");
|
||||
console_assign(stdin, "eserial1");
|
||||
printf("Switched to UART1 (initial log has been printed to "
|
||||
"UART0).\n");
|
||||
|
||||
clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
|
||||
PLPPAR1_ESDHC_4BITS_VAL);
|
||||
clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
|
||||
PLPDIR1_ESDHC_4BITS_VAL);
|
||||
bcsr6 |= BCSR6_SD_CARD_4BITS;
|
||||
} else {
|
||||
printf("should be disabled.\n");
|
||||
}
|
||||
|
||||
/* Assign I2C2 signals to eSDHC. */
|
||||
clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
|
||||
PLPPAR1_ESDHC_VAL);
|
||||
clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
|
||||
PLPDIR1_ESDHC_VAL);
|
||||
|
||||
/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
|
||||
setbits_8(&bcsr[6], bcsr6);
|
||||
|
||||
return fsl_esdhc_mmc_init(bd);
|
||||
}
|
||||
|
||||
static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
|
||||
{
|
||||
const char *status = "disabled";
|
||||
int off = -1;
|
||||
|
||||
if (!hwconfig("esdhc"))
|
||||
return;
|
||||
|
||||
if (esdhc_disables_uart0())
|
||||
fdt_board_disable_serial(blob, bd, "serial0");
|
||||
|
||||
while (1) {
|
||||
const u32 *idx;
|
||||
int len;
|
||||
|
||||
off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
|
||||
if (off < 0)
|
||||
break;
|
||||
|
||||
idx = fdt_getprop(blob, off, "cell-index", &len);
|
||||
if (!idx || len != sizeof(*idx))
|
||||
continue;
|
||||
|
||||
if (*idx == 1) {
|
||||
fdt_setprop(blob, off, "status", status,
|
||||
strlen(status) + 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
|
||||
off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
|
||||
if (off < 0) {
|
||||
printf("WARNING: could not find esdhc node\n");
|
||||
return;
|
||||
}
|
||||
fdt_delprop(blob, off, "sdhci,1-bit-only");
|
||||
}
|
||||
}
|
||||
#else
|
||||
static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
|
||||
#endif
|
||||
|
||||
static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
|
||||
{
|
||||
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
|
||||
|
||||
if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
|
||||
clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
|
||||
else
|
||||
setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
|
||||
|
||||
if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
|
||||
clrbits_8(&bcsr[17], BCSR17_USBVCC);
|
||||
clrbits_8(&bcsr[17], BCSR17_USBMODE);
|
||||
do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
|
||||
"peripheral", sizeof("peripheral"), 1);
|
||||
} else {
|
||||
setbits_8(&bcsr[17], BCSR17_USBVCC);
|
||||
setbits_8(&bcsr[17], BCSR17_USBMODE);
|
||||
}
|
||||
|
||||
clrbits_8(&bcsr[17], BCSR17_nUSBEN);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
void pci_init_board(void)
|
||||
{
|
||||
#if defined(CONFIG_PQ_MDS_PIB)
|
||||
pib_init();
|
||||
#endif
|
||||
|
||||
fsl_pcie_init_board(0);
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#if defined(CONFIG_SYS_UCC_RMII_MODE)
|
||||
int nodeoff, off, err;
|
||||
unsigned int val;
|
||||
const u32 *ph;
|
||||
const u32 *index;
|
||||
|
||||
/* fixup device tree for supporting rmii mode */
|
||||
nodeoff = -1;
|
||||
while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
|
||||
"ucc_geth")) >= 0) {
|
||||
err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
|
||||
"clk16");
|
||||
if (err < 0) {
|
||||
printf("WARNING: could not set tx-clock-name %s.\n",
|
||||
fdt_strerror(err));
|
||||
break;
|
||||
}
|
||||
|
||||
err = fdt_fixup_phy_connection(blob, nodeoff,
|
||||
PHY_INTERFACE_MODE_RMII);
|
||||
|
||||
if (err < 0) {
|
||||
printf("WARNING: could not set phy-connection-type "
|
||||
"%s.\n", fdt_strerror(err));
|
||||
break;
|
||||
}
|
||||
|
||||
index = fdt_getprop(blob, nodeoff, "cell-index", 0);
|
||||
if (index == NULL) {
|
||||
printf("WARNING: could not get cell-index of ucc\n");
|
||||
break;
|
||||
}
|
||||
|
||||
ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
|
||||
if (ph == NULL) {
|
||||
printf("WARNING: could not get phy-handle of ucc\n");
|
||||
break;
|
||||
}
|
||||
|
||||
off = fdt_node_offset_by_phandle(blob, *ph);
|
||||
if (off < 0) {
|
||||
printf("WARNING: could not get phy node %s.\n",
|
||||
fdt_strerror(err));
|
||||
break;
|
||||
}
|
||||
|
||||
val = 0x7 + *index; /* RMII phy address starts from 0x8 */
|
||||
|
||||
err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
|
||||
if (err < 0) {
|
||||
printf("WARNING: could not set reg for phy-handle "
|
||||
"%s.\n", fdt_strerror(err));
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
FT_FSL_PCI_SETUP;
|
||||
|
||||
fdt_board_fixup_esdhc(blob, bd);
|
||||
fdt_board_fixup_qe_uart(blob, bd);
|
||||
fdt_board_fixup_qe_usb(blob, bd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,94 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2009-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 Initializations */
|
||||
/*
|
||||
* TLBe 0: 64M write-through, guarded
|
||||
* Out of reset this entry is only 4K.
|
||||
* 0xfc000000 32MB NAND FLASH (CS3)
|
||||
* 0xfe000000 32MB NOR FLASH (CS0)
|
||||
*/
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_1M, 1),
|
||||
#else
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_64M, 1),
|
||||
#endif
|
||||
/*
|
||||
* TLBe 1: 256KB Non-cacheable, guarded
|
||||
* 0xf8000000 32K BCSR
|
||||
* 0xf8008000 32K PIB (CS4)
|
||||
* 0xf8010000 32K PIB (CS5)
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_256K, 1),
|
||||
|
||||
/*
|
||||
* TLBe 2: 256M Non-cacheable, guarded
|
||||
* 0xa00000000 256M PCIe MEM (lower half)
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLBe 3: 256M Non-cacheable, guarded
|
||||
* 0xb00000000 256M PCIe MEM (higher half)
|
||||
*/
|
||||
SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
|
||||
(CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/*
|
||||
* TLBe 4: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe280_0000 8M PCIe IO
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
|
||||
/* *I*G - L2SRAM */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_256K, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
|
||||
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_256K, 1),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
Reference in New Issue
Block a user