GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,15 @@
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if TARGET_MX28EVK
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config SYS_BOARD
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default "mx28evk"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "mxs"
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config SYS_CONFIG_NAME
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default "mx28evk"
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endif
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@@ -0,0 +1,9 @@
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MX28EVK BOARD
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M: Fabio Estevam <fabio.estevam@nxp.com>
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S: Maintained
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F: board/freescale/mx28evk/
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F: include/configs/mx28evk.h
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F: configs/mx28evk_defconfig
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F: configs/mx28evk_auart_console_defconfig
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F: configs/mx28evk_nand_defconfig
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F: configs/mx28evk_spi_defconfig
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@@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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ifndef CONFIG_SPL_BUILD
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obj-y := mx28evk.o
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else
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obj-y := iomux.o
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endif
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@@ -0,0 +1,62 @@
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FREESCALE MX28EVK
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==================
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Supported hardware: MX28EVK rev C and D are supported in U-Boot.
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Files of the MX28EVK port
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--------------------------
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arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28
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arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28
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board/freescale/mx28evk/ - MX28EVK board specific files
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include/configs/mx28evk.h - MX28EVK configuration file
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Jumper configuration
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---------------------
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To boot MX28EVK from an SD card, set the boot mode DIP switches as:
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* Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42)
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* JTAG PSWITCH RESET: To the right (reset disabled)
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* Battery Source: Down
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* Wall 5V: Up
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* VDD 5V: To the left (off)
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* Hold Button: Down (off)
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To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as:
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* Boot Mode Select: 0 0 1 0 (Boot from SSP2)
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* JTAG PSWITCH RESET: To the right (reset disabled)
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* Battery Source: Down
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* Wall 5V: Up
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* VDD 5V: To the left (off)
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* Hold Button: Down (off)
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Environment Storage
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-------------------
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There are three targets for mx28evk:
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"make mx28evk_config" - store environment variables into MMC
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or
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"make mx28evk_nand_config" - store environment variables into NAND flash
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or
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"make mx28evk_spi_config" - store environment variables into SPI NOR flash
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Choose the target accordingly.
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Note: The mx28evk board does not come with a NAND flash populated from the
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factory. It comes with an empty slot (U23), which allows the insertion of a
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48-pin TSOP flash device.
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mx28evk does not come with SPI NOR flash populated from the factory either.
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It is possible to solder a SOIC memory on U49 or use a DIP8 on J89.
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To get SPI communication to work R320, R321,R322 and C178 need to be populated.
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Look in the schematics for the proper component values.
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Follow the instructions from doc/imx/common/mxs.txt to generate a bootable
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SD card or to generate a binary to be flashed into SPI NOR.
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@@ -0,0 +1,205 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale MX28EVK IOMUX setup
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
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const iomux_cfg_t iomux_setup[] = {
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/* DUART */
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MX28_PAD_PWM0__DUART_RX,
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MX28_PAD_PWM1__DUART_TX,
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/* MMC0 */
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MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
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(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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MX28_PAD_SSP0_SCK__SSP0_SCK |
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(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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/* write protect */
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MX28_PAD_SSP1_SCK__GPIO_2_12,
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/* MMC0 slot power enable */
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MX28_PAD_PWM3__GPIO_3_28 |
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(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
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#ifdef CONFIG_NAND_MXS
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/* GPMI NAND */
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MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_RDN__GPMI_RDN |
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(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
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MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
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#endif
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/* FEC0 */
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MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
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/* FEC0 Enable */
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MX28_PAD_SSP1_DATA3__GPIO_2_15 |
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(MXS_PAD_12MA | MXS_PAD_3V3),
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/* FEC0 Reset */
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MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
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(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
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/* FEC1 */
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MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
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/* EMI */
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MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
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/* SPI2 (for SPI flash) */
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MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
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MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
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MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
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MX28_PAD_SSP2_SS0__SSP2_D3 |
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(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
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/* I2C */
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MX28_PAD_I2C0_SCL__I2C0_SCL,
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MX28_PAD_I2C0_SDA__I2C0_SDA,
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/* LCD */
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MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
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MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
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MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
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MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD,
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MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */
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MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */
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};
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#define HW_DRAM_CTL29 (0x74 >> 2)
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#define CS_MAP 0xf
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#define COLUMN_SIZE 0x2
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#define ADDR_PINS 0x1
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#define APREBIT 0xa
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#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
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ADDR_PINS << 8 | APREBIT)
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void mxs_adjust_memory_params(uint32_t *dram_vals)
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{
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dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
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}
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void board_init_ll(const uint32_t arg, const uint32_t *resptr)
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{
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mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
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}
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@@ -0,0 +1,147 @@
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// SPDX-License-Identifier: GPL-2.0+
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||||
/*
|
||||
* Freescale MX28EVK board
|
||||
*
|
||||
* (C) Copyright 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* Based on m28evk.c:
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
*/
|
||||
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||||
#include <common.h>
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||||
#include <asm/gpio.h>
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||||
#include <asm/io.h>
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||||
#include <asm/arch/imx-regs.h>
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||||
#include <asm/arch/iomux-mx28.h>
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||||
#include <asm/arch/clock.h>
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||||
#include <asm/arch/sys_proto.h>
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||||
#include <linux/mii.h>
|
||||
#include <miiphy.h>
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||||
#include <netdev.h>
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||||
#include <errno.h>
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||||
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||||
DECLARE_GLOBAL_DATA_PTR;
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||||
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||||
/*
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||||
* Functions
|
||||
*/
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* IO0 clock at 480MHz */
|
||||
mxs_set_ioclk(MXC_IOCLK0, 480000);
|
||||
/* IO1 clock at 480MHz */
|
||||
mxs_set_ioclk(MXC_IOCLK1, 480000);
|
||||
|
||||
/* SSP0 clock at 96MHz */
|
||||
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
|
||||
/* SSP2 clock at 160MHz */
|
||||
mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
|
||||
mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
|
||||
MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
|
||||
gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
|
||||
#endif
|
||||
|
||||
/* Power on LCD */
|
||||
gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
|
||||
|
||||
/* Set contrast to maximum */
|
||||
gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
return mxs_dram_init();
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Adress of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_MMC
|
||||
static int mx28evk_mmc_wp(int id)
|
||||
{
|
||||
if (id != 0) {
|
||||
printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
/* Configure WP as input */
|
||||
gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
|
||||
|
||||
/* Configure MMC0 Power Enable */
|
||||
gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
|
||||
|
||||
return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_NET
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
struct mxs_clkctrl_regs *clkctrl_regs =
|
||||
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
struct eth_device *dev;
|
||||
int ret;
|
||||
|
||||
ret = cpu_eth_init(bis);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* MX28EVK uses ENET_CLK PAD to drive FEC clock */
|
||||
writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
|
||||
&clkctrl_regs->hw_clkctrl_enet);
|
||||
|
||||
/* Power-on FECs */
|
||||
gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
|
||||
|
||||
/* Reset FEC PHYs */
|
||||
gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
|
||||
udelay(200);
|
||||
gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
|
||||
if (ret) {
|
||||
puts("FEC MXS: Unable to init FEC0\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
|
||||
if (ret) {
|
||||
puts("FEC MXS: Unable to init FEC1\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev = eth_get_dev_by_name("FEC0");
|
||||
if (!dev) {
|
||||
puts("FEC MXS: Unable to get FEC0 device entry\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dev = eth_get_dev_by_name("FEC1");
|
||||
if (!dev) {
|
||||
puts("FEC MXS: Unable to get FEC1 device entry\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user