GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_MX6SLEVK
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config SYS_BOARD
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default "mx6slevk"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "mx6slevk"
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endif
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@@ -0,0 +1,9 @@
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MX6SLEVK BOARD
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M: Fabio Estevam <fabio.estevam@nxp.com>
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M: Peng Fan <peng.fan@nxp.com>
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S: Maintained
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F: board/freescale/mx6slevk/
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F: include/configs/mx6slevk.h
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F: configs/mx6slevk_defconfig
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F: configs/mx6slevk_spl_defconfig
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F: configs/mx6slevk_spinor_defconfig
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@@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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# (C) Copyright 2013 Freescale Semiconductor, Inc.
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obj-y := mx6slevk.o
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@@ -0,0 +1,123 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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/*
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* Secure boot support
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*/
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#ifdef CONFIG_IMX_HAB
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x020c4018 0x00260324
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020e0344 0x00003030
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DATA 4 0x020e0348 0x00003030
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DATA 4 0x020e034c 0x00003030
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DATA 4 0x020e0350 0x00003030
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DATA 4 0x020e030c 0x00000030
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DATA 4 0x020e0310 0x00000030
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DATA 4 0x020e0314 0x00000030
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DATA 4 0x020e0318 0x00000030
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DATA 4 0x020e0300 0x00000030
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DATA 4 0x020e031c 0x00000030
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DATA 4 0x020e0338 0x00000028
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DATA 4 0x020e0320 0x00000030
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DATA 4 0x020e032c 0x00000000
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DATA 4 0x020e033c 0x00000008
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DATA 4 0x020e0340 0x00000008
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DATA 4 0x020e05c4 0x00000030
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DATA 4 0x020e05cc 0x00000030
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DATA 4 0x020e05d4 0x00000030
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DATA 4 0x020e05d8 0x00000030
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DATA 4 0x020e05ac 0x00000030
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DATA 4 0x020e05c8 0x00000030
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DATA 4 0x020e05b0 0x00020000
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DATA 4 0x020e05b4 0x00000000
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DATA 4 0x020e05c0 0x00020000
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DATA 4 0x020e05d0 0x00080000
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b085c 0x1b4700c7
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DATA 4 0x021b0800 0xa1390003
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DATA 4 0x021b0890 0x00400000
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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DATA 4 0x021b082c 0xf3333333
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DATA 4 0x021b0830 0xf3333333
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DATA 4 0x021b0834 0xf3333333
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DATA 4 0x021b0838 0xf3333333
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DATA 4 0x021b0848 0x4241444a
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DATA 4 0x021b0850 0x3030312b
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DATA 4 0x021b083c 0x20000000
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DATA 4 0x021b0840 0x00000000
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DATA 4 0x021b08c0 0x24911492
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b000c 0x33374133
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DATA 4 0x021b0004 0x00020024
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DATA 4 0x021b0010 0x00100A82
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DATA 4 0x021b0014 0x00000093
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DATA 4 0x021b0018 0x00001688
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DATA 4 0x021b002c 0x0f9f26d2
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DATA 4 0x021b0030 0x009f0e10
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DATA 4 0x021b0038 0x00190778
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DATA 4 0x021b0008 0x00000000
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DATA 4 0x021b0040 0x0000004f
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DATA 4 0x021b0000 0xc3110000
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DATA 4 0x021b001c 0x003f8030
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DATA 4 0x021b001c 0xff0a8030
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DATA 4 0x021b001c 0x82018030
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DATA 4 0x021b001c 0x04028030
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DATA 4 0x021b001c 0x02038030
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DATA 4 0x021b001c 0xff0a8038
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DATA 4 0x021b001c 0x82018038
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DATA 4 0x021b001c 0x04028038
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DATA 4 0x021b001c 0x02038038
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DATA 4 0x021b0800 0xa1310003
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DATA 4 0x021b0020 0x00001800
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DATA 4 0x021b0818 0x00000000
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b0004 0x00025564
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DATA 4 0x021b0404 0x00011006
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DATA 4 0x021b001c 0x00000000
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@@ -0,0 +1,418 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <fsl_esdhc_imx.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include "../common/pfuze.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
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PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
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PAD_CTL_SRE_FAST)
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#define ETH_PHY_POWER IMX_GPIO_NR(4, 21)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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#ifdef CONFIG_SPL_BUILD
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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/* 8 bit SD */
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/*CD pin*/
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MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/*CD pin*/
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MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/*CD pin*/
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MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#endif
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static iomux_v3_cfg_t const fec_pads[] = {
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MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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/* Power up LAN8720 PHY */
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gpio_request(ETH_PHY_POWER, "eth_pwr");
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gpio_direction_output(ETH_PHY_POWER , 1);
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udelay(15000);
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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#ifdef CONFIG_DM_PMIC_PFUZE100
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret;
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u32 dev_id, rev_id, i;
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u32 switch_num = 6;
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u32 offset = PFUZE100_SW1CMODE;
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ret = pmic_get("pfuze100", &dev);
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if (ret == -ENODEV)
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return 0;
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if (ret != 0)
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return ret;
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dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
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rev_id = pmic_reg_read(dev, PFUZE100_REVID);
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printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
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/* set SW1AB staby volatage 0.975V */
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pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
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/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
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pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
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/* set SW1C staby volatage 0.975V */
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pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
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/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
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pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
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/* Init mode to APS_PFM */
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pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
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for (i = 0; i < switch_num - 1; i++)
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pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
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return 0;
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}
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#endif
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#ifdef CONFIG_FEC_MXC
|
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int board_eth_init(bd_t *bis)
|
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{
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setup_iomux_fec();
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return cpu_eth_init(bis);
|
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}
|
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static int setup_fec(void)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
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|
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/* clear gpr1[14], gpr1[18:17] to select anatop clock */
|
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
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return enable_fec_anatop_clock(0, ENET_50MHZ);
|
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_FEC_MXC
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setup_fec();
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#endif
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return 0;
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}
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int checkboard(void)
|
||||
{
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puts("Board: MX6SLEVK\n");
|
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
|
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#include <spl.h>
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#include <linux/libfdt.h>
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#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
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#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
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#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
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static struct fsl_esdhc_cfg usdhc_cfg[3] = {
|
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{USDHC1_BASE_ADDR},
|
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{USDHC2_BASE_ADDR, 0, 4},
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{USDHC3_BASE_ADDR, 0, 4},
|
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};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
|
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gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
|
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ret = !gpio_get_value(USDHC1_CD_GPIO);
|
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break;
|
||||
case USDHC2_BASE_ADDR:
|
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gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
|
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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break;
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||||
case USDHC3_BASE_ADDR:
|
||||
gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
|
||||
ret = !gpio_get_value(USDHC3_CD_GPIO);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
|
||||
u32 val;
|
||||
u32 port;
|
||||
|
||||
val = readl(&src_regs->sbmr1);
|
||||
|
||||
/* Boot from USDHC */
|
||||
port = (val >> 11) & 0x3;
|
||||
switch (port) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
|
||||
ARRAY_SIZE(usdhc1_pads));
|
||||
gpio_direction_input(USDHC1_CD_GPIO);
|
||||
usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
|
||||
ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
|
||||
usdhc_cfg[0].max_bus_width = 4;
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
break;
|
||||
case 2:
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
|
||||
ARRAY_SIZE(usdhc3_pads));
|
||||
gpio_direction_input(USDHC3_CD_GPIO);
|
||||
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
|
||||
usdhc_cfg[0].max_bus_width = 4;
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
break;
|
||||
}
|
||||
|
||||
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||
}
|
||||
|
||||
const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
|
||||
.dram_sdqs0 = 0x00003030,
|
||||
.dram_sdqs1 = 0x00003030,
|
||||
.dram_sdqs2 = 0x00003030,
|
||||
.dram_sdqs3 = 0x00003030,
|
||||
.dram_dqm0 = 0x00000030,
|
||||
.dram_dqm1 = 0x00000030,
|
||||
.dram_dqm2 = 0x00000030,
|
||||
.dram_dqm3 = 0x00000030,
|
||||
.dram_cas = 0x00000030,
|
||||
.dram_ras = 0x00000030,
|
||||
.dram_sdclk_0 = 0x00000028,
|
||||
.dram_reset = 0x00000030,
|
||||
.dram_sdba2 = 0x00000000,
|
||||
.dram_odt0 = 0x00000008,
|
||||
.dram_odt1 = 0x00000008,
|
||||
};
|
||||
|
||||
const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
|
||||
.grp_b0ds = 0x00000030,
|
||||
.grp_b1ds = 0x00000030,
|
||||
.grp_b2ds = 0x00000030,
|
||||
.grp_b3ds = 0x00000030,
|
||||
.grp_addds = 0x00000030,
|
||||
.grp_ctlds = 0x00000030,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
.grp_ddrpke = 0x00000000,
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_ddr_type = 0x00080000,
|
||||
};
|
||||
|
||||
const struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
||||
.p0_mpdgctrl0 = 0x20000000,
|
||||
.p0_mpdgctrl1 = 0x00000000,
|
||||
.p0_mprddlctl = 0x4241444a,
|
||||
.p0_mpwrdlctl = 0x3030312b,
|
||||
.mpzqlp2ctl = 0x1b4700c7,
|
||||
};
|
||||
|
||||
static struct mx6_lpddr2_cfg mem_ddr = {
|
||||
.mem_speed = 800,
|
||||
.density = 4,
|
||||
.width = 32,
|
||||
.banks = 8,
|
||||
.rowaddr = 14,
|
||||
.coladdr = 10,
|
||||
.trcd_lp = 2000,
|
||||
.trppb_lp = 2000,
|
||||
.trpab_lp = 2250,
|
||||
.trasmin = 4200,
|
||||
};
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
writel(0xFFFFFFFF, &ccm->CCGR0);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR1);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR2);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR3);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR4);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR5);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR6);
|
||||
|
||||
writel(0x00260324, &ccm->cbcmr);
|
||||
}
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
struct mx6_ddr_sysinfo sysinfo = {
|
||||
.dsize = mem_ddr.width / 32,
|
||||
.cs_density = 20,
|
||||
.ncs = 2,
|
||||
.cs1_mirror = 0,
|
||||
.walat = 0,
|
||||
.ralat = 2,
|
||||
.mif3_mode = 3,
|
||||
.bi_on = 1,
|
||||
.rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
|
||||
.rtt_nom = 0,
|
||||
.sde_to_rst = 0, /* LPDDR2 does not need this field */
|
||||
.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
|
||||
.ddr_type = DDR_TYPE_LPDDR2,
|
||||
.refsel = 0, /* Refresh cycles at 64KHz */
|
||||
.refr = 3, /* 4 refresh commands per refresh cycle */
|
||||
};
|
||||
mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
||||
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
ccgr_init();
|
||||
|
||||
/* iomux and setup of i2c */
|
||||
board_early_init_f();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* load/boot image from boot device */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user