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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
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source/bootloader/u-boot-2020.01/board/hisilicon/hikey/Kconfig
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if TARGET_HIKEY
config SYS_BOARD
default "hikey"
config SYS_VENDOR
default "hisilicon"
config SYS_SOC
default "hi6220"
config SYS_CONFIG_NAME
default "hikey"
endif
source/bootloader/u-boot-2020.01/board/hisilicon/hikey/MAINTAINERS
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HIKEY BOARD
M: Peter Griffin <peter.griffin@linaro.org>
S: Maintained
F: board/hisilicon/hikey
F: include/configs/hikey.h
F: configs/hikey_defconfig
source/bootloader/u-boot-2020.01/board/hisilicon/hikey/Makefile
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# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y := hikey.o
source/bootloader/u-boot-2020.01/board/hisilicon/hikey/README
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Introduction
============
HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: -
* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
* ARM Mali 450-MP4 GPU
* 1GB 800MHz LPDDR3 DRAM
* 4GB eMMC Flash Storage
* microSD
* 802.11a/b/g/n WiFi, Bluetooth
The HiKey schematic can be found here: -
https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/HiKey_schematics_LeMaker_version_Rev_A1.pdf
The SoC datasheet can be found here: -
https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Currently the u-boot port supports: -
* USB
* eMMC
* SD card
* GPIO
The HiKey U-Boot port has been tested with l-loader, booting ATF, which then boots
U-Boot as the bl33.bin executable.
Compile from source
===================
First get all the sources
> mkdir -p ~/hikey/src ~/hikey/bin
> cd ~/hikey/src
> git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
> git clone https://github.com/ARM-software/arm-trusted-firmware
> git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
> git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
> git clone https://github.com/96boards-hikey/atf-fastboot
> wget https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/hisi-idt.py
Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source.
The latest version can be obtained from the OpenPlatformPkg repo.
> cp OpenPlatformPkg/Platforms/Hisilicon/HiKey/Binary/mcuimage.bin ~/hikey/bin/
Get nvme.img binary
> wget -P ~/hikey/bin https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/nvme.img
Compile U-Boot
==============
> cd ~/hikey/src/u-boot
> make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
> make CROSS_COMPILE=aarch64-linux-gnu-
> cp u-boot.bin ~/hikey/bin
Compile ARM Trusted Firmware (ATF)
==================================
> cd ~/hikey/src/arm-trusted-firmware
> make CROSS_COMPILE=aarch64-linux-gnu- all fip \
SCP_BL2=~/hikey/bin/mcuimage.bin \
BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
Copy the resulting FIP binary
> cp build/hikey/debug/fip.bin ~/hikey/bin
Compile ATF Fastboot
====================
> cd ~/hikey/src/atf-fastboot
> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=hikey DEBUG=1
Compile l-loader
================
> cd ~/hikey/src/l-loader
> ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl1.bin
> ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl2.bin
> ln -sf ~/hikey/src/atf-fastboot/build/hikey/debug/bl1.bin fastboot.bin
> make hikey PTABLE_LST=aosp-8g
Copy the resulting binaries
> cp *.img ~/hikey/bin
> cp l-loader.bin ~/hikey/bin
> cp recovery.bin ~/hikey/bin
These instructions are adapted from
https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey.rst
FLASHING
========
1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
the hisi-idt.py utility. Then connect a USB A to B mini cable from your PC to the USB OTG port of HiKey and execute the below command.
The command below assumes HiKey enumerated as the first USB serial port
> sudo python ~/hikey/src/hisi-idt.py -d /dev/ttyUSB0 --img1 ~/hikey/bin/recovery.bin
2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device.
> sudo fastboot devices
0123456789ABCDEF fastboot
3. Flash the images
> sudo fastboot flash ptable ~/hikey/bin/prm_ptable.img
> sudo fastboot flash loader ~/hikey/bin/l-loader.bin
> sudo fastboot flash fastboot ~/hikey/bin/fip.bin
> sudo fastboot flash nvme ~/hikey/bin/nvme.img
4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
have ATF, booting u-boot from eMMC.
Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
will get 'dwc_otg_core_host_init: Timeout!' errors.
See working boot trace below on UART3 available at Low Speed Expansion header: -
NOTICE: BL2: v1.5(debug):v1.5-694-g6d4f6aea
NOTICE: BL2: Built : 09:21:42, Aug 29 2018
INFO: BL2: Doing platform setup
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 150mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 266mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 400mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 533mhz
INFO: ddr3 rank1 init pass
INFO: succeed to set ddrc 800mhz
INFO: Samsung DDR
INFO: ddr test value:0xa5a55a5a
INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
INFO: BL2: TrustZone: protecting 4194304 bytes of memory at 0x3e800000
INFO: [BDID] [fff91c18] midr: 0x410fd033
INFO: init_acpu_dvfs: pmic version 17
INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00.
INFO: acpu_dvfs_volt_init: success!
INFO: acpu_dvfs_set_freq: support freq num is 5
INFO: acpu_dvfs_set_freq: start prof is 0x4
INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5
INFO: acpu_dvfs_set_freq: voltage:
INFO: - 0: 0x49
INFO: - 1: 0x49
INFO: - 2: 0x50
INFO: - 3: 0x60
INFO: - 4: 0x78
NOTICE: acpu_dvfs_set_freq: set acpu freq success!INFO: BL2: Loading image id 2
INFO: Loading image id=2 at address 0x1000000
INFO: Image id=2 loaded: 0x1000000 - 0x1023d00
INFO: hisi_mcu_load_image: mcu sections 0:
INFO: hisi_mcu_load_image: src = 0x1000200
INFO: hisi_mcu_load_image: dst = 0xf6000000
INFO: hisi_mcu_load_image: size = 31184
INFO: hisi_mcu_load_image: [SRC 0x1000200] 0x8000 0x3701 0x7695 0x7689
INFO: hisi_mcu_load_image: [DST 0xf6000000] 0x8000 0x3701 0x7695 0x7689
INFO: hisi_mcu_load_image: mcu sections 1:
INFO: hisi_mcu_load_image: src = 0x1007bd0
INFO: hisi_mcu_load_image: dst = 0x5e00000
INFO: hisi_mcu_load_image: size = 93828
INFO: hisi_mcu_load_image: [SRC 0x1007bd0] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
INFO: hisi_mcu_load_image: [DST 0x5e00000] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
INFO: hisi_mcu_load_image: mcu sections 2:
INFO: hisi_mcu_load_image: src = 0x101ea54
INFO: hisi_mcu_load_image: dst = 0x5e16e84
INFO: hisi_mcu_load_image: size = 15428
INFO: hisi_mcu_load_image: [SRC 0x101ea54] 0x9 0x1020640 0x10001 0x8f0d180
INFO: hisi_mcu_load_image: [DST 0x5e16e84] 0x9 0x1020640 0x10001 0x8f0d180
INFO: hisi_mcu_load_image: mcu sections 3:
INFO: hisi_mcu_load_image: src = 0x1022698
INFO: hisi_mcu_load_image: dst = 0x5e22a10
INFO: hisi_mcu_load_image: size = 3060
INFO: hisi_mcu_load_image: [SRC 0x1022698] 0x0 0x0 0x0 0x0
INFO: hisi_mcu_load_image: [DST 0x5e22a10] 0x0 0x0 0x0 0x0
INFO: hisi_mcu_load_image: mcu sections 4:
INFO: hisi_mcu_load_image: src = 0x102328c
INFO: hisi_mcu_load_image: dst = 0x5e23604
INFO: hisi_mcu_load_image: size = 2616
INFO: hisi_mcu_load_image: [SRC 0x102328c] 0xf80000a0 0x0 0xf80000ac 0x0
INFO: hisi_mcu_load_image: [DST 0x5e23604] 0xf80000a0 0x0 0xf80000ac 0x0
INFO: hisi_mcu_start_run: AO_SC_SYS_CTRL2=0
INFO: plat_hikey_bl2_handle_scp_bl2: MCU PC is at 0x42933301
INFO: plat_hikey_bl2_handle_scp_bl2: AO_SC_PERIPH_CLKSTAT4 is 0x3b018f09
WARNING: BL2: Platform setup already done!!
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0xf9858000
INFO: Image id=3 loaded: 0xf9858000 - 0xf9860058
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x35000000
INFO: Image id=5 loaded: 0x35000000 - 0x35061cd2
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0xf9858000
INFO: SPSR = 0x3cd
NOTICE: BL31: v1.5(debug):v1.5-694-g6d4f6aea
NOTICE: BL31: Built : 09:21:44, Aug 29 2018
WARNING: Using deprecated integer interrupt array in gicv2_driver_data_t
WARNING: Please migrate to using an interrupt_prop_t array
INFO: ARM GICv2 driver initialized
INFO: BL31: Initializing runtime services
INFO: BL31: cortex_a53: CPU workaround for disable_non_temporal_hint was applied
INFO: BL31: cortex_a53: CPU workaround for 843419 was applied
INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x35000000
INFO: SPSR = 0x3c9
U-Boot 2018.09-rc1 (Aug 22 2018 - 14:55:49 +0530)hikey
DRAM: 990 MiB
HI6553 PMIC init
MMC: config_sd_carddetect: SD card present
Hisilicon DWMMC: 0, Hisilicon DWMMC: 1
Loading Environment from FAT... Unable to use mmc 1:1... Failed (-5)
In: uart@f7113000
Out: uart@f7113000
Err: uart@f7113000
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
starting USB...
USB0: scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found
source/bootloader/u-boot-2020.01/board/hisilicon/hikey/build-tf.mak
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CROSS_COMPILE := aarch64-linux-gnu-
output_dir := $(PWD)/../bin
makejobs := $(shell grep '^processor' /proc/cpuinfo | sort -u | wc -l)
makethreads := $(shell dc -e "$(makejobs) 1 + p")
make_options := GCC49_AARCH64_PREFIX=$CROSS_COMPILE \
-j$(makethreads) -l$(makejobs)
BL30_HIKEY := $(output_dir)/mcuimage.bin
BL33_HIKEY := $(output_dir)/u-boot-hikey.bin
.PHONY: help
help:
@echo "**** Common Makefile ****"
@echo "example:"
@echo "make -f build-tf.mak build"
.PHONY: have-crosscompiler
have-crosscompiler:
@echo -n "Check that $(CROSS_COMPILE)gcc is available..."
@which $(CROSS_COMPILE)gcc > /dev/null ; \
if [ ! $$? -eq 0 ] ; then \
echo "ERROR: cross-compiler $(CROSS_COMPILE)gcc not in PATH=$$PATH!" ; \
echo "ABORTING." ; \
exit 1 ; \
else \
echo "OK" ;\
fi
build: have-crosscompiler FORCE
@echo "Build TF for Hikey..."
rm -rf build/
CROSS_COMPILE=$(CROSS_COMPILE) \
make all fip \
BL30=$(BL30_HIKEY) \
BL33=$(BL33_HIKEY) \
DEBUG=1 \
PLAT=hikey
@echo "Copy resulting binaries..."
cp build/hikey/debug/bl1.bin $(output_dir)/bl1-hikey.bin
cp build/hikey/debug/fip.bin $(output_dir)/fip-hikey.bin
FORCE:
source/bootloader/u-boot-2020.01/board/hisilicon/hikey/hikey.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015 Linaro
* Peter Griffin <peter.griffin@linaro.org>
*/
#include <common.h>
#include <dm.h>
#include <dm/platform_data/serial_pl01x.h>
#include <errno.h>
#include <malloc.h>
#include <netdev.h>
#include <asm/io.h>
#include <usb.h>
#include <power/hi6553_pmic.h>
#include <asm-generic/gpio.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/periph.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/hi6220.h>
#include <asm/armv8/mmu.h>
/*TODO drop this table in favour of device tree */
static const struct hikey_gpio_platdata hi6220_gpio[] = {
{ 0, HI6220_GPIO_BASE(0)},
{ 1, HI6220_GPIO_BASE(1)},
{ 2, HI6220_GPIO_BASE(2)},
{ 3, HI6220_GPIO_BASE(3)},
{ 4, HI6220_GPIO_BASE(4)},
{ 5, HI6220_GPIO_BASE(5)},
{ 6, HI6220_GPIO_BASE(6)},
{ 7, HI6220_GPIO_BASE(7)},
{ 8, HI6220_GPIO_BASE(8)},
{ 9, HI6220_GPIO_BASE(9)},
{ 10, HI6220_GPIO_BASE(10)},
{ 11, HI6220_GPIO_BASE(11)},
{ 12, HI6220_GPIO_BASE(12)},
{ 13, HI6220_GPIO_BASE(13)},
{ 14, HI6220_GPIO_BASE(14)},
{ 15, HI6220_GPIO_BASE(15)},
{ 16, HI6220_GPIO_BASE(16)},
{ 17, HI6220_GPIO_BASE(17)},
{ 18, HI6220_GPIO_BASE(18)},
{ 19, HI6220_GPIO_BASE(19)},
};
U_BOOT_DEVICES(hi6220_gpios) = {
{ "gpio_hi6220", &hi6220_gpio[0] },
{ "gpio_hi6220", &hi6220_gpio[1] },
{ "gpio_hi6220", &hi6220_gpio[2] },
{ "gpio_hi6220", &hi6220_gpio[3] },
{ "gpio_hi6220", &hi6220_gpio[4] },
{ "gpio_hi6220", &hi6220_gpio[5] },
{ "gpio_hi6220", &hi6220_gpio[6] },
{ "gpio_hi6220", &hi6220_gpio[7] },
{ "gpio_hi6220", &hi6220_gpio[8] },
{ "gpio_hi6220", &hi6220_gpio[9] },
{ "gpio_hi6220", &hi6220_gpio[10] },
{ "gpio_hi6220", &hi6220_gpio[11] },
{ "gpio_hi6220", &hi6220_gpio[12] },
{ "gpio_hi6220", &hi6220_gpio[13] },
{ "gpio_hi6220", &hi6220_gpio[14] },
{ "gpio_hi6220", &hi6220_gpio[15] },
{ "gpio_hi6220", &hi6220_gpio[16] },
{ "gpio_hi6220", &hi6220_gpio[17] },
{ "gpio_hi6220", &hi6220_gpio[18] },
{ "gpio_hi6220", &hi6220_gpio[19] },
};
DECLARE_GLOBAL_DATA_PTR;
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct pl01x_serial_platdata serial_platdata = {
#if CONFIG_CONS_INDEX == 1
.base = HI6220_UART0_BASE,
#elif CONFIG_CONS_INDEX == 4
.base = HI6220_UART3_BASE,
#else
#error "Unsupported console index value."
#endif
.type = TYPE_PL011,
.clock = 19200000
};
U_BOOT_DEVICE(hikey_seriala) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
};
#endif
static struct mm_region hikey_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = hikey_mem_map;
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_uart_init(void)
{
switch (CONFIG_CONS_INDEX) {
case 1:
hi6220_pinmux_config(PERIPH_ID_UART0);
break;
case 4:
hi6220_pinmux_config(PERIPH_ID_UART3);
break;
default:
debug("%s: Unsupported UART selected\n", __func__);
return -1;
}
return 0;
}
int board_early_init_f(void)
{
board_uart_init();
return 0;
}
#endif
struct peri_sc_periph_regs *peri_sc =
(struct peri_sc_periph_regs *)HI6220_PERI_BASE;
struct alwayson_sc_regs *ao_sc =
(struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
/* status offset from enable reg */
#define STAT_EN_OFF 0x2
void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
{
uint32_t data;
data = readl(clk_base);
data |= bitfield;
writel(bitfield, clk_base);
do {
data = readl(clk_base + STAT_EN_OFF);
} while ((data & bitfield) == 0);
}
/* status offset from disable reg */
#define STAT_DIS_OFF 0x1
void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
{
uint32_t data;
data = readl(clk_base);
data |= bitfield;
writel(data, clk_base);
do {
data = readl(clk_base + STAT_DIS_OFF);
} while (data & bitfield);
}
#define EYE_PATTERN 0x70533483
int board_usb_init(int index, enum usb_init_type init)
{
unsigned int data;
/* enable USB clock */
hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
/* take usb IPs out of reset */
writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
&peri_sc->rst0_dis);
do {
data = readl(&peri_sc->rst0_stat);
data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
} while (data);
/*CTRL 5*/
data = readl(&peri_sc->ctrl5);
data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
data |= 0x300;
writel(data, &peri_sc->ctrl5);
/*CTRL 4*/
/* configure USB PHY */
data = readl(&peri_sc->ctrl4);
/* make PHY out of low power mode */
data &= ~PERI_CTRL4_PICO_SIDDQ;
data &= ~PERI_CTRL4_PICO_OGDISABLE;
data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
writel(data, &peri_sc->ctrl4);
writel(EYE_PATTERN, &peri_sc->ctrl8);
mdelay(5);
return 0;
}
static int config_sd_carddetect(void)
{
int ret;
/* configure GPIO8 as nopull */
writel(0, 0xf8001830);
gpio_request(8, "SD CD");
gpio_direction_input(8);
ret = gpio_get_value(8);
if (!ret) {
printf("%s: SD card present\n", __func__);
return 1;
}
printf("%s: SD card not present\n", __func__);
return 0;
}
static void mmc1_init_pll(void)
{
uint32_t data;
/* select SYSPLL as the source of MMC1 */
/* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
do {
data = readl(&peri_sc->clk0_sel);
} while (!(data & (1 << 11)));
/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
writel(1 << 30, &peri_sc->clk0_sel);
do {
data = readl(&peri_sc->clk0_sel);
} while (data & (1 << 14));
hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
do {
/* 1.2GHz / 50 = 24MHz */
writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
data = readl(&peri_sc->clkcfg8bit2);
} while ((data & 0x31) != 0x31);
}
static void mmc1_reset_clk(void)
{
unsigned int data;
/* disable mmc1 bus clock */
hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
/* enable mmc1 bus clock */
hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
/* reset mmc1 clock domain */
writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
/* bypass mmc1 clock phase */
data = readl(&peri_sc->ctrl2);
data |= 3 << 2;
writel(data, &peri_sc->ctrl2);
/* disable low power */
data = readl(&peri_sc->ctrl13);
data |= 1 << 4;
writel(data, &peri_sc->ctrl13);
do {
data = readl(&peri_sc->rst0_stat);
} while (!(data & PERI_RST0_MMC1));
/* unreset mmc1 clock domain */
writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
do {
data = readl(&peri_sc->rst0_stat);
} while (data & PERI_RST0_MMC1);
}
static void mmc0_reset_clk(void)
{
unsigned int data;
/* disable mmc0 bus clock */
hi6220_clk_disable(PERI_CLK0_MMC0, &peri_sc->clk0_dis);
/* enable mmc0 bus clock */
hi6220_clk_enable(PERI_CLK0_MMC0, &peri_sc->clk0_en);
/* reset mmc0 clock domain */
writel(PERI_RST0_MMC0, &peri_sc->rst0_en);
/* bypass mmc0 clock phase */
data = readl(&peri_sc->ctrl2);
data |= 3;
writel(data, &peri_sc->ctrl2);
/* disable low power */
data = readl(&peri_sc->ctrl13);
data |= 1 << 3;
writel(data, &peri_sc->ctrl13);
do {
data = readl(&peri_sc->rst0_stat);
} while (!(data & PERI_RST0_MMC0));
/* unreset mmc0 clock domain */
writel(PERI_RST0_MMC0, &peri_sc->rst0_dis);
do {
data = readl(&peri_sc->rst0_stat);
} while (data & PERI_RST0_MMC0);
}
/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
static void hi6220_pmussi_init(void)
{
uint32_t data;
/* Take PMUSSI out of reset */
writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
&ao_sc->rst4_dis);
do {
data = readl(&ao_sc->rst4_stat);
} while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
/* set PMU SSI clock latency for read operation */
data = readl(&ao_sc->mcu_subsys_ctrl3);
data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
writel(data, &ao_sc->mcu_subsys_ctrl3);
/* enable PMUSSI clock */
data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
hi6220_clk_enable(data, &ao_sc->clk5_en);
/* Output high to PMIC on PWR_HOLD_GPIO0_0 */
gpio_request(0, "PWR_HOLD_GPIO0_0");
gpio_direction_output(0, 1);
}
int misc_init_r(void)
{
return 0;
}
int board_init(void)
{
return 0;
}
#ifdef CONFIG_MMC
static int init_dwmmc(void)
{
int ret = 0;
#ifdef CONFIG_MMC_DW
/* mmc0 pll is already configured by ATF */
mmc0_reset_clk();
ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
if (ret)
printf("%s: Error configuring pinmux for eMMC (%d)\n"
, __func__, ret);
ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
if (ret)
printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
/* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
mmc1_init_pll();
mmc1_reset_clk();
ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
if (ret)
printf("%s: Error configuring pinmux for eMMC (%d)\n"
, __func__, ret);
config_sd_carddetect();
ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
if (ret)
printf("%s: Error adding SD port (%d)\n", __func__, ret);
#endif
return ret;
}
/* setup board specific PMIC */
int power_init_board(void)
{
/* init the hi6220 pmussi ip */
hi6220_pmussi_init();
power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
return 0;
}
int board_mmc_init(bd_t *bis)
{
int ret;
/* add the eMMC and sd ports */
ret = init_dwmmc();
if (ret)
debug("init_dwmmc failed\n");
return ret;
}
#endif
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init_banksize(void)
{
/*
* Reserve regions below from DT memory node (which gets generated
* by U-Boot from the dram banks in arch_fixup_fdt() before booting
* the kernel. This will then match the kernel hikey dts memory node.
*
* 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
* 0x05f0,1000 - 0x05f0,1fff: Reboot reason
* 0x06df,f000 - 0x06df,ffff: Mailbox message data
* 0x0740,f000 - 0x0740,ffff: MCU firmware section
* 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
* 0x3e00,0000 - 0x3fff,ffff: OP-TEE
*/
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = 0x05e00000;
gd->bd->bi_dram[1].start = 0x05f00000;
gd->bd->bi_dram[1].size = 0x00001000;
gd->bd->bi_dram[2].start = 0x05f02000;
gd->bd->bi_dram[2].size = 0x00efd000;
gd->bd->bi_dram[3].start = 0x06e00000;
gd->bd->bi_dram[3].size = 0x0060f000;
gd->bd->bi_dram[4].start = 0x07410000;
gd->bd->bi_dram[4].size = 0x1aaf0000;
gd->bd->bi_dram[5].start = 0x22000000;
gd->bd->bi_dram[5].size = 0x1c000000;
return 0;
}
void reset_cpu(ulong addr)
{
writel(0x48698284, &ao_sc->stat0);
wfi();
}