GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/board/intel/edison/Kconfig

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+if TARGET_EDISON
+
+config SYS_BOARD
+	default "edison"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "tangier"
+
+config SYS_CONFIG_NAME
+	default "edison"
+
+config SYS_TEXT_BASE
+	default 0x01101000
+
+config ROM_TABLE_ADDR
+	default 0x0e4500
+
+config ROM_TABLE_SIZE
+	default 0x007b00
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_LOAD_FROM_32_BIT
+	select INTEL_MID
+	select INTEL_TANGIER
+	select BOARD_LATE_INIT
+	select MD5
+
+endif

source/bootloader/u-boot-2020.01/board/intel/edison/MAINTAINERS

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+Intel Edison Board
+M:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+S:	Maintained
+F:	board/intel/edison
+F:	include/configs/edison.h
+F:	configs/edison_defconfig

source/bootloader/u-boot-2020.01/board/intel/edison/Makefile

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+#
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= start.o edison.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o

source/bootloader/u-boot-2020.01/board/intel/edison/config.mk

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+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+#
+# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+# Copyright (c) 2017 Intel Corporation
+#
+
+# Add 4096 bytes of zeroes to u-boot.bin
+quiet_cmd_mkalign_eds = EDSALGN $@
+cmd_mkalign_eds =							\
+	dd if=$^ of=$@ bs=4k seek=1 2>/dev/null &&			\
+	mv $@ $^
+
+ALL-y += u-boot-align.bin
+u-boot-align.bin: u-boot.bin
+	$(call if_changed,mkalign_eds)
+
+HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros

source/bootloader/u-boot-2020.01/board/intel/edison/dsdt.asl

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+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * Partially based on dsdt.asl for other x86 boards
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+}

source/bootloader/u-boot-2020.01/board/intel/edison/edison.c

@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Intel Corporation
+ */
+#include <common.h>
+#include <dwc3-uboot.h>
+#include <env.h>
+#include <init.h>
+#include <mmc.h>
+#include <u-boot/md5.h>
+#include <usb.h>
+#include <watchdog.h>
+
+#include <linux/usb/gadget.h>
+
+#include <asm/cache.h>
+#include <asm/pmu.h>
+#include <asm/scu.h>
+#include <asm/u-boot-x86.h>
+
+/* List of Intel Tangier LSSs */
+#define PMU_LSS_TANGIER_SDIO0_01	1
+
+int board_early_init_r(void)
+{
+	pmu_turn_power(PMU_LSS_TANGIER_SDIO0_01, true);
+	return 0;
+}
+
+static struct dwc3_device dwc3_device_data = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = CONFIG_SYS_USB_OTG_BASE,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+};
+
+int usb_gadget_handle_interrupts(int controller_index)
+{
+	dwc3_uboot_handle_interrupt(controller_index);
+	WATCHDOG_RESET();
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	if (index == 0 && init == USB_INIT_DEVICE)
+		return dwc3_uboot_init(&dwc3_device_data);
+	return -EINVAL;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_uboot_exit(index);
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static void assign_serial(void)
+{
+	struct mmc *mmc = find_mmc_device(0);
+	unsigned char ssn[16];
+	char usb0addr[18];
+	char serial[33];
+	int i;
+
+	if (!mmc)
+		return;
+
+	md5((unsigned char *)mmc->cid, sizeof(mmc->cid), ssn);
+
+	snprintf(usb0addr, sizeof(usb0addr), "02:00:86:%02x:%02x:%02x",
+		 ssn[13], ssn[14], ssn[15]);
+	env_set("usb0addr", usb0addr);
+
+	for (i = 0; i < 16; i++)
+		snprintf(&serial[2 * i], 3, "%02x", ssn[i]);
+	env_set("serial#", serial);
+
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+	env_save();
+#endif
+}
+
+static void assign_hardware_id(void)
+{
+	struct ipc_ifwi_version v;
+	char hardware_id[4];
+	int ret;
+
+	ret = scu_ipc_command(IPCMSG_GET_FW_REVISION, 1, NULL, 0, (u32 *)&v, 4);
+	if (ret < 0)
+		printf("Can't retrieve hardware revision\n");
+
+	snprintf(hardware_id, sizeof(hardware_id), "%02X", v.hardware_id);
+	env_set("hardware_id", hardware_id);
+
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+	env_save();
+#endif
+}
+
+int board_late_init(void)
+{
+	if (!env_get("serial#"))
+		assign_serial();
+
+	if (!env_get("hardware_id"))
+		assign_hardware_id();
+
+	return 0;
+}

source/bootloader/u-boot-2020.01/board/intel/edison/start.S

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ */
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+	/* No 32-bit board specific initialisation */
+	jmp	early_board_init_ret