GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,14 @@
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if TARGET_OMAP3_IGEP00X0
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config SYS_BOARD
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default "igep00x0"
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config SYS_VENDOR
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default "isee"
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config SYS_CONFIG_NAME
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default "omap3_igep00x0"
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source "board/ti/common/Kconfig"
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endif
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@@ -0,0 +1,6 @@
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IGEP00X0 BOARD
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M: Enric Balletbo i Serra <eballetbo@gmail.com>
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S: Maintained
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F: board/isee/igep00x0/
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F: include/configs/omap3_igep00x0.h
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F: configs/igep00x0_defconfig
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@@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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ifdef CONFIG_SPL_BUILD
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obj-y := spl.o common.o
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else
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obj-y := igep00x0.o common.o
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endif
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@@ -0,0 +1,67 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <twl4030.h>
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#include <asm/io.h>
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#include <asm/omap_mmc.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <jffs2/load_kernel.h>
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#include <linux/mtd/rawnand.h>
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#include "igep00x0.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_DEFAULT();
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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int loops = 100;
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/* find out flash memory type, assume NAND first */
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gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
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gpmc_init();
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/* Issue a RESET and then READID */
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writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
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writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
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while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
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!= NAND_STATUS_READY) {
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udelay(1);
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if (--loops == 0) {
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gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
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gpmc_init(); /* reinitialize for OneNAND */
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break;
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}
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}
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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#if defined(CONFIG_MMC)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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void board_mmc_power_init(void)
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{
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twl4030_power_mmc_init(0);
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}
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#endif
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@@ -0,0 +1,259 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010
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* ISEE 2007 SL, <www.iseebcn.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <status_led.h>
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#include <dm.h>
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#include <ns16550.h>
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#include <twl4030.h>
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#include <netdev.h>
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#include <spl.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/onenand.h>
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#include <jffs2/load_kernel.h>
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#include <mtd_node.h>
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#include <fdt_support.h>
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#include "igep00x0.h"
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static const struct ns16550_platdata igep_serial = {
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.base = OMAP34XX_UART3,
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.reg_shift = 2,
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.clock = V_NS16550_CLK,
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.fcr = UART_FCR_DEFVAL,
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};
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U_BOOT_DEVICE(igep_uart) = {
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"ns16550_serial",
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&igep_serial
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};
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/*
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* Routine: get_board_revision
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* Description: GPIO_28 and GPIO_129 are used to read board and revision from
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* IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from
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* IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because
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* this functionality is shared by USB HOST.
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* Once USB reset is applied, U-boot configures these pins as input pullup to
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* detect board and revision:
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* IGEP0020-RF = 0b00
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* IGEP0020-RC = 0b01
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* IGEP0030-RG = 0b10
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* IGEP0030-RE = 0b11
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*/
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static int get_board_revision(void)
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{
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int revision;
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gpio_request(IGEP0030_USB_TRANSCEIVER_RESET,
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"igep0030_usb_transceiver_reset");
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gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0);
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gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection");
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gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION);
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revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION);
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gpio_free(GPIO_IGEP00X0_BOARD_DETECTION);
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gpio_request(GPIO_IGEP00X0_REVISION_DETECTION,
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"igep00x0_revision_detection");
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gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION);
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revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION);
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gpio_free(GPIO_IGEP00X0_REVISION_DETECTION);
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gpio_free(IGEP0030_USB_TRANSCEIVER_RESET);
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return revision;
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}
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int onenand_board_init(struct mtd_info *mtd)
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{
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if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
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struct onenand_chip *this = mtd->priv;
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this->base = (void *)CONFIG_SYS_ONENAND_BASE;
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return 0;
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}
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return 1;
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}
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#if defined(CONFIG_CMD_NET)
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static void reset_net_chip(int gpio)
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{
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if (!gpio_request(gpio, "eth nrst")) {
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gpio_direction_output(gpio, 1);
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udelay(1);
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gpio_set_value(gpio, 0);
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udelay(40);
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gpio_set_value(gpio, 1);
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mdelay(10);
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}
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}
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/*
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* Routine: setup_net_chip
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* Description: Setting up the configuration GPMC registers specific to the
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* Ethernet hardware.
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*/
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static void setup_net_chip(void)
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{
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struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
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static const u32 gpmc_lan_config[] = {
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NET_LAN9221_GPMC_CONFIG1,
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NET_LAN9221_GPMC_CONFIG2,
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NET_LAN9221_GPMC_CONFIG3,
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NET_LAN9221_GPMC_CONFIG4,
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NET_LAN9221_GPMC_CONFIG5,
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NET_LAN9221_GPMC_CONFIG6,
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};
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enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
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CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
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/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
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writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
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/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
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writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
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/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
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writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
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&ctrl_base->gpmc_nadv_ale);
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reset_net_chip(64);
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SMC911X
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return smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#else
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return 0;
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#endif
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}
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#else
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static inline void setup_net_chip(void) {}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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static int ft_enable_by_compatible(void *blob, char *compat, int enable)
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{
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int off = fdt_node_offset_by_compatible(blob, -1, compat);
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if (off < 0)
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return off;
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if (enable)
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fdt_status_okay(blob, off);
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else
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fdt_status_disabled(blob, off);
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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#ifdef CONFIG_FDT_FIXUP_PARTITIONS
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static const struct node_info nodes[] = {
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{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
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{ "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
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};
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fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
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#endif
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ft_enable_by_compatible(blob, "ti,omap2-nand",
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gpmc_cs0_flash == MTD_DEV_TYPE_NAND);
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ft_enable_by_compatible(blob, "ti,omap2-onenand",
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gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND);
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return 0;
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}
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#endif
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void set_led(void)
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{
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switch (get_board_revision()) {
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case 0:
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case 1:
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gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led");
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gpio_direction_output(IGEP0020_GPIO_LED, 1);
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break;
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case 2:
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case 3:
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gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led");
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gpio_direction_output(IGEP0030_GPIO_LED, 0);
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break;
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default:
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/* Should not happen... */
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break;
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}
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}
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void set_boardname(void)
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{
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char rev[5] = { 'F','C','G','E', };
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int i = get_board_revision();
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rev[i+1] = 0;
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env_set("board_rev", rev + i);
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env_set("board_name", i < 2 ? "igep0020" : "igep0030");
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}
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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t2_t *t2_base = (t2_t *)T2_BASE;
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u32 pbias_lite;
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twl4030_power_init();
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/* set VSIM to 1.8V */
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twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
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TWL4030_PM_RECEIVER_VSIM_VSEL_18,
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TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
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TWL4030_PM_RECEIVER_DEV_GRP_P1);
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/* set up dual-voltage GPIOs to 1.8V */
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pbias_lite = readl(&t2_base->pbias_lite);
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pbias_lite &= ~PBIASLITEVMODE1;
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pbias_lite |= PBIASLITEPWRDNZ1;
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writel(pbias_lite, &t2_base->pbias_lite);
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if (get_cpu_family() == CPU_OMAP36XX)
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writel(readl(OMAP34XX_CTRL_WKUP_CTRL) |
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OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
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OMAP34XX_CTRL_WKUP_CTRL);
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setup_net_chip();
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omap_die_id_display();
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set_led();
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set_boardname();
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return 0;
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}
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void board_mtdparts_default(const char **mtdids, const char **mtdparts)
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{
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struct mtd_info *mtd = get_mtd_device(NULL, 0);
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if (mtd) {
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static char ids[24];
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static char parts[48];
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const char *linux_name = "omap2-nand";
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if (strncmp(mtd->name, "onenand0", 8) == 0)
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linux_name = "omap2-onenand";
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snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
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snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
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linux_name, 4 * mtd->erasesize >> 10);
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*mtdids = ids;
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*mtdparts = parts;
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}
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}
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@@ -0,0 +1,127 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* ISEE 2007 SL, <www.iseebcn.com>
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*/
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#ifndef _IGEP00X0_H_
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#define _IGEP00X0_H_
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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* PTD - Pull type Down
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* M0 - Mode 0
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* The commented string gives the final mux configuration for that pin
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*/
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#define MUX_DEFAULT()\
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\
|
||||
MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
|
||||
#endif
|
||||
@@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
#include <serial.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <jffs2/load_kernel.h>
|
||||
#include <linux/mtd/rawnand.h>
|
||||
#include "igep00x0.h"
|
||||
|
||||
/*
|
||||
* Routine: get_board_mem_timings
|
||||
* Description: If we use SPL then there is no x-loader nor config header
|
||||
* so we have to setup the DDR timings ourself on both banks.
|
||||
*/
|
||||
void get_board_mem_timings(struct board_sdrc_timings *timings)
|
||||
{
|
||||
int mfr, id, err = identify_nand_chip(&mfr, &id);
|
||||
|
||||
timings->mr = MICRON_V_MR_165;
|
||||
if (!err) {
|
||||
switch (mfr) {
|
||||
case NAND_MFR_HYNIX:
|
||||
timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
|
||||
timings->ctrla = HYNIX_V_ACTIMA_200;
|
||||
timings->ctrlb = HYNIX_V_ACTIMB_200;
|
||||
break;
|
||||
case NAND_MFR_MICRON:
|
||||
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
|
||||
timings->ctrla = MICRON_V_ACTIMA_200;
|
||||
timings->ctrlb = MICRON_V_ACTIMB_200;
|
||||
break;
|
||||
default:
|
||||
/* Should not happen... */
|
||||
break;
|
||||
}
|
||||
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
|
||||
gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
|
||||
} else {
|
||||
if (get_cpu_family() == CPU_OMAP34XX) {
|
||||
timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
|
||||
timings->ctrla = NUMONYX_V_ACTIMA_165;
|
||||
timings->ctrlb = NUMONYX_V_ACTIMB_165;
|
||||
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
|
||||
} else {
|
||||
timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
|
||||
timings->ctrla = NUMONYX_V_ACTIMA_200;
|
||||
timings->ctrlb = NUMONYX_V_ACTIMB_200;
|
||||
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
|
||||
}
|
||||
gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* break into full u-boot on 'c' */
|
||||
if (serial_tstc() && serial_getc() == 'c')
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user