GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/board/k+p/bootscripts/tpcboot.cmd

@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018
+# Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d tpcboot.cmd boot.scr
+#
+
+
+# Input envs (to be set in environment)
+# Mandatory:
+# kernel_file = "fitImage"
+# boardname = "XXXX"  // set automatically in u-boot
+# boardsoc = "imx6q"  // set automatically in u-boot
+#
+# Optional:
+# bootcmd_force = "nfs" "tftp_kernel"
+# If not set - eMMC/SD boot
+
+# Generic setup
+setenv mmcroot "/dev/mmcblk${devnum}p2 rootwait rw"
+setenv displayargs ""
+setenv mmcargs "setenv bootargs console=${console} ${smp} root=${mmcroot} \
+	${displayargs}"
+setenv miscadj "
+if test '${boardsoc}' = 'imx53'; then
+       setenv bootargs '${bootargs} di=${dig_in} key1=${key1}';
+fi;"
+setenv nfsadj "
+if test '${boardsoc}' = 'imx53'; then
+   if test '${boardtype}' = 'hsc'; then
+       setenv bootargs '${bootargs} dsa_core.blacklist=yes';
+   fi;
+fi;"
+setenv boot_fitImage "
+	setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb';
+	setenv itbcfg "\"#\${fdt_conf}\"";
+	print itbcfg;
+	bootm '${loadaddr}${itbcfg}';"
+
+#------------------------------------------------------------
+#
+# Provide default 'bootcmd' command
+#------------------------------------------------------------
+setenv bootcmd "
+if test -e ${devtype} ${devnum}:${distro_bootpart} ${kernel_file}; then
+	echo Found kernel image: ${kernel_file};
+	if load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} \
+	   ${kernel_file}; then
+		run mmcargs;
+		run miscadj;
+		run boot_fitImage;
+	fi;
+fi;"
+
+#------------------------------------------------------------
+#
+# Provide 'boot_tftp_kernel' command
+#------------------------------------------------------------
+setenv download_kernel "dhcp ${loadaddr} ${kernel_file}"
+
+setenv boot_tftp_kernel "
+if run download_kernel; then
+	run mmcargs;
+	run miscadj;
+	run boot_fitImage;
+fi"
+
+#------------------------------------------------------------
+#
+# Provide 'boot_nfs' command
+#------------------------------------------------------------
+setenv nfsargs "setenv bootargs root=/dev/nfs rw nfsroot='${rootpath}',nolock,nfsvers=3"
+setenv addip "setenv bootargs '${bootargs}' ip='${ipaddr}':'${serverip}':'${gatewayip}':'${netmask}':'${hostname}':eth0:on"
+
+setenv boot_nfs "
+if run download_kernel; then
+	run nfsargs;
+	run addip;
+	run nfsadj;
+	setenv bootargs '${bootargs}' console=${console};
+
+	run boot_fitImage;
+fi"
+
+#------------------------------------------------------------
+#
+# Set correct boot flow
+#------------------------------------------------------------
+
+setenv bcmd "
+if test ! -n ${bootcmd_force}; then
+	run bootcmd;
+fi;
+if test ${bootcmd_force} = nfs; then
+	run boot_nfs;
+else if test ${bootcmd_force} = tftp_kernel; then
+	run boot_tftp_kernel;
+     fi;
+fi"
+
+run bcmd

source/bootloader/u-boot-2020.01/board/k+p/kp_imx53/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_KP_IMX53
+
+config SYS_BOARD
+	default "kp_imx53"
+
+config SYS_VENDOR
+	default "k+p"
+
+config SYS_SOC
+	default "mx5"
+
+config SYS_CONFIG_NAME
+	default "kp_imx53"
+
+endif

source/bootloader/u-boot-2020.01/board/k+p/kp_imx53/MAINTAINERS

@@ -0,0 +1,6 @@
+KP_IMX53_HSC BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/k+p/kp_imx53/
+F:	include/configs/kp_imx53.h
+F:	configs/kp_imx53_defconfig

source/bootloader/u-boot-2020.01/board/k+p/kp_imx53/Makefile

@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2018, DENX Software Engineering
+# Lukasz Majewski <lukma@denx.de>
+#
+# SPDX-License-Identifier:    GPL-2.0+
+#
+
+obj-y		+= kp_imx53.o kp_id_rev.o

source/bootloader/u-boot-2020.01/board/k+p/kp_imx53/kp_id_rev.c

@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Based on code developed by:
+ *
+ * Copyright (C) 2012 TQ-Systems GmbH
+ * Daniel Gericke <daniel.gericke@tqs.de>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <i2c.h>
+#include "kp_id_rev.h"
+
+static int eeprom_has_been_read;
+static struct id_eeprom eeprom;
+
+void show_eeprom(void)
+{
+	char safe_string[33];
+	int i;
+	u8 *p;
+
+	puts("Module EEPROM:\n");
+	/* ID */
+	for (i = 0; i <= sizeof(eeprom.id) && 0xff != eeprom.id[i]; ++i)
+		safe_string[i] = eeprom.id[i];
+	safe_string[i] = '\0';
+
+	if (!strncmp(safe_string, "TQM", 3)) {
+		printf("  ID: %s\n", safe_string);
+		env_set("boardtype", safe_string);
+	} else {
+		puts("  unknown hardware variant\n");
+	}
+
+	/* Serial number */
+	for (i = 0; (sizeof(eeprom.serial) >= i) &&
+		    (eeprom.serial[i] >= 0x30) &&
+		    (eeprom.serial[i] <= 0x39); ++i)
+		safe_string[i] = eeprom.serial[i];
+	safe_string[i] = '\0';
+
+	if (strlen(safe_string) == 8) {
+		printf("  SN: %s\n", safe_string);
+		env_set("serial#", safe_string);
+	} else {
+		puts("  unknown serial number\n");
+	}
+
+	/* MAC address  */
+	p = eeprom.mac;
+	if (!is_valid_ethaddr(p)) {
+		printf("  Not valid ETH EEPROM addr!\n");
+		return;
+	}
+
+	printf("  MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+	       p[0], p[1], p[2], p[3], p[4], p[5]);
+
+	eth_env_set_enetaddr("ethaddr", p);
+}
+
+int read_eeprom(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (eeprom_has_been_read)
+		return 0;
+
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+				      CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
+	if (ret) {
+		printf("Cannot find EEPROM !\n");
+		return ret;
+	}
+
+	ret = dm_i2c_read(dev, 0x0, (uchar *)&eeprom, sizeof(eeprom));
+
+	eeprom_has_been_read = (ret == 0) ? 1 : 0;
+	return ret;
+}
+
+int read_board_id(void)
+{
+	unsigned char rev_id = 0x42;
+	char rev_str[32], buf[8];
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(2, 0x22, 1, &dev);
+	if (ret) {
+		printf("Cannot find pcf8574 IO expander !\n");
+		return ret;
+	}
+
+	dm_i2c_read(dev, 0x0, &rev_id, sizeof(rev_id));
+
+	sprintf(rev_str, "%02X", rev_id);
+	if (rev_id & 0x80) {
+		printf("BBoard:4x00 Rev:%s\n", rev_str);
+		env_set("boardtype", "ddc");
+		env_set("fit_config", "imx53_kb_conf");
+	} else {
+		printf("BBoard:40x0 Rev:%s\n", rev_str);
+		env_set("boardtype", "hsc");
+		env_set("fit_config", "imx53_kb_40x0_conf");
+	}
+
+	sprintf(buf, "kp-%s", env_get("boardtype"));
+	env_set("boardname", buf);
+	env_set("boardsoc", "imx53");
+	env_set("kb53_rev", rev_str);
+
+	return 0;
+}

source/bootloader/u-boot-2020.01/board/k+p/kp_imx53/kp_id_rev.h

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Based on code developed by:
+ *
+ * Copyright (C) 2012 TQ-Systems GmbH
+ * Daniel Gericke <daniel.gericke@tqs.de>
+ */
+
+#ifndef __KP_ID_REV_H_
+#define __KP_ID_REV_H_
+
+struct id_eeprom {
+	u8 hrcw_primary[0x20];
+	u8 mac[6];              /* 0x20 ... 0x25 */
+	u8 rsv1[10];
+	u8 serial[8];           /* 0x30 ... 0x37 */
+	u8 rsv2[8];
+	u8 id[0x40];            /* 0x40 ... 0x7f */
+} __packed;
+
+void show_eeprom(void);
+int read_eeprom(void);
+int read_board_id(void);
+#endif /* __KP_ID_REV_H_ */

source/bootloader/u-boot-2020.01/board/k+p/kp_imx53/kp_imx53.c

@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <asm/gpio.h>
+#include <env.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include "kp_id_rev.h"
+
+#define BOOSTER_OFF IMX_GPIO_NR(2, 23)
+#define LCD_BACKLIGHT IMX_GPIO_NR(1, 1)
+#define KEY1 IMX_GPIO_NR(2, 26)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	u32 size;
+
+	size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	gd->ram_size = size;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+static int power_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("mc34708", &dev);
+	if (ret) {
+		printf("%s: mc34708 not found !\n", __func__);
+		return ret;
+	}
+
+	/* Set VDDGP to 1.110V for 800 MHz on SW1 */
+	pmic_clrsetbits(dev, REG_SW_0, SWx_VOLT_MASK_MC34708,
+			SWx_1_110V_MC34708);
+
+	/* Set VCC as 1.30V on SW2 */
+	pmic_clrsetbits(dev, REG_SW_1, SWx_VOLT_MASK_MC34708,
+			SWx_1_300V_MC34708);
+
+	/* Set global reset timer to 4s */
+	pmic_clrsetbits(dev, REG_POWER_CTL2, TIMER_MASK_MC34708,
+			TIMER_4S_MC34708);
+
+	return ret;
+}
+
+static void setup_clocks(void)
+{
+	int ret;
+	u32 ref_clk = MXC_HCLK;
+	/*
+	 * CPU clock set to 800MHz and DDR to 400MHz
+	 */
+	ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to 800MHZ failed\n");
+
+	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
+static void setup_ups(void)
+{
+	gpio_request(BOOSTER_OFF, "BOOSTER_OFF");
+	gpio_direction_output(BOOSTER_OFF, 0);
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+void board_disable_display(void)
+{
+	gpio_request(LCD_BACKLIGHT, "LCD_BACKLIGHT");
+	gpio_direction_output(LCD_BACKLIGHT, 0);
+}
+
+void board_misc_setup(void)
+{
+	gpio_request(KEY1, "KEY1_GPIO");
+	gpio_direction_input(KEY1);
+
+	if (gpio_get_value(KEY1))
+		env_set("key1", "off");
+	else
+		env_set("key1", "on");
+}
+
+int board_late_init(void)
+{
+	int ret = 0;
+
+	board_disable_display();
+	setup_ups();
+
+	if (!power_init())
+		setup_clocks();
+
+	ret = read_eeprom();
+	if (ret)
+		printf("Error %d reading EEPROM content!\n", ret);
+
+	show_eeprom();
+	read_board_id();
+
+	board_misc_setup();
+
+	return ret;
+}

source/bootloader/u-boot-2020.01/board/k+p/kp_imx6q_tpc/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_KP_IMX6Q_TPC
+
+config SYS_BOARD
+	default "kp_imx6q_tpc"
+
+config SYS_VENDOR
+	default "k+p"
+
+config SYS_CONFIG_NAME
+	default "kp_imx6q_tpc"
+
+endif

source/bootloader/u-boot-2020.01/board/k+p/kp_imx6q_tpc/MAINTAINERS

@@ -0,0 +1,6 @@
+KP_IMX6Q_TPC BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/k+p/kp_imx6q_tpc/
+F:	include/configs/kp_imx6q_tpc.h
+F:	configs/kp_imx6q_tpc_defconfig

source/bootloader/u-boot-2020.01/board/k+p/kp_imx6q_tpc/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= kp_imx6q_tpc_spl.o
+else
+obj-y	:= kp_imx6q_tpc.o
+endif

source/bootloader/u-boot-2020.01/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c

@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K+P iMX6Q KP_IMX6Q_TPC board configuration
+ *
+ * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <env.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <led.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec_clock(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* set gpr1[21] to select anatop clock */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK,
+			IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
+}
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8031 output a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+static void setup_usb(void)
+{
+	/*
+	 * Set daisy chain for otg_pin_id on MX6Q.
+	 * For MX6DL, this bit is reserved.
+	 */
+	imx_iomux_set_gpr_register(1, 13, 1, 0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_USB_EHCI_MX6
+	setup_usb();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec_clock();
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Enable eim_slow clocks */
+	setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	env_set("boardname", "kp-tpc");
+	env_set("boardsoc", "imx6q");
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n");
+	return 0;
+}

source/bootloader/u-boot-2020.01/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c

@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K+P iMX6Q KP_IMX6Q_TPC board configuration
+ *
+ * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+/* DDR3 */
+static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdclk_1 = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_reset = 0x00000030,
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = 0x00000030,
+	.dram_sdodt1 = 0x00000030,
+
+	.dram_sdqs0 = 0x00000018,
+	.dram_sdqs1 = 0x00000018,
+	.dram_sdqs2 = 0x00000018,
+	.dram_sdqs3 = 0x00000018,
+	.dram_sdqs4 = 0x00000018,
+	.dram_sdqs5 = 0x00000018,
+	.dram_sdqs6 = 0x00000018,
+	.dram_sdqs7 = 0x00000018,
+
+	.dram_dqm0 = 0x00000018,
+	.dram_dqm1 = 0x00000018,
+	.dram_dqm2 = 0x00000018,
+	.dram_dqm3 = 0x00000018,
+	.dram_dqm4 = 0x00000018,
+	.dram_dqm5 = 0x00000018,
+	.dram_dqm6 = 0x00000018,
+	.dram_dqm7 = 0x00000018,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000018,
+	.grp_b1ds = 0x00000018,
+	.grp_b2ds = 0x00000018,
+	.grp_b3ds = 0x00000018,
+	.grp_b4ds = 0x00000018,
+	.grp_b5ds = 0x00000018,
+	.grp_b6ds = 0x00000018,
+	.grp_b7ds = 0x00000018,
+};
+
+static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001F001F,
+	.p0_mpwldectrl1 = 0x001F001F,
+	.p1_mpwldectrl0 = 0x001F001F,
+	.p1_mpwldectrl1 = 0x001F001F,
+	.p0_mpdgctrl0 = 0x43270338,
+	.p0_mpdgctrl1 = 0x03200314,
+	.p1_mpdgctrl0 = 0x431A032F,
+	.p1_mpdgctrl1 = 0x03200263,
+	.p0_mprddlctl = 0x4B434748,
+	.p1_mprddlctl = 0x4445404C,
+	.p0_mpwrdlctl = 0x38444542,
+	.p1_mpwrdlctl = 0x4935493A,
+};
+
+/* MT41K256M16 (4Gb density) */
+static const struct mx6_ddr3_cfg mt41k256m16 = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+#ifdef CONFIG_MX6_DDRCAL
+static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+	struct mx6_mmdc_calibration calibration = {0};
+
+	mmdc_read_calibration(sysinfo, &calibration);
+
+	debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
+	debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
+	debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
+	debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
+	debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
+	debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
+	debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
+	debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
+	debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
+	debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
+	debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
+	debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
+}
+
+static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+	int ret;
+
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	ret = mmdc_do_write_level_calibration(sysinfo);
+	if (ret) {
+		printf("DDR: Write level calibration error [%d]\n", ret);
+		return;
+	}
+
+	ret = mmdc_do_dqs_calibration(sysinfo);
+	if (ret) {
+		printf("DDR: DQS calibration error [%d]\n", ret);
+		return;
+	}
+
+	spl_dram_print_cal(sysinfo);
+}
+#endif /* CONFIG_MX6_DDRCAL */
+
+static void spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize = 2,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32, /* 32Gb per CS */
+		/* single chip select */
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
+		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
+	};
+
+	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
+
+#ifdef CONFIG_MX6_DDRCAL
+	spl_dram_perform_cal(&sysinfo);
+#endif
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	u32 boot_device = spl_boot_device();
+	u32 reg = imx6_src_get_boot_mode();
+
+	reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
+
+	debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg);
+	if (boot_device == BOOT_DEVICE_MMC1)
+		if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC)
+			boot_device = BOOT_DEVICE_MMC2;
+
+	spl_boot_list[0] = boot_device;
+	/*
+	 * Below boot device is a 'fallback' - it shall always be possible to
+	 * boot from SD card
+	 */
+	spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* Early - pre reloc - driver model setup */
+	spl_early_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+}