GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/board/kosagi/novena/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_KOSAGI_NOVENA
+
+config SYS_BOARD
+	default "novena"
+
+config SYS_VENDOR
+	default "kosagi"
+
+config SYS_CONFIG_NAME
+	default "novena"
+
+endif

source/bootloader/u-boot-2020.01/board/kosagi/novena/MAINTAINERS

@@ -0,0 +1,6 @@
+NOVENA BOARD
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	board/kosagi/novena/
+F:	include/configs/novena.h
+F:	configs/novena_defconfig

source/bootloader/u-boot-2020.01/board/kosagi/novena/Makefile

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014 Marek Vasut <marex@denx.de>
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= novena_spl.o
+else
+obj-y	:= novena.o
+obj-$(CONFIG_VIDEO_IPUV3)	+= video.o
+endif

source/bootloader/u-boot-2020.01/board/kosagi/novena/novena.c

@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Novena board support
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <eeprom.h>
+#include <init.h>
+#include <dm/device-internal.h>
+#include <ahci.h>
+#include <env.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
+#include <dwc_ahsata.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/fb.h>
+#include <linux/input.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <stdio_dev.h>
+#include <video_console.h>
+
+#include "novena.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * GPIO button
+ */
+#ifdef CONFIG_KEYBOARD
+static struct input_config button_input;
+
+static int novena_gpio_button_read_keys(struct input_config *input)
+{
+	int key = KEY_ENTER;
+	if (gpio_get_value(NOVENA_BUTTON_GPIO))
+		return 0;
+	input_send_keycodes(&button_input, &key, 1);
+	return 1;
+}
+
+static int novena_gpio_button_getc(struct stdio_dev *dev)
+{
+	return input_getc(&button_input);
+}
+
+static int novena_gpio_button_tstc(struct stdio_dev *dev)
+{
+	return input_tstc(&button_input);
+}
+
+static int novena_gpio_button_init(struct stdio_dev *dev)
+{
+	gpio_direction_input(NOVENA_BUTTON_GPIO);
+	input_set_delays(&button_input, 250, 250);
+	return 0;
+}
+
+int drv_keyboard_init(void)
+{
+	int error;
+	struct stdio_dev dev = {
+		.name	= "button",
+		.flags	= DEV_FLAGS_INPUT,
+		.start	= novena_gpio_button_init,
+		.getc	= novena_gpio_button_getc,
+		.tstc	= novena_gpio_button_tstc,
+	};
+
+	gpio_request(NOVENA_BUTTON_GPIO, "button");
+
+	error = input_init(&button_input, 0);
+	if (error) {
+		debug("%s: Cannot set up input\n", __func__);
+		return -1;
+	}
+	input_add_tables(&button_input, false);
+	button_input.read_keys = novena_gpio_button_read_keys;
+
+	error = input_stdio_register(&dev);
+	if (error)
+		return error;
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display_clock();
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+	struct udevice *con;
+	char buf[DISPLAY_OPTIONS_BANNER_LENGTH];
+	int ret;
+
+	setup_display_lvds();
+
+	ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con);
+	if (ret)
+		return ret;
+
+	display_options_get_banner(false, buf, sizeof(buf));
+	vidconsole_position_cursor(con, 0, 0);
+	vidconsole_put_string(con, buf);
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Novena 4x\n");
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	struct pmic *p;
+	u32 reg;
+	int ret;
+
+	power_pfuze100_init(1);
+	p = pmic_get("PFUZE100");
+	if (!p)
+		return -EINVAL;
+
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	/* Set SWBST to 5.0V and enable (for USB) */
+	pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
+	reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+	reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
+	pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+
+	return 0;
+}
+
+/* EEPROM configuration data */
+struct novena_eeprom_data {
+	uint8_t		signature[6];
+	uint8_t		version;
+	uint8_t		reserved;
+	uint32_t	serial;
+	uint8_t		mac[6];
+	uint16_t	features;
+};
+
+int misc_init_r(void)
+{
+	struct novena_eeprom_data data;
+	uchar *datap = (uchar *)&data;
+	const char *signature = "Novena";
+	int ret;
+
+	/* If 'ethaddr' is already set, do nothing. */
+	if (env_get("ethaddr"))
+		return 0;
+
+	/* EEPROM is at bus 2. */
+	ret = i2c_set_bus_num(2);
+	if (ret) {
+		puts("Cannot select EEPROM I2C bus.\n");
+		return 0;
+	}
+
+	/* EEPROM is at address 0x56. */
+	ret = eeprom_read(0x56, 0, datap, sizeof(data));
+	if (ret) {
+		puts("Cannot read I2C EEPROM.\n");
+		return 0;
+	}
+
+	/* Check EEPROM signature. */
+	if (memcmp(data.signature, signature, 6)) {
+		puts("Invalid I2C EEPROM signature.\n");
+		return 0;
+	}
+
+	/* Set ethernet address from EEPROM. */
+	eth_env_set_enetaddr("ethaddr", data.mac);
+
+	return ret;
+}

source/bootloader/u-boot-2020.01/board/kosagi/novena/novena.h

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Novena board support
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __BOARD_KOSAGI_NOVENA_NOVENA_H__
+#define __BOARD_KOSAGI_NOVENA_NOVENA_H__
+
+#define NOVENA_AUDIO_PWRON		IMX_GPIO_NR(5, 17)
+#define NOVENA_BACKLIGHT_PWM_GPIO	IMX_GPIO_NR(4, 29)
+#define NOVENA_BACKLIGHT_PWR_GPIO	IMX_GPIO_NR(4, 15)
+#define NOVENA_BUTTON_GPIO		IMX_GPIO_NR(4, 14)
+#define NOVENA_FPGA_RESET_N_GPIO	IMX_GPIO_NR(5, 7)
+#define NOVENA_HDMI_GHOST_HPD		IMX_GPIO_NR(5, 4)
+#define NOVENA_ITE6251_PWR_GPIO		IMX_GPIO_NR(5, 28)
+#define NOVENA_PCIE_DISABLE_GPIO	IMX_GPIO_NR(2, 16)
+#define NOVENA_PCIE_POWER_ON_GPIO	IMX_GPIO_NR(7, 12)
+#define NOVENA_PCIE_RESET_GPIO		IMX_GPIO_NR(3, 29)
+#define NOVENA_PCIE_WAKE_UP_GPIO	IMX_GPIO_NR(3, 22)
+#define NOVENA_SD_CD			IMX_GPIO_NR(1, 4)
+#define NOVENA_SD_WP			IMX_GPIO_NR(1, 2)
+
+#define NOVENA_IT6251_I2C_BUS	2
+#define NOVENA_IT6251_CHIPADDR	0x5c
+#define NOVENA_IT6251_LVDSADDR	0x5e
+
+void setup_display_clock(void);
+void setup_display_lvds(void);
+
+#endif	/* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */

source/bootloader/u-boot-2020.01/board/kosagi/novena/novena_spl.c

@@ -0,0 +1,597 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Novena SPL
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/crm_regs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <spl.h>
+
+#include <asm/arch/mx6-ddr.h>
+
+#include "novena.h"
+
+#define UART_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define ENET_PHY_CFG_PAD_CTRL					\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_22K_UP | PAD_CTL_HYS)
+
+#define RGMII_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL						\
+	(PAD_CTL_HYS |						\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_240ohm  | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define BUTTON_PAD_CTRL						\
+	(PAD_CTL_PKE | PAD_CTL_PUE |				\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/*
+ * Audio
+ */
+static iomux_v3_cfg_t audio_pads[] = {
+	/* AUD_PWRON */
+	MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_audio(void)
+{
+	imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads));
+	gpio_direction_output(NOVENA_AUDIO_PWRON, 1);
+}
+
+/*
+ * ENET
+ */
+static iomux_v3_cfg_t enet_pads1[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	/* pin 35, PHY_AD2 */
+	MX6_PAD_RGMII_RXC__GPIO6_IO30	| MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+	/* pin 32, MODE0 */
+	MX6_PAD_RGMII_RD0__GPIO6_IO25	| MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+	/* pin 31, MODE1 */
+	MX6_PAD_RGMII_RD1__GPIO6_IO27	| MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+	/* pin 28, MODE2 */
+	MX6_PAD_RGMII_RD2__GPIO6_IO28	| MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+	/* pin 27, MODE3 */
+	MX6_PAD_RGMII_RD3__GPIO6_IO29	| MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+	/* pin 33, CLK125_EN */
+	MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+
+	/* pin 42 PHY nRST */
+	MX6_PAD_EIM_D23__GPIO3_IO23		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t enet_pads2[] = {
+	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(RGMII_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+
+	/* Assert Ethernet PHY nRST */
+	gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+
+	/*
+	 * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
+	 * de-assertion. The intention is to use weak signal drivers (pull-ups)
+	 * to prevent the conflict between PHY pins becoming outputs after
+	 * reset and imx6 still driving the pins. The issue is described in PHY
+	 * datasheet, p.14
+	 */
+	gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
+	gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
+	gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
+	gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
+	gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
+	gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
+
+	/* Following reset timing (p.53, fig.8 from the PHY datasheet) */
+	mdelay(10);
+
+	/* De-assert Ethernet PHY nRST */
+	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+
+	/* PHY is now configured, connect FEC to the pads */
+	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+
+	/*
+	 * PHY datasheet recommends on p.53 to wait at least 100us after reset
+	 * before using MII, so we enforce the delay here
+	 */
+	udelay(100);
+}
+
+/*
+ * FPGA
+ */
+static iomux_v3_cfg_t fpga_pads[] = {
+	/* FPGA_RESET_N */
+	MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_fpga(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads));
+	gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0);
+}
+
+/*
+ * GPIO Button
+ */
+static iomux_v3_cfg_t button_pads[] = {
+	/* Debug */
+	MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_buttons(void)
+{
+	imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads));
+}
+
+/*
+ * I2C
+ */
+/*
+ * I2C1:
+ *  0x1d ... MMA7455L
+ *  0x30 ... SO-DIMM temp sensor
+ *  0x44 ... STMPE610
+ *  0x50 ... SO-DIMM ID
+ */
+struct i2c_pads_info i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode	= MX6_PAD_EIM_D21__I2C1_SCL | PC,
+		.gpio_mode	= MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+		.gp		= IMX_GPIO_NR(3, 21)
+	},
+	.sda = {
+		.i2c_mode	= MX6_PAD_EIM_D28__I2C1_SDA | PC,
+		.gpio_mode	= MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+		.gp		= IMX_GPIO_NR(3, 28)
+	}
+};
+
+/*
+ * I2C2:
+ *  0x08 ... PMIC
+ *  0x3a ... HDMI DCC
+ *  0x50 ... HDMI DCC
+ */
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode	= MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode	= MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.gp		= IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode	= MX6_PAD_EIM_D16__I2C2_SDA | PC,
+		.gpio_mode	= MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+		.gp		= IMX_GPIO_NR(3, 16)
+	}
+};
+
+/*
+ * I2C3:
+ *  0x11 ... ES8283
+ *  0x50 ... LCD EDID
+ *  0x56 ... EEPROM
+ */
+static struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode	= MX6_PAD_EIM_D17__I2C3_SCL | PC,
+		.gpio_mode	= MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+		.gp		= IMX_GPIO_NR(3, 17)
+	},
+	.sda = {
+		.i2c_mode	= MX6_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode	= MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+		.gp		= IMX_GPIO_NR(3, 18)
+	}
+};
+
+static void novena_spl_setup_iomux_i2c(void)
+{
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+}
+
+/*
+ * PCI express
+ */
+#ifdef CONFIG_CMD_PCI
+static iomux_v3_cfg_t pcie_pads[] = {
+	/* "Reset" pin */
+	MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* "Power on" pin */
+	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* "Wake up" pin (input) */
+	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* "Disable endpoint" (rfkill) pin */
+	MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_pcie(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+
+	/* Ensure PCIe is powered down */
+	gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0);
+
+	/* Put the card into reset */
+	gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0);
+
+	/* Input signal to wake system from mPCIe card */
+	gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO);
+
+	/* Drive RFKILL high, to ensure the radio is turned on */
+	gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1);
+}
+#else
+static inline void novena_spl_setup_iomux_pcie(void) {}
+#endif
+
+/*
+ * SDHC
+ */
+static iomux_v3_cfg_t usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
+	MX6_PAD_GPIO_4__GPIO1_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_sdhc(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+	/* Big SD write-protect and card-detect */
+	gpio_direction_input(IMX_GPIO_NR(1, 2));
+	gpio_direction_input(IMX_GPIO_NR(1, 4));
+}
+
+/*
+ * SPI
+ */
+#ifdef CONFIG_MXC_SPI
+static iomux_v3_cfg_t ecspi3_pads[] = {
+	/* SS1 */
+	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_spi(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
+	/* De-assert the nCS */
+	gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1);
+	gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1);
+	gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1);
+}
+#else
+static void novena_spl_setup_iomux_spi(void) {}
+#endif
+
+/*
+ * UART
+ */
+static iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+
+};
+
+static void novena_spl_setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+/*
+ * Video
+ */
+#ifdef CONFIG_VIDEO
+static iomux_v3_cfg_t hdmi_pads[] = {
+	/* "Ghost HPD" pin */
+	MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* LCD_PWR_CTL */
+	MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* LCD_BL_ON */
+	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* GPIO_PWM1 */
+	MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_video(void)
+{
+	imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
+	gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
+}
+#else
+static inline void novena_spl_setup_iomux_video(void) {}
+#endif
+
+/*
+ * SPL boots from uSDHC card
+ */
+#ifdef CONFIG_FSL_ESDHC_IMX
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	USDHC3_BASE_ADDR, 0, 4
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* There is no CD for a microSD card, assume always present. */
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif
+
+/* Configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0		= 0x00020038,
+	.dram_sdclk_1		= 0x00020038,
+	.dram_cas		= 0x00000038,
+	.dram_ras		= 0x00000038,
+	.dram_reset		= 0x00000038,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0		= 0x00000038,
+	.dram_sdcke1		= 0x00000038,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2		= 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0		= 0x00000038,
+	.dram_sdodt1		= 0x00000038,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0		= 0x00000038,
+	.dram_sdqs1		= 0x00000038,
+	.dram_sdqs2		= 0x00000038,
+	.dram_sdqs3		= 0x00000038,
+	.dram_sdqs4		= 0x00000038,
+	.dram_sdqs5		= 0x00000038,
+	.dram_sdqs6		= 0x00000038,
+	.dram_sdqs7		= 0x00000038,
+
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0		= 0x00000038,
+	.dram_dqm1		= 0x00000038,
+	.dram_dqm2		= 0x00000038,
+	.dram_dqm3		= 0x00000038,
+	.dram_dqm4		= 0x00000038,
+	.dram_dqm5		= 0x00000038,
+	.dram_dqm6		= 0x00000038,
+	.dram_dqm7		= 0x00000038,
+};
+
+/* Configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs novena_grp_ioregs = {
+	/* DDR3 */
+	.grp_ddr_type		= 0x000c0000,
+	.grp_ddrmode_ctl	= 0x00020000,
+	/* Disable DDR pullups */
+	.grp_ddrpke		= 0x00000000,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds		= 0x00000038,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds		= 0x00000038,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode		= 0x00020000,
+	.grp_b0ds		= 0x00000038,
+	.grp_b1ds		= 0x00000038,
+	.grp_b2ds		= 0x00000038,
+	.grp_b3ds		= 0x00000038,
+	.grp_b4ds		= 0x00000038,
+	.grp_b5ds		= 0x00000038,
+	.grp_b6ds		= 0x00000038,
+	.grp_b7ds		= 0x00000038,
+};
+
+static struct mx6_mmdc_calibration novena_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0		= 0x00420048,
+	.p0_mpwldectrl1		= 0x006f0059,
+	.p1_mpwldectrl0		= 0x005a0104,
+	.p1_mpwldectrl1		= 0x01070113,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0		= 0x437c040b,
+	.p0_mpdgctrl1		= 0x0413040e,
+	.p1_mpdgctrl0		= 0x444f0446,
+	.p1_mpdgctrl1		= 0x044d0422,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl		= 0x4c424249,
+	.p1_mprddlctl		= 0x4e48414f,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl		= 0x42414641,
+	.p1_mpwrdlctl		= 0x46374b43,
+};
+
+static struct mx6_ddr_sysinfo novena_ddr_info = {
+	/* Width of data bus: 0=16, 1=32, 2=64 */
+	.dsize		= 2,
+	/* Config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,	/* 32Gb per CS */
+	/* Single chip select */
+	.ncs		= 1,
+	.cs1_mirror	= 0,
+	.rtt_wr		= 0,	/* RTT_Wr = RZQ/4 */
+	.rtt_nom	= 1,	/* RTT_Nom = RZQ/2 */
+	.walat		= 0,	/* Write additional latency */
+	.ralat		= 5,	/* Read additional latency */
+	.mif3_mode	= 3,	/* Command prediction working mode */
+	.bi_on		= 1,	/* Bank interleaving enabled */
+	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.refsel = 1,	/* Refresh cycles at 32KHz */
+	.refr = 7,	/* 8 refresh commands per refresh cycle */
+};
+
+static struct mx6_ddr3_cfg elpida_4gib_1600 = {
+	.mem_speed	= 1600,
+	.density	= 4,
+	.width		= 64,
+	.banks		= 8,
+	.rowaddr	= 16,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1375,
+	.trcmin		= 4875,
+	.trasmin	= 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0xFFFFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+	board_postclk_init();
+#endif
+#ifdef CONFIG_FSL_ESDHC_IMX
+	get_clocks();
+#endif
+
+	/* Setup IOMUX and configure basics. */
+	novena_spl_setup_iomux_audio();
+	novena_spl_setup_iomux_buttons();
+	novena_spl_setup_iomux_enet();
+	novena_spl_setup_iomux_fpga();
+	novena_spl_setup_iomux_i2c();
+	novena_spl_setup_iomux_pcie();
+	novena_spl_setup_iomux_sdhc();
+	novena_spl_setup_iomux_spi();
+	novena_spl_setup_iomux_uart();
+	novena_spl_setup_iomux_video();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* Start the DDR DRAM */
+	mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
+	mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
+
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	mmdc_do_write_level_calibration(&novena_ddr_info);
+	mmdc_do_dqs_calibration(&novena_ddr_info);
+}

source/bootloader/u-boot-2020.01/board/kosagi/novena/video.c

@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Novena video output support
+ *
+ * IT6251 code based on code Copyright (C) 2014 Sean Cross
+ * from https://github.com/xobs/novena-linux.git commit
+ * 3d85836ee1377d445531928361809612aa0a18db
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/fb.h>
+#include <linux/input.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+
+#include "novena.h"
+
+#define IT6251_VENDOR_ID_LOW				0x00
+#define IT6251_VENDOR_ID_HIGH				0x01
+#define IT6251_DEVICE_ID_LOW				0x02
+#define IT6251_DEVICE_ID_HIGH				0x03
+#define IT6251_SYSTEM_STATUS				0x0d
+#define IT6251_SYSTEM_STATUS_RINTSTATUS			(1 << 0)
+#define IT6251_SYSTEM_STATUS_RHPDSTATUS			(1 << 1)
+#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE		(1 << 2)
+#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK		(1 << 3)
+#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK		(1 << 4)
+#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK		(1 << 5)
+#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK		(1 << 6)
+#define IT6251_REF_STATE				0x0e
+#define IT6251_REF_STATE_MAIN_LINK_DISABLED		(1 << 0)
+#define IT6251_REF_STATE_AUX_CHANNEL_READ		(1 << 1)
+#define IT6251_REF_STATE_CR_PATTERN			(1 << 2)
+#define IT6251_REF_STATE_EQ_PATTERN			(1 << 3)
+#define IT6251_REF_STATE_NORMAL_OPERATION		(1 << 4)
+#define IT6251_REF_STATE_MUTED				(1 << 5)
+
+#define IT6251_REG_PCLK_CNT_LOW				0x57
+#define IT6251_REG_PCLK_CNT_HIGH			0x58
+
+#define IT6521_RETRY_MAX				20
+
+static int it6251_is_stable(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+	const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
+	int status;
+	int clkcnt;
+	int rpclkcnt;
+	int refstate;
+
+	rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
+		   ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
+	debug("RPCLKCnt: %d\n", rpclkcnt);
+
+	status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
+	debug("System status: 0x%02x\n", status);
+
+	clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
+		 ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
+		  0x0f00);
+	debug("Clock: 0x%02x\n", clkcnt);
+
+	refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
+	debug("Ref Link State: 0x%02x\n", refstate);
+
+	if ((refstate & 0x1f) != 0)
+		return 0;
+
+	/* If video is muted, that's a failure */
+	if (refstate & IT6251_REF_STATE_MUTED)
+		return 0;
+
+	if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
+		return 0;
+
+	return 1;
+}
+
+static int it6251_ready(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+
+	/* Test if the IT6251 came out of reset by reading ID regs. */
+	if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
+		return 0;
+	if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
+		return 0;
+	if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
+		return 0;
+	if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
+		return 0;
+
+	return 1;
+}
+
+static void it6251_program_regs(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+	const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
+
+	i2c_reg_write(caddr, 0x05, 0x00);
+	mdelay(1);
+
+	/* set LVDSRX address, and enable */
+	i2c_reg_write(caddr, 0xfd, 0xbc);
+	i2c_reg_write(caddr, 0xfe, 0x01);
+
+	/*
+	 * LVDSRX
+	 */
+	/* This write always fails, because the chip goes into reset */
+	/* reset LVDSRX */
+	i2c_reg_write(laddr, 0x05, 0xff);
+	i2c_reg_write(laddr, 0x05, 0x00);
+
+	/* reset LVDSRX PLL */
+	i2c_reg_write(laddr, 0x3b, 0x42);
+	i2c_reg_write(laddr, 0x3b, 0x43);
+
+	/* something with SSC PLL */
+	i2c_reg_write(laddr, 0x3c, 0x08);
+	/* don't swap links, but writing reserved registers */
+	i2c_reg_write(laddr, 0x0b, 0x88);
+
+	/* JEIDA, 8-bit depth  0x11, orig 0x42 */
+	i2c_reg_write(laddr, 0x2c, 0x01);
+	/* "reserved" */
+	i2c_reg_write(laddr, 0x32, 0x04);
+	/* "reserved" */
+	i2c_reg_write(laddr, 0x35, 0xe0);
+	/* "reserved" + clock delay */
+	i2c_reg_write(laddr, 0x2b, 0x24);
+
+	/* reset LVDSRX pix clock */
+	i2c_reg_write(laddr, 0x05, 0x02);
+	i2c_reg_write(laddr, 0x05, 0x00);
+
+	/*
+	 * DPTX
+	 */
+	/* set for two lane mode, normal op, no swapping, no downspread */
+	i2c_reg_write(caddr, 0x16, 0x02);
+
+	/* some AUX channel EDID magic */
+	i2c_reg_write(caddr, 0x23, 0x40);
+
+	/* power down lanes 3-0 */
+	i2c_reg_write(caddr, 0x5c, 0xf3);
+
+	/* enable DP scrambling, change EQ CR phase */
+	i2c_reg_write(caddr, 0x5f, 0x06);
+
+	/* color mode RGB, pclk/2 */
+	i2c_reg_write(caddr, 0x60, 0x02);
+	/* dual pixel input mode, no EO swap, no RGB swap */
+	i2c_reg_write(caddr, 0x61, 0x04);
+	/* M444B24 video format */
+	i2c_reg_write(caddr, 0x62, 0x01);
+
+	/* vesa range / not interlace / vsync high / hsync high */
+	i2c_reg_write(caddr, 0xa0, 0x0F);
+
+	/* hpd event timer set to 1.6-ish ms */
+	i2c_reg_write(caddr, 0xc9, 0xf5);
+
+	/* more reserved magic */
+	i2c_reg_write(caddr, 0xca, 0x4d);
+	i2c_reg_write(caddr, 0xcb, 0x37);
+
+	/* enhanced framing mode, auto video fifo reset, video mute disable */
+	i2c_reg_write(caddr, 0xd3, 0x03);
+
+	/* "vidstmp" and some reserved stuff */
+	i2c_reg_write(caddr, 0xd4, 0x45);
+
+	/* queue number -- reserved */
+	i2c_reg_write(caddr, 0xe7, 0xa0);
+	/* info frame packets  and reserved */
+	i2c_reg_write(caddr, 0xe8, 0x33);
+	/* more AVI stuff */
+	i2c_reg_write(caddr, 0xec, 0x00);
+
+	/* select PC master reg for aux channel? */
+	i2c_reg_write(caddr, 0x23, 0x42);
+
+	/* send PC request commands */
+	i2c_reg_write(caddr, 0x24, 0x00);
+	i2c_reg_write(caddr, 0x25, 0x00);
+	i2c_reg_write(caddr, 0x26, 0x00);
+
+	/* native aux read */
+	i2c_reg_write(caddr, 0x2b, 0x00);
+	/* back to internal */
+	i2c_reg_write(caddr, 0x23, 0x40);
+
+	/* voltage swing level 3 */
+	i2c_reg_write(caddr, 0x19, 0xff);
+	/* pre-emphasis level 3 */
+	i2c_reg_write(caddr, 0x1a, 0xff);
+
+	/* start link training */
+	i2c_reg_write(caddr, 0x17, 0x01);
+}
+
+static int it6251_init(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+	int reg;
+	int tries, retries = 0;
+
+	for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
+		/* Program the chip. */
+		it6251_program_regs();
+
+		/* Wait for video stable. */
+		for (tries = 0; tries < 100; tries++) {
+			reg = i2c_reg_read(caddr, 0x17);
+			/* Test Link CFG, STS, LCS read done. */
+			if ((reg & 0xe0) != 0xe0) {
+				/* Not yet, wait a bit more. */
+				mdelay(2);
+				continue;
+			}
+
+			/* Test if the video input is stable. */
+			if (it6251_is_stable())
+				return 0;
+		}
+		/*
+		 * If we couldn't stabilize, requeue and try again,
+		 * because it means that the LVDS channel isn't
+		 * stable yet.
+		 */
+		printf("Display didn't stabilize.\n");
+		printf("This may be because the LVDS port is still in powersave mode.\n");
+		mdelay(50);
+	}
+
+	return -EINVAL;
+}
+
+static void enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static int lvds_enabled;
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	if (lvds_enabled)
+		return;
+
+	/* ITE IT6251 power enable. */
+	gpio_request(NOVENA_ITE6251_PWR_GPIO, "ite6251-power");
+	gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
+	mdelay(10);
+	gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
+	mdelay(20);
+	lvds_enabled = 1;
+}
+
+static int detect_lvds(struct display_info_t const *dev)
+{
+	int ret, loops = 250;
+
+	enable_lvds(dev);
+
+	ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+	if (ret) {
+		puts("Cannot select IT6251 I2C bus.\n");
+		return 0;
+	}
+
+	/* Wait up-to ~250 mS for the LVDS to come up. */
+	while (--loops) {
+		ret = it6251_ready();
+		if (ret)
+			return ret;
+
+		mdelay(1);
+	}
+
+	return 0;
+}
+
+struct display_info_t const displays[] = {
+	{
+		/* HDMI Output */
+		.bus	= -1,
+		.addr	= 0,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= detect_hdmi,
+		.enable	= enable_hdmi,
+		.mode	= {
+			.name		= "HDMI",
+			.refresh	= 60,
+			.xres		= 1024,
+			.yres		= 768,
+			.pixclock	= 15384,
+			.left_margin	= 220,
+			.right_margin	= 40,
+			.upper_margin	= 21,
+			.lower_margin	= 7,
+			.hsync_len	= 60,
+			.vsync_len	= 10,
+			.sync		= FB_SYNC_EXT,
+			.vmode		= FB_VMODE_NONINTERLACED
+		},
+	}, {
+		/* LVDS Output: N133HSE-EA1 Rev. C1 */
+		.bus	= -1,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= detect_lvds,
+		.enable	= enable_lvds,
+		.mode	= {
+			.name		= "Chimei-FHD",
+			.refresh	= 60,
+			.xres		= 1920,
+			.yres		= 1080,
+			.pixclock	= 15384,
+			.left_margin	= 148,
+			.right_margin	= 88,
+			.upper_margin	= 36,
+			.lower_margin	= 4,
+			.hsync_len	= 44,
+			.vsync_len	= 5,
+			.sync		= FB_SYNC_HOR_HIGH_ACT |
+					  FB_SYNC_VERT_HIGH_ACT |
+					  FB_SYNC_EXT,
+			.vmode		= FB_VMODE_NONINTERLACED,
+		},
+	},
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+static void enable_vpll(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int timeout = 100000;
+
+	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+			BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+			BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
+			BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+	clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+	if (timeout < 0)
+		printf("Warning: video pll lock timeout!\n");
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_BYPASS,
+			BM_ANADIG_PLL_VIDEO_ENABLE);
+}
+
+void setup_display_clock(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	enable_ipu_clock();
+	enable_vpll();
+	imx_setup_hdmi();
+
+	/* Turn on IPU LDB DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	/* Switch LDB DI0 to PLL5 (Video PLL) */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
+			(0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+
+	/* LDB clock div by 3.5 */
+	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+	/* DI0 clock derived from ldb_di0_clk */
+	clrsetbits_le32(&mxc_ccm->chsccdr,
+			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+			(CHSCCDR_CLK_SEL_LDB_DI0 <<
+			 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
+			);
+
+	/* Enable both LVDS channels, both connected to DI0. */
+	writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
+	       IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
+	       IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
+	       IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
+	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+	       IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
+	       IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
+	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+	       &iomux->gpr[2]);
+
+	clrsetbits_le32(&iomux->gpr[3],
+			IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+			IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
+			(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+			 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+			(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+			 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+			);
+}
+
+void setup_display_lvds(void)
+{
+	int ret;
+
+	ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+	if (ret) {
+		puts("Cannot select LVDS-to-eDP I2C bus.\n");
+		return;
+	}
+
+	/* The IT6251 should be ready now, if it's not, it's not connected. */
+	ret = it6251_ready();
+	if (!ret)
+		return;
+
+	/* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
+	ret = it6251_init();
+	if (!ret) {
+		gpio_request(NOVENA_BACKLIGHT_PWR_GPIO, "backlight-power");
+		gpio_request(NOVENA_BACKLIGHT_PWM_GPIO, "backlight-pwm");
+		/* Backlight power enable. */
+		gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
+		/* PWM backlight pin, always on for full brightness. */
+		gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
+	}
+}