GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,18 @@
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if TARGET_DISPLAY5
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config SYS_CPU
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default "armv7"
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config SYS_BOARD
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default "display5"
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config SYS_VENDOR
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default "liebherr"
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config SYS_SOC
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default "mx6"
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config SYS_CONFIG_NAME
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default "display5"
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endif
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@@ -0,0 +1,7 @@
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DISPLAY5 BOARD
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M: Lukasz Majewski <lukma@denx.de>
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S: Maintained
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F: board/liebherr/display5/
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F: include/configs/display5.h
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F: configs/display5_defconfig
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F: configs/display5_factory_defconfig
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@@ -0,0 +1,11 @@
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#
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# Copyright (C) 2017, DENX Software Engineering
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# Lukasz Majewski <lukma@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD
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obj-y = spl.o
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else
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obj-y := display5.o
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endif
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@@ -0,0 +1,34 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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#ifndef __DISPL5_COMMON_H_
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#define __DISPL5_COMMON_H_
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | \
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PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#endif /* __DISPL5_COMMON_H_ */
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@@ -0,0 +1,247 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/sys_proto.h>
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#include <env.h>
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#include <errno.h>
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#include <asm/gpio.h>
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#include <malloc.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <dm.h>
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#include <dm/platform_data/serial_mxc.h>
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#include <dm/platdata.h>
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#include "common.h"
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DECLARE_GLOBAL_DATA_PTR;
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static bool hw_ids_valid;
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static bool sw_ids_valid;
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static u32 cpu_id;
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static u32 unit_id;
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const char *gpio_table_sw_names[] = {
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"GPIO2_4", "GPIO2_5", "GPIO2_6", "GPIO2_7"
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};
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const char *gpio_table_sw_ids_names[] = {
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"sw0", "sw1", "sw2", "sw3"
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};
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const char *gpio_table_hw_names[] = {
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"GPIO6_7", "GPIO6_9", "GPIO6_10", "GPIO6_11",
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"GPIO4_7", "GPIO4_11", "GPIO4_13", "GPIO4_15"
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};
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const char *gpio_table_hw_ids_names[] = {
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"hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
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};
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static int get_board_id(const char **pin_names, const char **ids_names,
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int size, bool *valid, u32 *id)
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{
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struct gpio_desc desc;
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int i, ret, val;
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*valid = false;
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for (i = 0; i < size; i++) {
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memset(&desc, 0, sizeof(desc));
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ret = dm_gpio_lookup_name(pin_names[i], &desc);
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if (ret) {
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printf("Can't lookup request SWx gpios\n");
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return ret;
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}
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ret = dm_gpio_request(&desc, ids_names[i]);
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if (ret) {
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printf("Can't lookup request SWx gpios\n");
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return ret;
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}
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dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
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val = dm_gpio_get_value(&desc);
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if (val < 0) {
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printf("Can't get SW%d ID\n", i);
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*id = 0;
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return val;
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}
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*id |= val << i;
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}
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*valid = true;
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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iomux_v3_cfg_t const misc_pads[] = {
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/* Prod ID GPIO pins */
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MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* HW revision GPIO pins */
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MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* XTALOSC */
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MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* Emergency recovery pin */
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MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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/*
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* Do not overwrite the console
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* Always use serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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fdt_fixup_ethernet(blob);
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return 0;
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}
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#endif
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int board_phy_config(struct phy_device *phydev)
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{
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/* display5 due to PCB routing can only work with 100 Mbps */
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phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
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ADVERTISED_1000baseX_Full |
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SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full);
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if (phydev->drv->config)
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return phydev->drv->config(phydev);
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return 0;
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}
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int board_init(void)
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{
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struct gpio_desc phy_int_gbe, spi2_wp;
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int ret;
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debug("board init\n");
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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/* Setup misc (application specific) stuff */
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SETUP_IOMUX_PADS(misc_pads);
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get_board_id(gpio_table_sw_names, &gpio_table_sw_ids_names[0],
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ARRAY_SIZE(gpio_table_sw_names), &sw_ids_valid, &unit_id);
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debug("SWx unit_id 0x%x\n", unit_id);
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get_board_id(gpio_table_hw_names, &gpio_table_hw_ids_names[0],
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ARRAY_SIZE(gpio_table_hw_names), &hw_ids_valid, &cpu_id);
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debug("HWx cpu_id 0x%x\n", cpu_id);
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if (hw_ids_valid && sw_ids_valid)
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printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
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udelay(25);
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/* Setup low level FEC (ETH) */
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ret = dm_gpio_lookup_name("GPIO1_28", &phy_int_gbe);
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if (ret) {
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printf("Cannot get GPIO1_28\n");
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} else {
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ret = dm_gpio_request(&phy_int_gbe, "INT_GBE");
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if (!ret)
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dm_gpio_set_dir_flags(&phy_int_gbe, GPIOD_IS_IN);
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}
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iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
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enable_fec_anatop_clock(0, ENET_125MHZ);
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/* Setup #WP for SPI-NOR memory */
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ret = dm_gpio_lookup_name("GPIO7_0", &spi2_wp);
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if (ret) {
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printf("Cannot get GPIO7_0\n");
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} else {
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ret = dm_gpio_request(&spi2_wp, "spi2_#wp");
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if (!ret)
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dm_gpio_set_dir_flags(&spi2_wp, GPIOD_IS_OUT |
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GPIOD_IS_OUT_ACTIVE);
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}
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* eMMC, USDHC-4, 8-bit bus width */
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/* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */
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{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
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{"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
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{NULL, 0},
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};
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static void setup_boot_modes(void)
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{
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add_board_boot_modes(board_boot_modes);
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}
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#else
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static inline void setup_boot_modes(void) {}
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#endif
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int misc_init_r(void)
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{
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struct gpio_desc em_pad;
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int ret;
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setup_boot_modes();
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ret = dm_gpio_lookup_name("GPIO3_29", &em_pad);
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if (ret) {
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printf("Can't find emergency PAD gpio\n");
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return ret;
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}
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ret = dm_gpio_request(&em_pad, "Emergency_PAD");
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if (ret) {
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printf("Can't request emergency PAD gpio\n");
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return ret;
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}
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dm_gpio_set_dir_flags(&em_pad, GPIOD_IS_IN);
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return 0;
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}
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@@ -0,0 +1,396 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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#include <common.h>
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#include <env.h>
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#include <serial.h>
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#include <spl.h>
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#include <linux/libfdt.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include "asm/arch/crm_regs.h"
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/imx-regs.h>
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#include "asm/arch/iomux.h"
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/gpio.h>
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#include <fsl_esdhc_imx.h>
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#include <netdev.h>
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#include <bootcount.h>
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#include <watchdog.h>
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#include "common.h"
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DECLARE_GLOBAL_DATA_PTR;
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static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_sdclk_0 = 0x00000030,
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.dram_sdclk_1 = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_reset = 0x00000030,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x00000030,
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.dram_sdodt1 = 0x00000030,
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.dram_sdqs0 = 0x00000030,
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.dram_sdqs1 = 0x00000030,
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.dram_sdqs2 = 0x00000030,
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.dram_sdqs3 = 0x00000030,
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.dram_sdqs4 = 0x00000030,
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.dram_sdqs5 = 0x00000030,
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.dram_sdqs6 = 0x00000030,
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.dram_sdqs7 = 0x00000030,
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.dram_dqm0 = 0x00000030,
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.dram_dqm1 = 0x00000030,
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.dram_dqm2 = 0x00000030,
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.dram_dqm3 = 0x00000030,
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.dram_dqm4 = 0x00000030,
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.dram_dqm5 = 0x00000030,
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.dram_dqm6 = 0x00000030,
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.dram_dqm7 = 0x00000030,
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};
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static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_b2ds = 0x00000030,
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.grp_b3ds = 0x00000030,
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.grp_b4ds = 0x00000030,
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.grp_b5ds = 0x00000030,
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.grp_b6ds = 0x00000030,
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.grp_b7ds = 0x00000030,
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};
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/* 4x128Mx16.cfg */
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static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
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.p0_mpwldectrl0 = 0x002D0028,
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.p0_mpwldectrl1 = 0x0032002D,
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.p1_mpwldectrl0 = 0x00210036,
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.p1_mpwldectrl1 = 0x0019002E,
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.p0_mpdgctrl0 = 0x4349035C,
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.p0_mpdgctrl1 = 0x0348033D,
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.p1_mpdgctrl0 = 0x43550362,
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.p1_mpdgctrl1 = 0x03520316,
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.p0_mprddlctl = 0x41393940,
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.p1_mprddlctl = 0x3F3A3C47,
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.p0_mpwrdlctl = 0x413A423A,
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.p1_mpwrdlctl = 0x4042483E,
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};
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/* MT41K128M16JT-125 (2Gb density) */
|
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static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
|
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.mem_speed = 1600,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
|
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.trcmin = 4875,
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.trasmin = 3500,
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||||
};
|
||||
|
||||
iomux_v3_cfg_t const uart_console_pads[] = {
|
||||
/* UART5 */
|
||||
MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
void displ5_set_iomux_uart_spl(void)
|
||||
{
|
||||
SETUP_IOMUX_PADS(uart_console_pads);
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t const misc_pads_spl[] = {
|
||||
/* Emergency recovery pin */
|
||||
MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
void displ5_set_iomux_misc_spl(void)
|
||||
{
|
||||
SETUP_IOMUX_PADS(misc_pads_spl);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
iomux_v3_cfg_t const ecspi2_pads[] = {
|
||||
/* SPI2, NOR Flash nWP, CS0 */
|
||||
MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
|
||||
{
|
||||
if (bus != 1 || cs != 0)
|
||||
return -EINVAL;
|
||||
|
||||
return IMX_GPIO_NR(5, 29);
|
||||
}
|
||||
|
||||
void displ5_set_iomux_ecspi_spl(void)
|
||||
{
|
||||
SETUP_IOMUX_PADS(ecspi2_pads);
|
||||
}
|
||||
|
||||
#else
|
||||
void displ5_set_iomux_ecspi_spl(void) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
||||
iomux_v3_cfg_t const usdhc4_pads[] = {
|
||||
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
void displ5_set_iomux_usdhc_spl(void)
|
||||
{
|
||||
SETUP_IOMUX_PADS(usdhc4_pads);
|
||||
}
|
||||
|
||||
#else
|
||||
void displ5_set_iomux_usdhc_spl(void) {}
|
||||
#endif
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
writel(0x00C03F3F, &ccm->CCGR0);
|
||||
writel(0x0030FC3F, &ccm->CCGR1);
|
||||
writel(0x0FFFCFC0, &ccm->CCGR2);
|
||||
writel(0x3FF00000, &ccm->CCGR3);
|
||||
writel(0x00FFF300, &ccm->CCGR4);
|
||||
writel(0x0F0000C3, &ccm->CCGR5);
|
||||
writel(0x000003FF, &ccm->CCGR6);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MX6_DDRCAL
|
||||
static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
|
||||
{
|
||||
struct mx6_mmdc_calibration calibration = {0};
|
||||
|
||||
mmdc_read_calibration(sysinfo, &calibration);
|
||||
|
||||
debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
|
||||
debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
|
||||
debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
|
||||
debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
|
||||
debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
|
||||
debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
|
||||
debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
|
||||
debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
|
||||
debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
|
||||
debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
|
||||
debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
|
||||
debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
|
||||
}
|
||||
|
||||
static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Perform DDR DRAM calibration */
|
||||
udelay(100);
|
||||
ret = mmdc_do_write_level_calibration(sysinfo);
|
||||
if (ret) {
|
||||
printf("DDR: Write level calibration error [%d]\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
ret = mmdc_do_dqs_calibration(sysinfo);
|
||||
if (ret) {
|
||||
printf("DDR: DQS calibration error [%d]\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
spl_dram_print_cal(sysinfo);
|
||||
}
|
||||
#endif /* CONFIG_MX6_DDRCAL */
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
struct mx6_ddr_sysinfo sysinfo = {
|
||||
/* width of data bus:0=16,1=32,2=64 */
|
||||
.dsize = 2,
|
||||
/* config for full 4GB range so that get_mem_size() works */
|
||||
.cs_density = 32, /* 32Gb per CS */
|
||||
/* single chip select */
|
||||
.ncs = 1,
|
||||
.cs1_mirror = 0,
|
||||
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
|
||||
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
|
||||
.walat = 1, /* Write additional latency */
|
||||
.ralat = 5, /* Read additional latency */
|
||||
.mif3_mode = 3, /* Command prediction working mode */
|
||||
.bi_on = 1, /* Bank interleaving enabled */
|
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
||||
.pd_fast_exit = 1, /* enable precharge power-down fast exit */
|
||||
.ddr_type = DDR_TYPE_DDR3,
|
||||
.refsel = 1, /* Refresh cycles at 32KHz */
|
||||
.refr = 7, /* 8 refresh commands per refresh cycle */
|
||||
};
|
||||
|
||||
mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
||||
mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
|
||||
|
||||
#ifdef CONFIG_MX6_DDRCAL
|
||||
spl_dram_perform_cal(&sysinfo);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_SPI_SUPPORT
|
||||
static void displ5_init_ecspi(void)
|
||||
{
|
||||
displ5_set_iomux_ecspi_spl();
|
||||
enable_spi_clk(1, 1);
|
||||
}
|
||||
#else
|
||||
static inline void displ5_init_ecspi(void) { }
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_MMC_SUPPORT
|
||||
static struct fsl_esdhc_cfg usdhc_cfg = {
|
||||
.esdhc_base = USDHC4_BASE_ADDR,
|
||||
.max_bus_width = 8,
|
||||
};
|
||||
|
||||
int board_mmc_init(bd_t *bd)
|
||||
{
|
||||
displ5_set_iomux_usdhc_spl();
|
||||
|
||||
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
|
||||
|
||||
return fsl_esdhc_initialize(bd, &usdhc_cfg);
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
ccgr_init();
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
gpr_init();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
displ5_set_iomux_uart_spl();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
displ5_init_ecspi();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
displ5_set_iomux_misc_spl();
|
||||
|
||||
/* Initialize and reset WDT in SPL */
|
||||
hw_watchdog_init();
|
||||
WATCHDOG_RESET();
|
||||
|
||||
/* load/boot image from boot device */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
#define EM_PAD IMX_GPIO_NR(3, 29)
|
||||
int board_check_emergency_pad(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = gpio_direction_input(EM_PAD);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return !gpio_get_value(EM_PAD);
|
||||
}
|
||||
|
||||
void board_boot_order(u32 *spl_boot_list)
|
||||
{
|
||||
/* Default boot sequence SPI -> MMC */
|
||||
spl_boot_list[0] = spl_boot_device();
|
||||
spl_boot_list[1] = BOOT_DEVICE_MMC1;
|
||||
spl_boot_list[2] = BOOT_DEVICE_UART;
|
||||
spl_boot_list[3] = BOOT_DEVICE_NONE;
|
||||
|
||||
/*
|
||||
* In case of emergency PAD pressed, we always boot
|
||||
* to proper u-boot and perform recovery tasks there.
|
||||
*/
|
||||
if (board_check_emergency_pad())
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_SPL_ENV_SUPPORT
|
||||
/* 'fastboot' */
|
||||
const char *s;
|
||||
|
||||
if (env_init() || env_load())
|
||||
return;
|
||||
|
||||
s = env_get("BOOT_FROM");
|
||||
if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
|
||||
spl_boot_list[0] = BOOT_DEVICE_MMC1;
|
||||
spl_boot_list[1] = spl_boot_device();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr) {}
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* break into full u-boot on 'c' */
|
||||
if (serial_tstc() && serial_getc() == 'c')
|
||||
return 1;
|
||||
|
||||
#ifdef CONFIG_SPL_ENV_SUPPORT
|
||||
if (env_get_yesno("boot_os") != 1)
|
||||
return 1;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user