GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_MX6LOGICPD
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config SYS_BOARD
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default "imx6"
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config SYS_VENDOR
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default "logicpd"
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config SYS_CONFIG_NAME
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default "imx6_logic"
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endif
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@@ -0,0 +1,10 @@
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MX6LOGICPD BOARD
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M: Adam Ford <aford173@gmail.com>
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S: Maintained
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F: board/logicpd/imx6/
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F: include/configs/imx6_logic.h
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F: configs/imx6q_logic_defconfig
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F: arch/arm/dts/imx6-logicpd-baseboard.dtsi
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F: arch/arm/dts/imx6-logicpd-som.dtsi
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F: arch/arm/dts/imx6q-logicpd.dts
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F: arch/arm/dts/imx6q-logicpd-u-boot.dtsi
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@@ -0,0 +1,10 @@
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#
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# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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#
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# (C) Copyright 2011 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := imx6logic.o
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@@ -0,0 +1,83 @@
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U-Boot for LogicPD i.MX6 Development Kit
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----------------------------------------
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This file contains information for the port of U-Boot to the Logic PD Development kit.
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Logic PD has an i.MX6 System On Module (SOM) and a correspondong development
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board. SOM has a built-in microSD socket, DDR and NAND flash. The development kit has
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an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
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On the intial release, the SOM came with either an i.MX6D or i.MX6Q.
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For more details about Logic PD i.MX6 Development kit, visit:
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https://www.logicpd.com/
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Building U-Boot for Logic PD Development Kit
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--------------------------------------------
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To build U-Boot for the Dual and Quad variants:
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make imx6q_logic_defconfig
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make u-boot.imx ARCH=arm CROSS_COMPILE=arm-linux-
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Flashing U-Boot into the SD card
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--------------------------------
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U-Boot is now building with SPL enabled which means there are two files to
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load into the SD card. Make sure the card is formatted with at least two
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partitions with the first partition being FAT32. First copy u-boot-dtb.img
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to the first partition then burn SPL to the SD card with dd.
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The SPL portion is programmed into a certain location for use by the internal
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bootROM and it cannot be changed. The following instructions assume the SD
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card is located as /dev/sdb.
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cp u-boot-dtb.img /dev/media/logic/boot
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sudo dd if=SPL of=/dev/sdb bs=1k seek=1 oflag=sync status=none && sync
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Flashing U-Boot into NAND
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-------------------------
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Once in Linux with MTD support for the NAND on /dev/mtd0, program U-Boot with the following:
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with:
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kobs-ng init -v -x u-boot-dtb.imx
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Using Falcon Mode
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-----------------
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With Falcon Mode enabled, U-Boot can be bypassed by having SPL directly load
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the kernel. The device tree, Kernel and boot args must first be configured,
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and stored to a file on the micro SD card called 'args'
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The kernel uImage is built with LOAD_ADDR=0x12000000 and the device tree is
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assummed to be imx6q-logicpd.dtb.
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By default the mmcroot is set to the baseboard.
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# Establish bootargs
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run mmcargs
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# Load Linux Kernel uImage
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fatload mmc 1 $loadaddr uImage
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# Load Device Tree
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run loadfdt
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# Setup the blob that will get passed to the kernel
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spl export fdt ${loadaddr} - ${fdt_addr_r}
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# Note the starting and ending address of the updated device tree.
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# for this example:
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# Loading Device Tree to 1ffdf000, end 1fff038b ... OK
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# Notice that 0x1fff038b - 1ffdf000 = 0x1138b
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# now Add 1, so the length is 0x1138c.
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fatwrite mmc 1 0x1ffdf000 args 0x1138c
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# Reset the board and it will bypass U-Boot and SPL will directly boot
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# the uImage
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To interrupt the boot sequence and force U-Boot to load, hold the 'c' button
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while starting.
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Additional Support Documentation can be found at:
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https://support.logicpd.com/
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@@ -0,0 +1,323 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Logic PD, Inc.
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*
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* Author: Adam Ford <aford173@gmail.com>
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*
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* Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
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* and updates by Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <init.h>
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#include <miiphy.h>
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#include <input.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <serial.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/sizes.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/iomux-v3.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const nand_pads[] = {
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MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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};
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static void setup_nand_pins(void)
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{
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imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
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}
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static int ar8031_phy_fixup(struct phy_device *phydev)
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{
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unsigned short val;
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/* To enable AR8031 output a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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val &= 0xffe3;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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ar8031_phy_fixup(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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int board_early_init_f(void)
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{
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setup_nand_pins();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int board_late_init(void)
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{
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env_set("board_name", "imx6logic");
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if (is_mx6dq()) {
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env_set("board_rev", "MX6DQ");
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if (!env_get("fdt_file"))
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env_set("fdt_file", "imx6q-logicpd.dtb");
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}
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6q-ddr.h>
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#include <spl.h>
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#include <linux/libfdt.h>
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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return 0;
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}
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#endif
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void board_boot_order(u32 *spl_boot_list)
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{
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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unsigned int reg = readl(&psrc->sbmr1) >> 11;
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u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
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unsigned int bmode = readl(&src_base->sbmr2);
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/* If bmode is serial or USB phy is active, return serial */
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if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
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spl_boot_list[0] = BOOT_DEVICE_BOARD;
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return;
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}
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switch (boot_mode >> IMX6_BMODE_SHIFT) {
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case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
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spl_boot_list[0] = BOOT_DEVICE_NAND;
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break;
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case IMX6_BMODE_SD:
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case IMX6_BMODE_ESD:
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case IMX6_BMODE_MMC:
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case IMX6_BMODE_EMMC:
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/*
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* Upon reading BOOT_CFG register the following map is done:
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* Bit 11 and 12 of BOOT_CFG register can determine the current
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* mmc port
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* 0x1 SD1-SOM
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* 0x2 SD2-Baseboard
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*/
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reg &= 0x3; /* Only care about bottom 2 bits */
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switch (reg) {
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case 0:
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spl_boot_list[0] = BOOT_DEVICE_MMC1;
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break;
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case 1:
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spl_boot_list[0] = BOOT_DEVICE_MMC2;
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break;
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}
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break;
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default:
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/* By default use USB downloader */
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spl_boot_list[0] = BOOT_DEVICE_BOARD;
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break;
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}
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/* As a last resort, use serial downloader */
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spl_boot_list[1] = BOOT_DEVICE_BOARD;
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}
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0xFFFFF300, &ccm->CCGR4);
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writel(0x0F0000F3, &ccm->CCGR5);
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writel(0x00000FFF, &ccm->CCGR6);
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}
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static int mx6q_dcd_table[] = {
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MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
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MX6_IOM_GRP_DDRPKE, 0x00000000,
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MX6_IOM_DRAM_SDCLK_0, 0x00000030,
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MX6_IOM_DRAM_SDCLK_1, 0x00000030,
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MX6_IOM_DRAM_CAS, 0x00000030,
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MX6_IOM_DRAM_RAS, 0x00000030,
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MX6_IOM_GRP_ADDDS, 0x00000030,
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MX6_IOM_DRAM_RESET, 0x00000030,
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MX6_IOM_DRAM_SDBA2, 0x00000000,
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MX6_IOM_DRAM_SDODT0, 0x00000030,
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MX6_IOM_DRAM_SDODT1, 0x00000030,
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MX6_IOM_GRP_CTLDS, 0x00000030,
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MX6_IOM_DDRMODE_CTL, 0x00020000,
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MX6_IOM_DRAM_SDQS0, 0x00000030,
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MX6_IOM_DRAM_SDQS1, 0x00000030,
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MX6_IOM_DRAM_SDQS2, 0x00000030,
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MX6_IOM_DRAM_SDQS3, 0x00000030,
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MX6_IOM_GRP_DDRMODE, 0x00020000,
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MX6_IOM_GRP_B0DS, 0x00000030,
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MX6_IOM_GRP_B1DS, 0x00000030,
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MX6_IOM_GRP_B2DS, 0x00000030,
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MX6_IOM_GRP_B3DS, 0x00000030,
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MX6_IOM_DRAM_DQM0, 0x00000030,
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MX6_IOM_DRAM_DQM1, 0x00000030,
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MX6_IOM_DRAM_DQM2, 0x00000030,
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MX6_IOM_DRAM_DQM3, 0x00000030,
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MX6_MMDC_P0_MDSCR, 0x00008000,
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MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
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MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
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MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
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MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
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MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
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MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
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||||
MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
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MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
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MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
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||||
MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
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MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
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MX6_MMDC_P0_MPMUR0, 0x00000800,
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MX6_MMDC_P0_MDPDC, 0x00020036,
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MX6_MMDC_P0_MDOTC, 0x09444040,
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MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
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MX6_MMDC_P0_MDCFG1, 0xFF328F64,
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MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
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MX6_MMDC_P0_MDMISC, 0x00011740,
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MX6_MMDC_P0_MDSCR, 0x00008000,
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MX6_MMDC_P0_MDRWD, 0x000026D2,
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MX6_MMDC_P0_MDOR, 0x00BE1023,
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MX6_MMDC_P0_MDASP, 0x00000047,
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MX6_MMDC_P0_MDCTL, 0x85190000,
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MX6_MMDC_P0_MDSCR, 0x00888032,
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MX6_MMDC_P0_MDSCR, 0x00008033,
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MX6_MMDC_P0_MDSCR, 0x00008031,
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MX6_MMDC_P0_MDSCR, 0x19408030,
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MX6_MMDC_P0_MDSCR, 0x04008040,
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MX6_MMDC_P0_MDREF, 0x00007800,
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MX6_MMDC_P0_MPODTCTRL, 0x00000007,
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MX6_MMDC_P0_MDPDC, 0x00025576,
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MX6_MMDC_P0_MAPSR, 0x00011006,
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||||
MX6_MMDC_P0_MDSCR, 0x00000000,
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
|
||||
MX6_IOMUXC_GPR4, 0xF00000CF,
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
MX6_IOMUXC_GPR6, 0x007F007F,
|
||||
MX6_IOMUXC_GPR7, 0x007F007F,
|
||||
};
|
||||
|
||||
static void ddr_init(int *table, int size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < size / 2 ; i++)
|
||||
writel(table[2 * i + 1], table[2 * i]);
|
||||
}
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
if (is_mx6dq())
|
||||
ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
ccgr_init();
|
||||
gpr_init();
|
||||
|
||||
/* iomux and setup of uart and NAND pins */
|
||||
board_early_init_f();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* Enable device tree and early DM support*/
|
||||
spl_early_init();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user