GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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CRS305-1G-4S BOARD
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M: Luka Kovacic <me@lukakovacic.xyz>
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S: Maintained
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F: board/mikrotik/crs305-1g-4s/
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F: include/configs/crs305-1g-4s.h
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F: configs/crs305-1g-4s_defconfig
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F: arch/arm/dts/armada-xp-crs305-1g-4s.dts
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2015 Stefan Roese <sr@denx.de>
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obj-y := crs305-1g-4s.o
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extra-y := kwbimage.cfg
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quiet_cmd_sed = SED $@
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cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)
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SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
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$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
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include/config/auto.conf
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$(call if_changed,sed)
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MikroTik CRS305-1G-4S+IN
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========================
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CRS305-1G-4S+IN is a 4x SFP+ switch with a Gigabit Ethernet port for management.
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Specifications:
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- Marvell Prestera 98DX3236 switch with an integrated ARMv7 CPU
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- 512 MB DDR3 RAM
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- UART @ 115200bps
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- 4x SFP+
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- Gigabit Ethernet (AR8033)
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- 16 MB SPI flash (Winbond 25Q128JVSM)
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Currently supported hardware:
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- UART boot (using kwboot) and console
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- SPI boot, environment and load kernel
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Planned:
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- Gigabit Ethernet support
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Getting binary.0
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================
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binary.0 (DDR3 init phase) can be retrieved/extracted from the integrated bootloader on the SPI flash.
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Then binary.0 can be replaced with the extracted blob.
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--------
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WARNING:
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--------
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This file should contain the bin_hdr generated by the original Marvell
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U-Boot implementation. As this is currently not included in this
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U-Boot version, we have added this placeholder, so that the U-Boot
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image can be generated without errors.
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If you have a known to be working bin_hdr for your board, then you
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just need to replace this text file here with the binary header
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and recompile U-Boot.
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/gpio.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* These values and defines are taken from the Marvell U-Boot version
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* "u-boot-2013.01-2016_T1.0.eng_drop_v6"
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*/
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#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) \
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| BIT(6) | BIT(12) | BIT(13) \
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| BIT(16) | BIT(17) | BIT(20) \
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| BIT(29) | BIT(30)))
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#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
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#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) \
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| BIT(6) | BIT(12) | BIT(13) \
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| BIT(16) | BIT(17) | BIT(20) \
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| BIT(29) | BIT(30))
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#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
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#define DB_DX_AC3_GPP_POL_LOW 0x0
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#define DB_DX_AC3_GPP_POL_MID 0x0
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(0x00142222, MVEBU_MPP_BASE + 0x00);
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writel(0x11122000, MVEBU_MPP_BASE + 0x04);
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writel(0x44444004, MVEBU_MPP_BASE + 0x08);
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writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
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writel(0x00000001, MVEBU_MPP_BASE + 0x10);
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/*
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* MVEBU_GPIO0_BASE is the User LED
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* MVEBU_GPIO1_BASE is the Reset Button (currently not used)
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*/
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/* Set GPP Out value */
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writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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/* writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); */
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/* Set GPP Polarity */
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writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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/* writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); */
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/* Set GPP Out Enable */
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writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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/* writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); */
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: " CONFIG_SYS_BOARD "\n");
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return 0;
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}
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@@ -0,0 +1,12 @@
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#
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# Copyright (C) 2014 Stefan Roese <sr@denx.de>
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#
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# Armada XP uses version 1 image format
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VERSION 1
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# Boot Media configurations
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BOOT_FROM spi
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# Binary Header (bin_hdr) with DDR3 training code
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BINARY board/mikrotik/crs305-1g-4s/binary.0 0000005b 00000068
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