GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_BEAVER
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config SYS_BOARD
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default "beaver"
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config SYS_VENDOR
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default "nvidia"
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config SYS_CONFIG_NAME
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default "beaver"
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endif
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@@ -0,0 +1,7 @@
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BEAVER BOARD
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M: Tom Warren <twarren@nvidia.com>
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M: Stephen Warren <swarren@nvidia.com>
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S: Maintained
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F: board/nvidia/beaver/
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F: include/configs/beaver.h
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F: configs/beaver_defconfig
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@@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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obj-y = ../cardhu/cardhu.o
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@@ -0,0 +1,12 @@
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if TARGET_CARDHU
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config SYS_BOARD
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default "cardhu"
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config SYS_VENDOR
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default "nvidia"
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config SYS_CONFIG_NAME
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default "cardhu"
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endif
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@@ -0,0 +1,6 @@
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CARDHU BOARD
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M: Tom Warren <twarren@nvidia.com>
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S: Maintained
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F: board/nvidia/cardhu/
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F: include/configs/cardhu.h
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F: configs/cardhu_defconfig
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@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2010-2012
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# NVIDIA Corporation <www.nvidia.com>
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obj-y := cardhu.o
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@@ -0,0 +1,130 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010-2013
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include "pinmux-config-cardhu.h"
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#include <i2c.h>
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#define PMU_I2C_ADDRESS 0x2D
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#define MAX_I2C_RETRY 3
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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pinmux_config_pingrp_table(tegra3_pinmux_common,
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ARRAY_SIZE(tegra3_pinmux_common));
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pinmux_config_pingrp_table(unused_pins_lowpower,
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ARRAY_SIZE(unused_pins_lowpower));
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/* Initialize any non-default pad configs (APB_MISC_GP regs) */
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pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
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}
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#if defined(CONFIG_MMC_SDHCI_TEGRA)
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/*
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* Do I2C/PMU writes to bring up SD card bus power
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*
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*/
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void board_sdmmc_voltage_init(void)
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{
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struct udevice *dev;
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uchar reg, data_buffer[1];
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int ret;
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int i;
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ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
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if (ret) {
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debug("%s: Cannot find PMIC I2C chip\n", __func__);
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return;
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}
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/* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */
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data_buffer[0] = 0x65;
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reg = 0x32;
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for (i = 0; i < MAX_I2C_RETRY; ++i) {
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if (dm_i2c_write(dev, reg, data_buffer, 1))
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udelay(100);
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}
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/* TPS659110: GPIO7_REG = PDEN, output a 1 to EN_3V3_SYS */
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data_buffer[0] = 0x09;
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reg = 0x67;
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for (i = 0; i < MAX_I2C_RETRY; ++i) {
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if (dm_i2c_write(dev, reg, data_buffer, 1))
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udelay(100);
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}
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}
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/*
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* Routine: pin_mux_mmc
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* Description: setup the MMC muxes, power rails, etc.
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*/
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void pin_mux_mmc(void)
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{
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/*
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* NOTE: We don't do mmc-specific pin muxes here.
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* They were done globally in pinmux_init().
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*/
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/* Bring up the SDIO1 power rail */
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board_sdmmc_voltage_init();
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}
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#endif /* MMC */
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#ifdef CONFIG_PCI_TEGRA
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int tegra_pcie_board_init(void)
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{
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struct udevice *dev;
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u8 addr, data[1];
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int err;
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err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
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if (err) {
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debug("failed to find PMU bus\n");
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return err;
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}
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/* TPS659110: LDO1_REG = 1.05V, ACTIVE */
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data[0] = 0x15;
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addr = 0x30;
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err = dm_i2c_write(dev, addr, data, 1);
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if (err) {
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debug("failed to set VDD supply\n");
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return err;
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}
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/* GPIO: PEX = 3.3V */
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err = gpio_request(TEGRA_GPIO(L, 7), "PEX");
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if (err < 0)
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return err;
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gpio_direction_output(TEGRA_GPIO(L, 7), 1);
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/* TPS659110: LDO2_REG = 1.05V, ACTIVE */
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data[0] = 0x15;
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addr = 0x31;
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err = dm_i2c_write(dev, addr, data, 1);
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if (err) {
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debug("failed to set AVDD supply\n");
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return err;
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}
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return 0;
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}
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#endif /* PCI */
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@@ -0,0 +1,335 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef _PINMUX_CONFIG_CARDHU_H_
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#define _PINMUX_CONFIG_CARDHU_H_
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#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
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{ \
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.pingrp = PMUX_PINGRP_##_pingrp, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_DEFAULT, \
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.od = PMUX_PIN_OD_DEFAULT, \
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.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
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}
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#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
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{ \
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.pingrp = PMUX_PINGRP_##_pingrp, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_##_lock, \
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.od = PMUX_PIN_OD_##_od, \
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.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
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}
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#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
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{ \
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.pingrp = PMUX_PINGRP_##_pingrp, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_##_lock, \
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.od = PMUX_PIN_OD_DEFAULT, \
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.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
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}
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#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
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{ \
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.drvgrp = PMUX_DRVGRP_##_drvgrp, \
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.slwf = _slwf, \
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.slwr = _slwr, \
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.drvup = _drvup, \
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.drvdn = _drvdn, \
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.lpmd = PMUX_LPMD_##_lpmd, \
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.schmt = PMUX_SCHMT_##_schmt, \
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.hsm = PMUX_HSM_##_hsm, \
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}
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static struct pmux_pingrp_config tegra3_pinmux_common[] = {
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/* SDMMC1 pinmux */
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DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
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/* SDMMC3 pinmux */
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DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT),
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/* SDMMC4 pinmux */
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LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
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/* I2C1 pinmux */
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I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* I2C2 pinmux */
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I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* I2C3 pinmux */
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I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* I2C4 pinmux */
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I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* Power I2C pinmux */
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I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
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||||
DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
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||||
DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
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||||
DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
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||||
DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
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||||
DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
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||||
DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
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||||
DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
|
||||
DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
|
||||
DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
|
||||
DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* KBC keys */
|
||||
DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* GPIOs */
|
||||
/* SDMMC1 CD gpio */
|
||||
DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
|
||||
/* SDMMC1 WP gpio */
|
||||
LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* Touch panel GPIO */
|
||||
/* Touch IRQ */
|
||||
DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
|
||||
|
||||
/* Touch RESET */
|
||||
DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* Power rails GPIO */
|
||||
DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
|
||||
|
||||
LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
};
|
||||
|
||||
static struct pmux_pingrp_config unused_pins_lowpower[] = {
|
||||
DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
};
|
||||
|
||||
static struct pmux_drvgrp_config cardhu_padctrl[] = {
|
||||
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
|
||||
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
|
||||
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
|
||||
};
|
||||
#endif /* _PINMUX_CONFIG_CARDHU_H_ */
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_DALMORE
|
||||
|
||||
config SYS_BOARD
|
||||
default "dalmore"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "dalmore"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
DALMORE BOARD
|
||||
M: Tom Warren <twarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/dalmore/
|
||||
F: include/configs/dalmore.h
|
||||
F: configs/dalmore_defconfig
|
||||
@@ -0,0 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
|
||||
obj-y := dalmore.o
|
||||
@@ -0,0 +1,100 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/gp_padctrl.h>
|
||||
#include "pinmux-config-dalmore.h"
|
||||
#include <i2c.h>
|
||||
|
||||
#define BAT_I2C_ADDRESS 0x48 /* TPS65090 charger */
|
||||
#define PMU_I2C_ADDRESS 0x58 /* TPS65913 PMU */
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_config_pingrp_table(tegra114_pinmux_set_nontristate,
|
||||
ARRAY_SIZE(tegra114_pinmux_set_nontristate));
|
||||
|
||||
pinmux_config_pingrp_table(tegra114_pinmux_common,
|
||||
ARRAY_SIZE(tegra114_pinmux_common));
|
||||
|
||||
pinmux_config_pingrp_table(unused_pins_lowpower,
|
||||
ARRAY_SIZE(unused_pins_lowpower));
|
||||
|
||||
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
|
||||
pinmux_config_drvgrp_table(dalmore_padctrl,
|
||||
ARRAY_SIZE(dalmore_padctrl));
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MMC_SDHCI_TEGRA)
|
||||
/*
|
||||
* Do I2C/PMU writes to bring up SD card bus power
|
||||
*
|
||||
*/
|
||||
void board_sdmmc_voltage_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
uchar reg, data_buffer[1];
|
||||
int ret;
|
||||
|
||||
ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
|
||||
if (ret) {
|
||||
debug("%s: Cannot find PMIC I2C chip\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/* TPS65913: LDO9_VOLTAGE = 3.3V */
|
||||
data_buffer[0] = 0x31;
|
||||
reg = 0x61;
|
||||
|
||||
ret = dm_i2c_write(dev, reg, data_buffer, 1);
|
||||
if (ret)
|
||||
printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
|
||||
__func__, reg, data_buffer[0], ret);
|
||||
|
||||
/* TPS65913: LDO9_CTRL = Active */
|
||||
data_buffer[0] = 0x01;
|
||||
reg = 0x60;
|
||||
|
||||
ret = dm_i2c_write(dev, reg, data_buffer, 1);
|
||||
if (ret)
|
||||
printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
|
||||
__func__, reg, data_buffer[0], ret);
|
||||
|
||||
/* TPS65090: FET6_CTRL = enable output auto discharge, enable FET6 */
|
||||
data_buffer[0] = 0x03;
|
||||
reg = 0x14;
|
||||
|
||||
ret = i2c_get_chip_for_busnum(0, BAT_I2C_ADDRESS, 1, &dev);
|
||||
if (ret) {
|
||||
debug("%s: Cannot find charger I2C chip\n", __func__);
|
||||
return;
|
||||
}
|
||||
ret = dm_i2c_write(dev, reg, data_buffer, 1);
|
||||
if (ret)
|
||||
printf("%s: BAT i2c_write %02X<-%02X returned %d\n",
|
||||
__func__, reg, data_buffer[0], ret);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: pin_mux_mmc
|
||||
* Description: setup the MMC muxes, power rails, etc.
|
||||
*/
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
/*
|
||||
* NOTE: We don't do mmc-specific pin muxes here.
|
||||
* They were done globally in pinmux_init().
|
||||
*/
|
||||
|
||||
/* Bring up the SDIO3 power rail */
|
||||
board_sdmmc_voltage_init();
|
||||
}
|
||||
#endif /* MMC */
|
||||
@@ -0,0 +1,359 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_DALMORE_H_
|
||||
#define _PINMUX_CONFIG_DALMORE_H_
|
||||
|
||||
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
|
||||
}
|
||||
|
||||
#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define USB_PINMUX CEC_PINMUX
|
||||
|
||||
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static struct pmux_pingrp_config tegra114_pinmux_common[] = {
|
||||
/* EXTPERIPH1 pinmux */
|
||||
DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* I2S0 pinmux */
|
||||
DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* I2S1 pinmux */
|
||||
DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* I2S3 pinmux */
|
||||
DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* CLDVFS pinmux */
|
||||
DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* ULPI pinmux */
|
||||
DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* I2C3 pinmux */
|
||||
I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
|
||||
/* VI pinmux */
|
||||
VI_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
|
||||
/* VI_ALT1 pinmux */
|
||||
VI_PINMUX(PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
|
||||
/* VGP4 pinmux */
|
||||
VI_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
|
||||
/* I2C2 pinmux */
|
||||
I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
|
||||
/* UARTD pinmux */
|
||||
DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* SPI4 pinmux */
|
||||
DEFAULT_PINMUX(GMI_AD5_PG5, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6_PG6, SPI4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7_PG7, SPI4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS6_N_PI3, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N_PI0, SPI4, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* PWM1 pinmux */
|
||||
DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* SOC pinmux */
|
||||
DEFAULT_PINMUX(GMI_CS1_N_PJ2, SOC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N_PI1, SOC, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* EXTPERIPH2 pinmux */
|
||||
DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* SDMMC1 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC3 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC4 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT),
|
||||
|
||||
/* BLINK pinmux */
|
||||
DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* KBC pinmux */
|
||||
DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
|
||||
|
||||
/*Audio Codec*/
|
||||
DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT),
|
||||
|
||||
/* UARTA pinmux */
|
||||
DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* I2CPWR pinmux (I2C5) */
|
||||
I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
|
||||
/* SYSCLK pinmux */
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* RTCK pinmux */
|
||||
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* CLK pinmux */
|
||||
DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* PWRON pinmux */
|
||||
DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* CPU pinmux */
|
||||
DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* PMI pinmux */
|
||||
DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* RESET_OUT_N pinmux */
|
||||
DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* EXTPERIPH3 pinmux */
|
||||
DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* I2C1 pinmux */
|
||||
I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
|
||||
/* UARTB pinmux */
|
||||
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* IRDA pinmux */
|
||||
DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* UARTC pinmux */
|
||||
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* OWR pinmux */
|
||||
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* CEC pinmux */
|
||||
CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
|
||||
|
||||
/* I2C4 pinmux */
|
||||
DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
|
||||
DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
|
||||
|
||||
/* USB pinmux */
|
||||
USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
|
||||
|
||||
/* nct */
|
||||
DEFAULT_PINMUX(GPIO_X6_AUD_PX6, SPI6, UP, TRISTATE, INPUT),
|
||||
};
|
||||
|
||||
static struct pmux_pingrp_config unused_pins_lowpower[] = {
|
||||
DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(USB_VBUS_EN1_PN5, RSVD3, DOWN, TRISTATE, OUTPUT),
|
||||
};
|
||||
|
||||
/* Initially setting all used GPIO's to non-TRISTATE */
|
||||
static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = {
|
||||
DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X6_AUD_PX6, RSVD3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X1_AUD_PX1, RSVD3, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PBB3, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB5, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB6, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB7, RSVD3, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PCC1, RSVD3, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PCC2, RSVD3, DOWN, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD10_PH2, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11_PH3, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD12_PH4, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13_PH5, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK_PK1, GMI, DOWN, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS2_N_PK3, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N_PK4, GMI, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS_P_PJ3, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_IORDY_PI5, GMI, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(SDMMC1_WP_N_PV3, SPI4, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3_PR3, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SPDIF_IN_PK6, USB, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT),
|
||||
};
|
||||
|
||||
static struct pmux_drvgrp_config dalmore_padctrl[] = {
|
||||
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
|
||||
DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
|
||||
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
|
||||
};
|
||||
#endif /* PINMUX_CONFIG_COMMON_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_E2220_1170
|
||||
|
||||
config SYS_BOARD
|
||||
default "e2220-1170"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "e2220-1170"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
E2220-1170 BOARD
|
||||
M: Tom Warren <twarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/e2220-1170/
|
||||
F: include/configs/e2220-1170.h
|
||||
F: configs/e2220-1170_defconfig
|
||||
@@ -0,0 +1,8 @@
|
||||
#
|
||||
# (C) Copyright 2013-2015
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += e2220-1170.o
|
||||
@@ -0,0 +1,50 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013-2015
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include "../p2571/max77620_init.h"
|
||||
#include "pinmux-config-e2220-1170.h"
|
||||
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
uchar val;
|
||||
int ret;
|
||||
|
||||
/* Turn on MAX77620 LDO2 to 3.3V for SD card power */
|
||||
debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
|
||||
ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
|
||||
return;
|
||||
}
|
||||
/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
|
||||
val = 0xF2;
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_clear_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(e2220_1170_gpio_inits,
|
||||
ARRAY_SIZE(e2220_1170_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(e2220_1170_pingrps,
|
||||
ARRAY_SIZE(e2220_1170_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(e2220_1170_drvgrps,
|
||||
ARRAY_SIZE(e2220_1170_drvgrps));
|
||||
}
|
||||
@@ -0,0 +1,276 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
*
|
||||
* To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
* https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
* Run "board-to-uboot.py e2220-1170".
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_E2220_1170_H_
|
||||
#define _PINMUX_CONFIG_E2220_1170_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config e2220_1170_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 5, IN),
|
||||
GPIO_INIT(A, 6, IN),
|
||||
GPIO_INIT(B, 4, IN),
|
||||
GPIO_INIT(E, 6, IN),
|
||||
GPIO_INIT(G, 2, OUT0),
|
||||
GPIO_INIT(G, 3, OUT0),
|
||||
GPIO_INIT(H, 0, OUT0),
|
||||
GPIO_INIT(H, 1, OUT0),
|
||||
GPIO_INIT(H, 2, IN),
|
||||
GPIO_INIT(H, 3, OUT0),
|
||||
GPIO_INIT(H, 4, OUT0),
|
||||
GPIO_INIT(H, 5, IN),
|
||||
GPIO_INIT(H, 6, OUT0),
|
||||
GPIO_INIT(H, 7, OUT0),
|
||||
GPIO_INIT(I, 0, OUT0),
|
||||
GPIO_INIT(I, 1, IN),
|
||||
GPIO_INIT(I, 2, OUT0),
|
||||
GPIO_INIT(I, 3, OUT0),
|
||||
GPIO_INIT(K, 0, IN),
|
||||
GPIO_INIT(K, 1, OUT0),
|
||||
GPIO_INIT(K, 2, OUT0),
|
||||
GPIO_INIT(K, 3, OUT0),
|
||||
GPIO_INIT(K, 4, IN),
|
||||
GPIO_INIT(K, 5, OUT0),
|
||||
GPIO_INIT(K, 6, IN),
|
||||
GPIO_INIT(K, 7, OUT0),
|
||||
GPIO_INIT(L, 0, OUT0),
|
||||
GPIO_INIT(S, 4, OUT0),
|
||||
GPIO_INIT(S, 5, OUT0),
|
||||
GPIO_INIT(S, 6, OUT0),
|
||||
GPIO_INIT(S, 7, OUT0),
|
||||
GPIO_INIT(T, 0, OUT0),
|
||||
GPIO_INIT(T, 1, OUT0),
|
||||
GPIO_INIT(V, 1, OUT0),
|
||||
GPIO_INIT(V, 2, OUT0),
|
||||
GPIO_INIT(V, 3, IN),
|
||||
GPIO_INIT(V, 5, OUT0),
|
||||
GPIO_INIT(V, 6, OUT0),
|
||||
GPIO_INIT(X, 0, IN),
|
||||
GPIO_INIT(X, 1, IN),
|
||||
GPIO_INIT(X, 2, IN),
|
||||
GPIO_INIT(X, 3, IN),
|
||||
GPIO_INIT(X, 4, IN),
|
||||
GPIO_INIT(X, 5, IN),
|
||||
GPIO_INIT(X, 6, IN),
|
||||
GPIO_INIT(X, 7, IN),
|
||||
GPIO_INIT(Y, 0, IN),
|
||||
GPIO_INIT(Y, 1, IN),
|
||||
GPIO_INIT(Z, 0, IN),
|
||||
GPIO_INIT(Z, 4, OUT0),
|
||||
GPIO_INIT(BB, 2, OUT0),
|
||||
GPIO_INIT(BB, 3, OUT0),
|
||||
GPIO_INIT(BB, 4, IN),
|
||||
GPIO_INIT(CC, 1, IN),
|
||||
GPIO_INIT(CC, 5, OUT0),
|
||||
GPIO_INIT(CC, 6, IN),
|
||||
GPIO_INIT(CC, 7, OUT0),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config e2220_1170_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, e_io_hv */
|
||||
PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_E2220_1170_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_HARMONY
|
||||
|
||||
config SYS_BOARD
|
||||
default "harmony"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "harmony"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
HARMONY BOARD
|
||||
M: Tom Warren <twarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/harmony/
|
||||
F: include/configs/harmony.h
|
||||
F: configs/harmony_defconfig
|
||||
@@ -0,0 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2010,2011
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
|
||||
obj-y := harmony.o
|
||||
@@ -0,0 +1,51 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2010,2011
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <lcd.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/funcmux.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/tegra.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
#ifdef CONFIG_MMC_SDHCI_TEGRA
|
||||
/*
|
||||
* Routine: pin_mux_mmc
|
||||
* Description: setup the pin muxes/tristate values for the SDMMC(s)
|
||||
*/
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
|
||||
funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
|
||||
|
||||
/* For power GPIO PI6 */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_ATA);
|
||||
/* For CD GPIO PH2 */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_ATD);
|
||||
|
||||
/* For power GPIO PT3 */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_DTB);
|
||||
/* For CD GPIO PI5 */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_ATC);
|
||||
}
|
||||
#endif
|
||||
|
||||
void pin_mux_usb(void)
|
||||
{
|
||||
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
|
||||
pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
|
||||
pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
|
||||
/* USB2 PHY reset GPIO */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_UAC);
|
||||
}
|
||||
|
||||
void pin_mux_display(void)
|
||||
{
|
||||
pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
|
||||
pinmux_tristate_disable(PMUX_PINGRP_SDC);
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_JETSON_TK1
|
||||
|
||||
config SYS_BOARD
|
||||
default "jetson-tk1"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "jetson-tk1"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
JETSON-TK1 BOARD
|
||||
M: Stephen Warren <swarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/jetson-tk1/
|
||||
F: include/configs/jetson-tk1.h
|
||||
F: configs/jetson-tk1_defconfig
|
||||
@@ -0,0 +1,9 @@
|
||||
#
|
||||
# (C) Copyright 2014
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += ../venice2/as3722_init.o
|
||||
obj-y += jetson-tk1.o
|
||||
@@ -0,0 +1,82 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2014
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <power/as3722.h>
|
||||
#include <power/pmic.h>
|
||||
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
|
||||
#include "pinmux-config-jetson-tk1.h"
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_clear_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(jetson_tk1_gpio_inits,
|
||||
ARRAY_SIZE(jetson_tk1_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(jetson_tk1_pingrps,
|
||||
ARRAY_SIZE(jetson_tk1_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
|
||||
ARRAY_SIZE(jetson_tk1_drvgrps));
|
||||
|
||||
pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
|
||||
ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI_TEGRA
|
||||
/* TODO: Convert to driver model */
|
||||
static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (sd > 6)
|
||||
return -EINVAL;
|
||||
|
||||
err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
|
||||
if (err) {
|
||||
pr_err("failed to update SD control register: %d", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_pcie_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_PMIC,
|
||||
DM_GET_DRIVER(pmic_as3722), &dev);
|
||||
if (ret) {
|
||||
debug("%s: Failed to find PMIC\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = as3722_sd_enable(dev, 4);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to enable SD4: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = as3722_sd_set_voltage(dev, 4, 0x24);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to set SD4 voltage: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* PCI */
|
||||
@@ -0,0 +1,308 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
*
|
||||
* To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
* https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
* Run "board-to-uboot.py jetson-tk1".
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
|
||||
#define _PINMUX_CONFIG_JETSON_TK1_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(G, 0, IN),
|
||||
GPIO_INIT(G, 1, IN),
|
||||
GPIO_INIT(G, 2, IN),
|
||||
GPIO_INIT(G, 3, IN),
|
||||
GPIO_INIT(G, 4, IN),
|
||||
GPIO_INIT(H, 2, OUT0),
|
||||
GPIO_INIT(H, 4, IN),
|
||||
GPIO_INIT(H, 7, IN),
|
||||
GPIO_INIT(I, 0, OUT0),
|
||||
GPIO_INIT(I, 1, IN),
|
||||
GPIO_INIT(I, 6, IN),
|
||||
GPIO_INIT(J, 0, IN),
|
||||
GPIO_INIT(K, 1, OUT0),
|
||||
GPIO_INIT(K, 2, IN),
|
||||
GPIO_INIT(K, 4, OUT0),
|
||||
GPIO_INIT(K, 6, OUT0),
|
||||
GPIO_INIT(N, 7, IN),
|
||||
GPIO_INIT(O, 1, IN),
|
||||
GPIO_INIT(O, 4, IN),
|
||||
GPIO_INIT(P, 2, OUT0),
|
||||
GPIO_INIT(Q, 0, IN),
|
||||
GPIO_INIT(Q, 3, IN),
|
||||
GPIO_INIT(Q, 5, IN),
|
||||
GPIO_INIT(R, 0, OUT0),
|
||||
GPIO_INIT(R, 2, OUT0),
|
||||
GPIO_INIT(R, 4, IN),
|
||||
GPIO_INIT(R, 7, IN),
|
||||
GPIO_INIT(S, 7, IN),
|
||||
GPIO_INIT(T, 0, OUT0),
|
||||
GPIO_INIT(T, 1, IN),
|
||||
GPIO_INIT(U, 0, IN),
|
||||
GPIO_INIT(U, 1, IN),
|
||||
GPIO_INIT(U, 2, IN),
|
||||
GPIO_INIT(U, 3, IN),
|
||||
GPIO_INIT(U, 4, IN),
|
||||
GPIO_INIT(U, 5, IN),
|
||||
GPIO_INIT(U, 6, IN),
|
||||
GPIO_INIT(V, 0, IN),
|
||||
GPIO_INIT(V, 1, IN),
|
||||
GPIO_INIT(X, 1, IN),
|
||||
GPIO_INIT(X, 4, IN),
|
||||
GPIO_INIT(X, 7, OUT0),
|
||||
GPIO_INIT(BB, 3, OUT0),
|
||||
GPIO_INIT(BB, 5, OUT0),
|
||||
GPIO_INIT(BB, 6, OUT0),
|
||||
GPIO_INIT(BB, 7, OUT0),
|
||||
GPIO_INIT(CC, 1, IN),
|
||||
GPIO_INIT(CC, 2, IN),
|
||||
GPIO_INIT(EE, 2, OUT1),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, rcv_sel */
|
||||
PINCFG(CLK_32K_OUT_PA0, SOC, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB0, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB1, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RXD_PC3, IRDA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG2, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI6, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_CTS_N_PJ5, UARTB, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA0_PO1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA3_PO4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL0_PQ0, DEFAULT, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL2_PQ2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL4_PQ4, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL5_PQ5, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL6_PQ6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL7_PQ7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW1_PR1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW11_PS3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU5, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_W3_AUD_PW3, SPI6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PY4, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PY5, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PY6, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PY7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PZ0, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PZ1, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_REQ_PEE2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DP_HPD_PFF0, DP, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
|
||||
};
|
||||
|
||||
#define MIPIPADCTRLCFG(_grp, _mux) \
|
||||
{ \
|
||||
.grp = PMUX_MIPIPADCTRLGRP_##_grp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
}
|
||||
|
||||
static const struct pmux_mipipadctrlgrp_config jetson_tk1_mipipadctrlgrps[] = {
|
||||
/* grp, mux */
|
||||
MIPIPADCTRLCFG(DSI_B, DSI_B),
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_JETSON_TK1_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_NYAN_BIG
|
||||
|
||||
config SYS_BOARD
|
||||
default "nyan-big"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "nyan-big"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
NYAN-BIG BOARD
|
||||
M: Allen Martin <amartin@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/nyan-big/
|
||||
F: include/configs/nyan-big.h
|
||||
F: configs/nyan-big_defconfig
|
||||
@@ -0,0 +1,9 @@
|
||||
#
|
||||
# (C) Copyright 2014
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += ../venice2/as3722_init.o
|
||||
obj-y += nyan-big.o
|
||||
@@ -0,0 +1,18 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright 2018 Google LLC
|
||||
# Written by Simon Glass <sjg@chromium.org>
|
||||
|
||||
U-Boot on Nyan
|
||||
==============
|
||||
|
||||
Nyan-big is supported by mainline U-Boot. This device is based on Tegra124.
|
||||
To build it, use the nyan-big config.
|
||||
|
||||
To boot it, connect a USB A-A cable from your computer to the back USB port.
|
||||
Connect a servo board. Then with t20_rec and warn_rst held down:
|
||||
|
||||
sudo tegrarcm --bct cbootimage-configs/tegra124/nvidia/norrin/PM370_Hynix_2GB_H5TC4G63AFR_PBA_924MHz_01212014.bct
|
||||
--bootloader u-boot-dtb-tegra.bin --loadaddr 0x80108000
|
||||
|
||||
The norrin config is close enough that it works well with Nyan.
|
||||
@@ -0,0 +1,132 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2014
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/mc.h>
|
||||
#include <asm/arch-tegra/clk_rst.h>
|
||||
#include <asm/arch-tegra/pmc.h>
|
||||
#include <power/as3722.h>
|
||||
#include <power/pmic.h>
|
||||
#include "pinmux-config-nyan-big.h"
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
gpio_config_table(nyan_big_gpio_inits,
|
||||
ARRAY_SIZE(nyan_big_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(nyan_big_pingrps,
|
||||
ARRAY_SIZE(nyan_big_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(nyan_big_drvgrps,
|
||||
ARRAY_SIZE(nyan_big_drvgrps));
|
||||
}
|
||||
|
||||
int tegra_board_id(void)
|
||||
{
|
||||
static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
|
||||
TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
|
||||
-1};
|
||||
|
||||
gpio_claim_vector(vector, "board_id%d");
|
||||
return gpio_get_values_as_int(vector);
|
||||
}
|
||||
|
||||
int tegra_lcd_pmic_init(int board_id)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_PMIC,
|
||||
DM_GET_DRIVER(pmic_as3722), &dev);
|
||||
if (ret) {
|
||||
debug("%s: Failed to find PMIC\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (board_id == 0)
|
||||
pmic_reg_write(dev, 0x00, 0x3c);
|
||||
else
|
||||
pmic_reg_write(dev, 0x00, 0x50);
|
||||
pmic_reg_write(dev, 0x12, 0x10);
|
||||
pmic_reg_write(dev, 0x0c, 0x07);
|
||||
pmic_reg_write(dev, 0x20, 0x10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Setup required information for Linux kernel */
|
||||
static void setup_kernel_info(void)
|
||||
{
|
||||
struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
|
||||
|
||||
/* The kernel graphics driver needs this region locked down */
|
||||
writel(0, &mc->mc_video_protect_bom);
|
||||
writel(0, &mc->mc_video_protect_size_mb);
|
||||
writel(1, &mc->mc_video_protect_reg_ctrl);
|
||||
}
|
||||
|
||||
/*
|
||||
* We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
|
||||
* I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
|
||||
* Otherwise reading AHUB devices will hang when the kernel boots.
|
||||
*/
|
||||
static void enable_required_clocks(void)
|
||||
{
|
||||
static enum periph_id ids[] = {
|
||||
PERIPH_ID_I2S0,
|
||||
PERIPH_ID_I2S1,
|
||||
PERIPH_ID_I2S2,
|
||||
PERIPH_ID_I2S3,
|
||||
PERIPH_ID_I2S4,
|
||||
PERIPH_ID_AUDIO,
|
||||
PERIPH_ID_APBIF,
|
||||
PERIPH_ID_DAM0,
|
||||
PERIPH_ID_DAM1,
|
||||
PERIPH_ID_DAM2,
|
||||
PERIPH_ID_AMX0,
|
||||
PERIPH_ID_AMX1,
|
||||
PERIPH_ID_ADX0,
|
||||
PERIPH_ID_ADX1,
|
||||
PERIPH_ID_SPDIF,
|
||||
PERIPH_ID_AFC0,
|
||||
PERIPH_ID_AFC1,
|
||||
PERIPH_ID_AFC2,
|
||||
PERIPH_ID_AFC3,
|
||||
PERIPH_ID_AFC4,
|
||||
PERIPH_ID_AFC5,
|
||||
PERIPH_ID_EXTPERIPH1
|
||||
};
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ids); i++)
|
||||
clock_enable(ids[i]);
|
||||
udelay(2);
|
||||
for (i = 0; i < ARRAY_SIZE(ids); i++)
|
||||
reset_set_enable(ids[i], 0);
|
||||
}
|
||||
|
||||
int nvidia_board_init(void)
|
||||
{
|
||||
clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
|
||||
clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_CLK_M, 1500000);
|
||||
|
||||
/* For external MAX98090 audio codec */
|
||||
clock_external_output(1);
|
||||
setup_kernel_info();
|
||||
enable_required_clocks();
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,294 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
*
|
||||
* To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
* https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
* Run "board-to-uboot.py nyan-big".
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_NYAN_BIG_H_
|
||||
#define _PINMUX_CONFIG_NYAN_BIG_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config nyan_big_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 0, IN),
|
||||
GPIO_INIT(C, 7, IN),
|
||||
GPIO_INIT(G, 0, IN),
|
||||
GPIO_INIT(G, 1, IN),
|
||||
GPIO_INIT(G, 2, IN),
|
||||
GPIO_INIT(G, 3, IN),
|
||||
GPIO_INIT(H, 2, IN),
|
||||
GPIO_INIT(H, 4, IN),
|
||||
GPIO_INIT(H, 6, IN),
|
||||
GPIO_INIT(H, 7, OUT1),
|
||||
GPIO_INIT(I, 0, IN),
|
||||
GPIO_INIT(I, 1, IN),
|
||||
GPIO_INIT(I, 5, OUT1),
|
||||
GPIO_INIT(I, 6, IN),
|
||||
GPIO_INIT(I, 7, IN),
|
||||
GPIO_INIT(J, 0, IN),
|
||||
GPIO_INIT(J, 7, IN),
|
||||
GPIO_INIT(K, 1, OUT0),
|
||||
GPIO_INIT(K, 2, IN),
|
||||
GPIO_INIT(K, 4, OUT0),
|
||||
GPIO_INIT(K, 6, OUT0),
|
||||
GPIO_INIT(K, 7, IN),
|
||||
GPIO_INIT(N, 7, IN),
|
||||
GPIO_INIT(P, 2, OUT0),
|
||||
GPIO_INIT(Q, 0, IN),
|
||||
GPIO_INIT(Q, 2, IN),
|
||||
GPIO_INIT(Q, 3, IN),
|
||||
GPIO_INIT(Q, 6, IN),
|
||||
GPIO_INIT(Q, 7, IN),
|
||||
GPIO_INIT(R, 0, OUT0),
|
||||
GPIO_INIT(R, 1, IN),
|
||||
GPIO_INIT(R, 4, IN),
|
||||
GPIO_INIT(R, 7, IN),
|
||||
GPIO_INIT(S, 3, OUT0),
|
||||
GPIO_INIT(S, 4, OUT0),
|
||||
GPIO_INIT(S, 7, IN),
|
||||
GPIO_INIT(T, 1, IN),
|
||||
GPIO_INIT(U, 4, IN),
|
||||
GPIO_INIT(U, 5, IN),
|
||||
GPIO_INIT(U, 6, IN),
|
||||
GPIO_INIT(V, 0, IN),
|
||||
GPIO_INIT(W, 3, IN),
|
||||
GPIO_INIT(X, 1, IN),
|
||||
GPIO_INIT(X, 4, IN),
|
||||
GPIO_INIT(X, 7, OUT0),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config nyan_big_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, rcv_sel */
|
||||
PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_TXD_PC2, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RXD_PC3, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI5, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_CTS_N_PJ5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RTS_N_PJ6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PN2, I2S0, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL2_PQ2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL6_PQ6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL7_PQ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_OUT_PEE0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DP_HPD_PFF0, DP, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config nyan_big_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_NYAN_BIG_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_P2371_0000
|
||||
|
||||
config SYS_BOARD
|
||||
default "p2371-0000"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "p2371-0000"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
P2371-0000 BOARD
|
||||
M: Tom Warren <twarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/p2371-0000/
|
||||
F: include/configs/p2371-0000.h
|
||||
F: configs/p2371-0000_defconfig
|
||||
@@ -0,0 +1,8 @@
|
||||
#
|
||||
# (C) Copyright 2013-2015
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += p2371-0000.o
|
||||
@@ -0,0 +1,50 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013-2015
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include "../p2571/max77620_init.h"
|
||||
#include "pinmux-config-p2371-0000.h"
|
||||
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
uchar val;
|
||||
int ret;
|
||||
|
||||
/* Turn on MAX77620 LDO2 to 3.3V for SD card power */
|
||||
debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
|
||||
ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
|
||||
return;
|
||||
}
|
||||
/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
|
||||
val = 0xF2;
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_clear_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(p2371_0000_gpio_inits,
|
||||
ARRAY_SIZE(p2371_0000_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(p2371_0000_pingrps,
|
||||
ARRAY_SIZE(p2371_0000_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(p2371_0000_drvgrps,
|
||||
ARRAY_SIZE(p2371_0000_drvgrps));
|
||||
}
|
||||
@@ -0,0 +1,267 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
*
|
||||
* To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
* https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
* Run "board-to-uboot.py p2371-0000".
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_P2371_0000_H_
|
||||
#define _PINMUX_CONFIG_P2371_0000_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config p2371_0000_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 5, IN),
|
||||
GPIO_INIT(E, 4, OUT0),
|
||||
GPIO_INIT(E, 6, IN),
|
||||
GPIO_INIT(G, 0, IN),
|
||||
GPIO_INIT(G, 3, OUT0),
|
||||
GPIO_INIT(H, 0, OUT0),
|
||||
GPIO_INIT(H, 2, IN),
|
||||
GPIO_INIT(H, 3, OUT0),
|
||||
GPIO_INIT(H, 4, OUT0),
|
||||
GPIO_INIT(H, 5, IN),
|
||||
GPIO_INIT(H, 6, OUT0),
|
||||
GPIO_INIT(H, 7, OUT0),
|
||||
GPIO_INIT(I, 0, OUT0),
|
||||
GPIO_INIT(I, 1, IN),
|
||||
GPIO_INIT(I, 2, OUT0),
|
||||
GPIO_INIT(I, 3, OUT0),
|
||||
GPIO_INIT(K, 4, IN),
|
||||
GPIO_INIT(K, 5, OUT0),
|
||||
GPIO_INIT(K, 6, IN),
|
||||
GPIO_INIT(K, 7, OUT0),
|
||||
GPIO_INIT(L, 0, OUT0),
|
||||
GPIO_INIT(S, 4, OUT0),
|
||||
GPIO_INIT(S, 5, OUT0),
|
||||
GPIO_INIT(S, 6, OUT0),
|
||||
GPIO_INIT(S, 7, OUT0),
|
||||
GPIO_INIT(T, 0, OUT0),
|
||||
GPIO_INIT(T, 1, OUT0),
|
||||
GPIO_INIT(V, 1, OUT0),
|
||||
GPIO_INIT(V, 2, OUT0),
|
||||
GPIO_INIT(V, 5, OUT0),
|
||||
GPIO_INIT(V, 6, OUT0),
|
||||
GPIO_INIT(V, 7, OUT1),
|
||||
GPIO_INIT(X, 0, IN),
|
||||
GPIO_INIT(X, 1, IN),
|
||||
GPIO_INIT(X, 2, IN),
|
||||
GPIO_INIT(X, 3, IN),
|
||||
GPIO_INIT(X, 4, IN),
|
||||
GPIO_INIT(X, 5, IN),
|
||||
GPIO_INIT(X, 6, IN),
|
||||
GPIO_INIT(X, 7, IN),
|
||||
GPIO_INIT(Y, 1, IN),
|
||||
GPIO_INIT(Z, 0, IN),
|
||||
GPIO_INIT(Z, 4, OUT0),
|
||||
GPIO_INIT(BB, 2, OUT0),
|
||||
GPIO_INIT(BB, 3, OUT0),
|
||||
GPIO_INIT(CC, 1, IN),
|
||||
GPIO_INIT(CC, 6, IN),
|
||||
GPIO_INIT(CC, 7, OUT0),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config p2371_0000_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, e_io_hv */
|
||||
PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MOSI_PC0, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MISO_PC1, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_SCK_PC2, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS0_PC3, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS1_PC4, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_DAT_PE1, DMIC1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_DAT_PE3, DMIC2, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK0, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK1, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK2, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK3, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_CLK_PV7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config p2371_0000_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_P2371_0000_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_P2371_2180
|
||||
|
||||
config SYS_BOARD
|
||||
default "p2371-2180"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "p2371-2180"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
P2371-2180 BOARD
|
||||
M: Tom Warren <twarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/p2371-2180/
|
||||
F: include/configs/p2371-2180.h
|
||||
F: configs/p2371-2180_defconfig
|
||||
@@ -0,0 +1,8 @@
|
||||
#
|
||||
# (C) Copyright 2013-2015
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += p2371-2180.o
|
||||
@@ -0,0 +1,193 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013-2015
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <fdtdec.h>
|
||||
#include <i2c.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch-tegra/cboot.h>
|
||||
#include "../p2571/max77620_init.h"
|
||||
#include "pinmux-config-p2371-2180.h"
|
||||
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
uchar val;
|
||||
int ret;
|
||||
|
||||
/* Turn on MAX77620 LDO2 to 3.3V for SD card power */
|
||||
debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
|
||||
ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
|
||||
return;
|
||||
}
|
||||
/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
|
||||
val = 0xF2;
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
|
||||
|
||||
/* Disable LDO4 discharge */
|
||||
ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
|
||||
if (ret) {
|
||||
printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
|
||||
} else {
|
||||
val &= ~BIT(1); /* ADE */
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/* Set MBLPD */
|
||||
ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
|
||||
if (ret) {
|
||||
printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
|
||||
} else {
|
||||
val |= BIT(6); /* MBLPD */
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_clear_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(p2371_2180_gpio_inits,
|
||||
ARRAY_SIZE(p2371_2180_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(p2371_2180_pingrps,
|
||||
ARRAY_SIZE(p2371_2180_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(p2371_2180_drvgrps,
|
||||
ARRAY_SIZE(p2371_2180_drvgrps));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI_TEGRA
|
||||
int tegra_pcie_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
uchar val;
|
||||
int ret;
|
||||
|
||||
/* Turn on MAX77620 LDO1 to 1.05V for PEX power */
|
||||
debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__);
|
||||
ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
/* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
|
||||
val = 0xCA;
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* PCI */
|
||||
|
||||
static void ft_mac_address_setup(void *fdt)
|
||||
{
|
||||
const void *cboot_fdt = (const void *)cboot_boot_x0;
|
||||
uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
|
||||
const char *path;
|
||||
int offset, err;
|
||||
|
||||
err = cboot_get_ethaddr(cboot_fdt, local_mac);
|
||||
if (err < 0)
|
||||
memset(local_mac, 0, ETH_ALEN);
|
||||
|
||||
path = fdt_get_alias(fdt, "ethernet");
|
||||
if (!path)
|
||||
return;
|
||||
|
||||
debug("ethernet alias found: %s\n", path);
|
||||
|
||||
offset = fdt_path_offset(fdt, path);
|
||||
if (offset < 0) {
|
||||
printf("ethernet alias points to absent node %s\n", path);
|
||||
return;
|
||||
}
|
||||
|
||||
if (is_valid_ethaddr(local_mac)) {
|
||||
err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
|
||||
ETH_ALEN);
|
||||
if (!err)
|
||||
debug("Local MAC address set: %pM\n", local_mac);
|
||||
}
|
||||
|
||||
if (eth_env_get_enetaddr("ethaddr", mac)) {
|
||||
if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
|
||||
err = fdt_setprop(fdt, offset, "mac-address", mac,
|
||||
ETH_ALEN);
|
||||
if (!err)
|
||||
debug("MAC address set: %pM\n", mac);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int ft_copy_carveout(void *dst, const void *src, const char *node)
|
||||
{
|
||||
struct fdt_memory fb;
|
||||
int err;
|
||||
|
||||
err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
|
||||
if (err < 0) {
|
||||
if (err != -FDT_ERR_NOTFOUND)
|
||||
printf("failed to get carveout for %s: %d\n", node,
|
||||
err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
|
||||
&fb);
|
||||
if (err < 0) {
|
||||
printf("failed to set carveout for %s: %d\n", node, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ft_carveout_setup(void *fdt)
|
||||
{
|
||||
const void *cboot_fdt = (const void *)cboot_boot_x0;
|
||||
static const char * const nodes[] = {
|
||||
"/host1x@50000000/dc@54200000",
|
||||
"/host1x@50000000/dc@54240000",
|
||||
};
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(nodes); i++) {
|
||||
err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
|
||||
if (err < 0) {
|
||||
if (err != -FDT_ERR_NOTFOUND)
|
||||
printf("failed to copy carveout for %s: %d\n",
|
||||
nodes[i], err);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int ft_board_setup(void *fdt, bd_t *bd)
|
||||
{
|
||||
ft_mac_address_setup(fdt);
|
||||
ft_carveout_setup(fdt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,278 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
*
|
||||
* To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
* https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
* Run "board-to-uboot.py p2371-2180".
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_P2371_2180_H_
|
||||
#define _PINMUX_CONFIG_P2371_2180_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config p2371_2180_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 5, IN),
|
||||
GPIO_INIT(B, 0, IN),
|
||||
GPIO_INIT(B, 1, IN),
|
||||
GPIO_INIT(B, 2, IN),
|
||||
GPIO_INIT(B, 3, IN),
|
||||
GPIO_INIT(C, 0, IN),
|
||||
GPIO_INIT(C, 1, IN),
|
||||
GPIO_INIT(C, 2, IN),
|
||||
GPIO_INIT(C, 3, IN),
|
||||
GPIO_INIT(C, 4, IN),
|
||||
GPIO_INIT(E, 4, IN),
|
||||
GPIO_INIT(E, 5, IN),
|
||||
GPIO_INIT(E, 6, IN),
|
||||
GPIO_INIT(H, 0, OUT0),
|
||||
GPIO_INIT(H, 1, OUT0),
|
||||
GPIO_INIT(H, 2, IN),
|
||||
GPIO_INIT(H, 3, OUT0),
|
||||
GPIO_INIT(H, 4, OUT0),
|
||||
GPIO_INIT(H, 5, IN),
|
||||
GPIO_INIT(H, 6, IN),
|
||||
GPIO_INIT(H, 7, IN),
|
||||
GPIO_INIT(I, 0, OUT0),
|
||||
GPIO_INIT(I, 1, IN),
|
||||
GPIO_INIT(I, 2, OUT0),
|
||||
GPIO_INIT(K, 4, IN),
|
||||
GPIO_INIT(K, 5, OUT0),
|
||||
GPIO_INIT(K, 6, IN),
|
||||
GPIO_INIT(K, 7, IN),
|
||||
GPIO_INIT(L, 1, IN),
|
||||
GPIO_INIT(S, 4, OUT0),
|
||||
GPIO_INIT(S, 5, OUT0),
|
||||
GPIO_INIT(S, 6, OUT0),
|
||||
GPIO_INIT(S, 7, OUT0),
|
||||
GPIO_INIT(T, 0, OUT0),
|
||||
GPIO_INIT(T, 1, OUT0),
|
||||
GPIO_INIT(U, 2, IN),
|
||||
GPIO_INIT(U, 3, IN),
|
||||
GPIO_INIT(V, 1, OUT0),
|
||||
GPIO_INIT(V, 2, OUT0),
|
||||
GPIO_INIT(V, 3, IN),
|
||||
GPIO_INIT(V, 5, OUT0),
|
||||
GPIO_INIT(V, 6, OUT0),
|
||||
GPIO_INIT(X, 0, IN),
|
||||
GPIO_INIT(X, 1, IN),
|
||||
GPIO_INIT(X, 2, IN),
|
||||
GPIO_INIT(X, 3, IN),
|
||||
GPIO_INIT(X, 4, IN),
|
||||
GPIO_INIT(X, 5, IN),
|
||||
GPIO_INIT(X, 6, IN),
|
||||
GPIO_INIT(X, 7, IN),
|
||||
GPIO_INIT(Y, 0, IN),
|
||||
GPIO_INIT(Y, 1, IN),
|
||||
GPIO_INIT(Z, 0, IN),
|
||||
GPIO_INIT(Z, 2, IN),
|
||||
GPIO_INIT(Z, 3, OUT0),
|
||||
GPIO_INIT(BB, 0, IN),
|
||||
GPIO_INIT(BB, 2, OUT0),
|
||||
GPIO_INIT(BB, 3, IN),
|
||||
GPIO_INIT(CC, 1, IN),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config p2371_2180_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, e_io_hv */
|
||||
PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PA6, SATA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_FS_PB0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PB1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PB2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PB3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MOSI_PB4, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MISO_PB5, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_SCK_PB6, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_CS0_PB7, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_SCK_PC5, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_CS0_PC6, SPI4, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MOSI_PC7, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MISO_PD0, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_CLK_PE4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_DAT_PE5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RX_PG1, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RTS_PG2, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_CTS_PG3, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_NFC_PH7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_INT_PI1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK0, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK1, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK2, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK3, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RTS_PU2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_CTS_PU3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO1_PV3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(ALS_PROX_INT_PX3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(DP_HPD0_PCC6, DP, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPI2_CS1_PDD0, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config p2371_2180_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_P2371_2180_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_P2571
|
||||
|
||||
config SYS_BOARD
|
||||
default "p2571"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "p2571"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
P2571 BOARD
|
||||
M: Tom Warren <twarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/p2571/
|
||||
F: include/configs/p2571.h
|
||||
F: configs/p2571_defconfig
|
||||
@@ -0,0 +1,8 @@
|
||||
#
|
||||
# (C) Copyright 2013-2015
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += p2571.o
|
||||
@@ -0,0 +1,69 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2013-2015
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#ifndef _MAX77620_INIT_H_
|
||||
#define _MAX77620_INIT_H_
|
||||
|
||||
/* MAX77620-PMIC-specific early init regs */
|
||||
|
||||
#define MAX77620_I2C_ADDR 0x78
|
||||
#define MAX77620_I2C_ADDR_7BIT 0x3C
|
||||
|
||||
#define MAX77620_CNFGGLBL1_REG 0x00
|
||||
|
||||
#define MAX77620_SD0_REG 0x16
|
||||
#define MAX77620_SD1_REG 0x17
|
||||
#define MAX77620_SD2_REG 0x18
|
||||
#define MAX77620_SD3_REG 0x19
|
||||
#define MAX77620_CNFG2SD_REG 0x22
|
||||
|
||||
#define MAX77620_CNFG1_L0_REG 0x23
|
||||
#define MAX77620_CNFG2_L0_REG 0x24
|
||||
#define MAX77620_CNFG1_L1_REG 0x25
|
||||
#define MAX77620_CNFG2_L1_REG 0x26
|
||||
#define MAX77620_CNFG1_L2_REG 0x27
|
||||
#define MAX77620_CNFG2_L2_REG 0x28
|
||||
#define MAX77620_CNFG1_L3_REG 0x29
|
||||
#define MAX77620_CNFG2_L3_REG 0x2A
|
||||
#define MAX77620_CNFG1_L4_REG 0x2B
|
||||
#define MAX77620_CNFG2_L4_REG 0x2C
|
||||
#define MAX77620_CNFG1_L5_REG 0x2D
|
||||
#define MAX77620_CNFG2_L5_REG 0x2E
|
||||
#define MAX77620_CNFG1_L6_REG 0x2F
|
||||
#define MAX77620_CNFG2_L6_REG 0x30
|
||||
#define MAX77620_CNFG1_L7_REG 0x31
|
||||
#define MAX77620_CNFG2_L7_REG 0x32
|
||||
#define MAX77620_CNFG1_L8_REG 0x33
|
||||
#define MAX77620_CNFG2_L8_REG 0x34
|
||||
#define MAX77620_CNFG3_LDO_REG 0x35
|
||||
|
||||
#define MAX77620_GPIO0_REG 0x36
|
||||
#define MAX77620_GPIO1_REG 0x37
|
||||
#define MAX77620_GPIO2_REG 0x38
|
||||
#define MAX77620_GPIO3_REG 0x39
|
||||
#define MAX77620_GPIO4_REG 0x3A
|
||||
#define MAX77620_GPIO5_REG 0x3B
|
||||
#define MAX77620_GPIO6_REG 0x3C
|
||||
#define MAX77620_GPIO7_REG 0x3D
|
||||
#define MAX77620_GPIO_PUE_GPIO 0x3E
|
||||
#define MAX77620_GPIO_PDE_GPIO 0x3F
|
||||
|
||||
#define MAX77620_AME_GPIO 0x40
|
||||
#define MAX77620_REG_ONOFF_CFG1 0x41
|
||||
#define MAX77620_REG_ONOFF_CFG2 0x42
|
||||
|
||||
#define MAX77620_CID0_REG 0x58
|
||||
#define MAX77620_CID1_REG 0x59
|
||||
#define MAX77620_CID2_REG 0x5A
|
||||
#define MAX77620_CID3_REG 0x5B
|
||||
#define MAX77620_CID4_REG 0x5C
|
||||
#define MAX77620_CID5_REG 0x5D
|
||||
|
||||
#define I2C_SEND_2_BYTES 0x0A02
|
||||
|
||||
void pmic_enable_cpu_vdd(void);
|
||||
|
||||
#endif /* _MAX77620_INIT_H_ */
|
||||
@@ -0,0 +1,62 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013-2015
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/gpio.h>
|
||||
#include "max77620_init.h"
|
||||
#include "pinmux-config-p2571.h"
|
||||
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
uchar val;
|
||||
int ret;
|
||||
|
||||
/* Turn on MAX77620 LDO2 to 3.3V for SD card power */
|
||||
debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
|
||||
ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
|
||||
return;
|
||||
}
|
||||
/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
|
||||
val = 0xF2;
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_clear_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(p2571_gpio_inits,
|
||||
ARRAY_SIZE(p2571_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(p2571_pingrps,
|
||||
ARRAY_SIZE(p2571_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(p2571_drvgrps,
|
||||
ARRAY_SIZE(p2571_drvgrps));
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: start_cpu_fan
|
||||
* Description: Enable/start PWM CPU fan on P2571
|
||||
*/
|
||||
void start_cpu_fan(void)
|
||||
{
|
||||
/* GPIO_PE4 is PS_VDD_FAN_ENABLE */
|
||||
gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD");
|
||||
gpio_direction_output(TEGRA_GPIO(E, 4), 1);
|
||||
}
|
||||
@@ -0,0 +1,242 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
*
|
||||
* To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
* https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
* Run "board-to-uboot.py p2571".
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_P2571_H_
|
||||
#define _PINMUX_CONFIG_P2571_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config p2571_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 0, IN),
|
||||
GPIO_INIT(A, 5, IN),
|
||||
GPIO_INIT(D, 4, IN),
|
||||
GPIO_INIT(E, 4, OUT0),
|
||||
GPIO_INIT(G, 0, IN),
|
||||
GPIO_INIT(H, 0, OUT0),
|
||||
GPIO_INIT(H, 2, IN),
|
||||
GPIO_INIT(H, 3, OUT0),
|
||||
GPIO_INIT(H, 4, OUT0),
|
||||
GPIO_INIT(H, 5, IN),
|
||||
GPIO_INIT(I, 0, OUT0),
|
||||
GPIO_INIT(I, 1, IN),
|
||||
GPIO_INIT(V, 1, OUT0),
|
||||
GPIO_INIT(V, 6, OUT1),
|
||||
GPIO_INIT(X, 4, IN),
|
||||
GPIO_INIT(X, 6, IN),
|
||||
GPIO_INIT(X, 7, IN),
|
||||
GPIO_INIT(Y, 1, IN),
|
||||
GPIO_INIT(Z, 0, IN),
|
||||
GPIO_INIT(Z, 4, OUT0),
|
||||
GPIO_INIT(BB, 2, OUT0),
|
||||
GPIO_INIT(CC, 1, IN),
|
||||
GPIO_INIT(CC, 3, IN),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config p2571_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, e_io_hv */
|
||||
PINCFG(PEX_L0_RST_N_PA0, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PA1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_WAKE_N_PA2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L1_RST_N_PA3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PA4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MOSI_PC0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MISO_PC1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_SCK_PC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS0_PC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS1_PC4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_TX_PD1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RX_PD2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RTS_PD3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_CTS_PD4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_CTS_PG3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PH6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_NFC_PH7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_EN_PI2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(DAP4_FS_PJ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PJ5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PJ6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PJ7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_MCLK_PS0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_MCLK_PS1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_AF_EN_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_PWDN_PS7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_PWDN_PT0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(ALS_PROX_INT_PX3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_POWER_ON_PX5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_TE_PY2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PCC3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(DP_HPD0_PCC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config p2571_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_P2571_H */
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (c) 2016, NVIDIA CORPORATION.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
if TARGET_P2771_0000
|
||||
|
||||
config SYS_BOARD
|
||||
default "p2771-0000"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "p2771-0000"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,7 @@
|
||||
P2771-0000 BOARD
|
||||
M: Stephen Warren <swarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/p2771-0000/
|
||||
F: include/configs/p2771-0000.h
|
||||
F: configs/p2771-0000-000_defconfig
|
||||
F: configs/p2771-0000-500_defconfig
|
||||
@@ -0,0 +1,5 @@
|
||||
# Copyright (c) 2016, NVIDIA CORPORATION.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
obj-y += p2771-0000.o
|
||||
@@ -0,0 +1,155 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2016, NVIDIA CORPORATION
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <fdtdec.h>
|
||||
#include <i2c.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <asm/arch-tegra/cboot.h>
|
||||
#include "../p2571/max77620_init.h"
|
||||
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
uchar val;
|
||||
int ret;
|
||||
|
||||
/* Turn on MAX77620 LDO3 to 3.3V for SD card power */
|
||||
debug("%s: Set LDO3 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
|
||||
ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
|
||||
return;
|
||||
}
|
||||
/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
|
||||
val = 0xF2;
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFG1_L3_REG, &val, 1);
|
||||
if (ret) {
|
||||
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI_TEGRA
|
||||
int tegra_pcie_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
uchar val;
|
||||
int ret;
|
||||
|
||||
/* Turn on MAX77620 LDO7 to 1.05V for PEX power */
|
||||
debug("%s: Set LDO7 for PEX power to 1.05V\n", __func__);
|
||||
ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
/* 0xC5 for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
|
||||
val = 0xC5;
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFG1_L7_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x31 failed: %d\n", ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void ft_mac_address_setup(void *fdt)
|
||||
{
|
||||
const void *cboot_fdt = (const void *)cboot_boot_x0;
|
||||
uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
|
||||
const char *path;
|
||||
int offset, err;
|
||||
|
||||
err = cboot_get_ethaddr(cboot_fdt, local_mac);
|
||||
if (err < 0)
|
||||
memset(local_mac, 0, ETH_ALEN);
|
||||
|
||||
path = fdt_get_alias(fdt, "ethernet");
|
||||
if (!path)
|
||||
return;
|
||||
|
||||
debug("ethernet alias found: %s\n", path);
|
||||
|
||||
offset = fdt_path_offset(fdt, path);
|
||||
if (offset < 0) {
|
||||
printf("ethernet alias points to absent node %s\n", path);
|
||||
return;
|
||||
}
|
||||
|
||||
if (is_valid_ethaddr(local_mac)) {
|
||||
err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
|
||||
ETH_ALEN);
|
||||
if (!err)
|
||||
debug("Local MAC address set: %pM\n", local_mac);
|
||||
}
|
||||
|
||||
if (eth_env_get_enetaddr("ethaddr", mac)) {
|
||||
if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
|
||||
err = fdt_setprop(fdt, offset, "mac-address", mac,
|
||||
ETH_ALEN);
|
||||
if (!err)
|
||||
debug("MAC address set: %pM\n", mac);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int ft_copy_carveout(void *dst, const void *src, const char *node)
|
||||
{
|
||||
struct fdt_memory fb;
|
||||
int err;
|
||||
|
||||
err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
|
||||
if (err < 0) {
|
||||
if (err != -FDT_ERR_NOTFOUND)
|
||||
printf("failed to get carveout for %s: %d\n", node,
|
||||
err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
|
||||
&fb);
|
||||
if (err < 0) {
|
||||
printf("failed to set carveout for %s: %d\n", node, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ft_carveout_setup(void *fdt)
|
||||
{
|
||||
const void *cboot_fdt = (const void *)cboot_boot_x0;
|
||||
static const char * const nodes[] = {
|
||||
"/host1x@13e00000/display-hub@15200000/display@15200000",
|
||||
"/host1x@13e00000/display-hub@15200000/display@15210000",
|
||||
"/host1x@13e00000/display-hub@15200000/display@15220000",
|
||||
};
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(nodes); i++) {
|
||||
printf("copying carveout for %s...\n", nodes[i]);
|
||||
|
||||
err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
|
||||
if (err < 0) {
|
||||
if (err != -FDT_ERR_NOTFOUND)
|
||||
printf("failed to copy carveout for %s: %d\n",
|
||||
nodes[i], err);
|
||||
|
||||
continue;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int ft_board_setup(void *fdt, bd_t *bd)
|
||||
{
|
||||
ft_mac_address_setup(fdt);
|
||||
ft_carveout_setup(fdt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_SEABOARD
|
||||
|
||||
config SYS_BOARD
|
||||
default "seaboard"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "seaboard"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
SEABOARD BOARD
|
||||
M: Tom Warren <twarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/seaboard/
|
||||
F: include/configs/seaboard.h
|
||||
F: configs/seaboard_defconfig
|
||||
@@ -0,0 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2010,2011
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
|
||||
obj-y := seaboard.o
|
||||
@@ -0,0 +1,55 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2010,2011
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/tegra.h>
|
||||
#include <asm/arch-tegra/board.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/funcmux.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
/* TODO: Remove this code when the SPI switch is working */
|
||||
#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
|
||||
void gpio_early_init_uart(void)
|
||||
{
|
||||
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
|
||||
gpio_request(TEGRA_GPIO(I, 3), "uart_en");
|
||||
gpio_direction_output(TEGRA_GPIO(I, 3), 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC_SDHCI_TEGRA
|
||||
/*
|
||||
* Routine: pin_mux_mmc
|
||||
* Description: setup the pin muxes/tristate values for the SDMMC(s)
|
||||
*/
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
|
||||
funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
|
||||
|
||||
/* For power GPIO PI6 */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_ATA);
|
||||
/* For CD GPIO PI5 */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_ATC);
|
||||
}
|
||||
#endif
|
||||
|
||||
void pin_mux_usb(void)
|
||||
{
|
||||
/* For USB0's GPIO PD0. For now, since we have no pinmux in fdt */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_SLXK);
|
||||
/* For USB1's ULPI signals */
|
||||
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
|
||||
pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
|
||||
pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
|
||||
/* USB1 PHY reset GPIO */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_UAC);
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_VENICE2
|
||||
|
||||
config SYS_BOARD
|
||||
default "venice2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "venice2"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
VENICE2 BOARD
|
||||
M: Tom Warren <twarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/venice2/
|
||||
F: include/configs/venice2.h
|
||||
F: configs/venice2_defconfig
|
||||
@@ -0,0 +1,9 @@
|
||||
#
|
||||
# (C) Copyright 2013-2014
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += as3722_init.o
|
||||
obj-y += venice2.o
|
||||
@@ -0,0 +1,101 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include "as3722_init.h"
|
||||
|
||||
/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
|
||||
|
||||
void tegra_i2c_ll_write_addr(uint addr, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(addr, ®->cmd_addr0);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void tegra_i2c_ll_write_data(uint data, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(data, ®->cmd_data1);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void pmic_enable_cpu_vdd(void)
|
||||
{
|
||||
debug("%s entry\n", __func__);
|
||||
|
||||
#ifdef AS3722_SD1VOLTAGE_DATA
|
||||
/* Set up VDD_CORE, for boards where OTP is incorrect*/
|
||||
debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
|
||||
/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
#endif
|
||||
|
||||
debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
|
||||
/*
|
||||
* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.0V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
|
||||
/*
|
||||
* Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.0V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
|
||||
/*
|
||||
* Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.2V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
|
||||
/*
|
||||
* Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set it to bypass 3.3V straight thru, then enable the regulator
|
||||
*
|
||||
* NOTE: We do this early because doing it later seems to hose the CPU
|
||||
* power rail/partition startup. Need to debug.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
}
|
||||
@@ -0,0 +1,43 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2013
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
/* AS3722-PMIC-specific early init regs */
|
||||
|
||||
#define AS3722_I2C_ADDR 0x80
|
||||
|
||||
#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
|
||||
#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
|
||||
#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
|
||||
#define AS3722_SDCONTROL_REG 0x4D
|
||||
|
||||
#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
|
||||
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
|
||||
#define AS3722_LDCONTROL_REG 0x4E
|
||||
|
||||
#if defined(CONFIG_TARGET_VENICE2)
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
|
||||
#else /* TK1 or Nyan-Big */
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
|
||||
#endif
|
||||
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
|
||||
|
||||
#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_CEI_TK1_SOM)
|
||||
#define AS3722_SD1VOLTAGE_DATA (0x2800 | AS3722_SD1VOLTAGE_REG)
|
||||
#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
|
||||
#endif
|
||||
|
||||
#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
|
||||
#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
|
||||
|
||||
#define I2C_SEND_2_BYTES 0x0A02
|
||||
|
||||
void pmic_enable_cpu_vdd(void);
|
||||
@@ -0,0 +1,305 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
*
|
||||
* To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
* https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
* Run "board-to-uboot.py venice2".
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_VENICE2_H_
|
||||
#define _PINMUX_CONFIG_VENICE2_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config venice2_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 0, IN),
|
||||
GPIO_INIT(C, 7, IN),
|
||||
GPIO_INIT(G, 0, IN),
|
||||
GPIO_INIT(G, 1, IN),
|
||||
GPIO_INIT(G, 2, IN),
|
||||
GPIO_INIT(G, 3, IN),
|
||||
GPIO_INIT(H, 2, IN),
|
||||
GPIO_INIT(H, 4, IN),
|
||||
GPIO_INIT(H, 5, OUT0),
|
||||
GPIO_INIT(H, 6, IN),
|
||||
GPIO_INIT(H, 7, OUT1),
|
||||
GPIO_INIT(I, 0, IN),
|
||||
GPIO_INIT(I, 1, IN),
|
||||
GPIO_INIT(I, 2, OUT0),
|
||||
GPIO_INIT(I, 4, OUT0),
|
||||
GPIO_INIT(I, 5, OUT1),
|
||||
GPIO_INIT(I, 6, IN),
|
||||
GPIO_INIT(J, 0, IN),
|
||||
GPIO_INIT(J, 7, IN),
|
||||
GPIO_INIT(K, 0, IN),
|
||||
GPIO_INIT(K, 1, OUT0),
|
||||
GPIO_INIT(K, 2, IN),
|
||||
GPIO_INIT(K, 3, IN),
|
||||
GPIO_INIT(K, 4, OUT0),
|
||||
GPIO_INIT(K, 6, OUT0),
|
||||
GPIO_INIT(K, 7, IN),
|
||||
GPIO_INIT(N, 7, IN),
|
||||
GPIO_INIT(O, 2, IN),
|
||||
GPIO_INIT(O, 5, IN),
|
||||
GPIO_INIT(O, 6, OUT0),
|
||||
GPIO_INIT(O, 7, IN),
|
||||
GPIO_INIT(P, 2, OUT0),
|
||||
GPIO_INIT(Q, 0, IN),
|
||||
GPIO_INIT(Q, 2, IN),
|
||||
GPIO_INIT(Q, 3, IN),
|
||||
GPIO_INIT(Q, 6, IN),
|
||||
GPIO_INIT(Q, 7, IN),
|
||||
GPIO_INIT(R, 0, OUT0),
|
||||
GPIO_INIT(R, 1, IN),
|
||||
GPIO_INIT(R, 4, IN),
|
||||
GPIO_INIT(S, 0, IN),
|
||||
GPIO_INIT(S, 3, OUT0),
|
||||
GPIO_INIT(S, 4, OUT0),
|
||||
GPIO_INIT(S, 7, IN),
|
||||
GPIO_INIT(T, 1, IN),
|
||||
GPIO_INIT(U, 4, IN),
|
||||
GPIO_INIT(U, 5, IN),
|
||||
GPIO_INIT(U, 6, IN),
|
||||
GPIO_INIT(V, 0, IN),
|
||||
GPIO_INIT(V, 1, IN),
|
||||
GPIO_INIT(W, 3, IN),
|
||||
GPIO_INIT(X, 1, IN),
|
||||
GPIO_INIT(X, 3, IN),
|
||||
GPIO_INIT(X, 4, IN),
|
||||
GPIO_INIT(X, 7, OUT0),
|
||||
GPIO_INIT(CC, 5, OUT0),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config venice2_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, rcv_sel */
|
||||
PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RXD_PC3, IRDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH0, PWM0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA1_PO2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA6_PO7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW7_PR7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW8_PS0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU1, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU3, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PX3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config venice2_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_VENICE2_H */
|
||||
@@ -0,0 +1,28 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013-2014
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include "pinmux-config-venice2.h"
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_set_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(venice2_gpio_inits,
|
||||
ARRAY_SIZE(venice2_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(venice2_pingrps,
|
||||
ARRAY_SIZE(venice2_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(venice2_drvgrps,
|
||||
ARRAY_SIZE(venice2_drvgrps));
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_VENTANA
|
||||
|
||||
config SYS_BOARD
|
||||
default "ventana"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "ventana"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,7 @@
|
||||
VENTANA BOARD
|
||||
M: Tom Warren <twarren@nvidia.com>
|
||||
M: Stephen Warren <swarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/ventana/
|
||||
F: include/configs/ventana.h
|
||||
F: configs/ventana_defconfig
|
||||
@@ -0,0 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2010,2011
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
|
||||
obj-y = ../seaboard/seaboard.o
|
||||
Reference in New Issue
Block a user