GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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if TARGET_DURIAN
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config SYS_BOARD
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default "durian"
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config SYS_VENDOR
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default "phytium"
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config SYS_CONFIG_NAME
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default "durian"
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endif
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DURIAN BOARD
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M: liuhao <liuhao@phytium.com.cn>
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M: shuyiqi <shuyiqi@phytium.com.cn>
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S: Maintained
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F: board/phytium/durian/*
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F: include/configs/durian.h
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F: configs/durian_defconfig
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2019
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# shuyiqi <shuyiqi@phytium.com.cn>
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# liuhao <liuhao@phytium.com.cn>
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#
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obj-y += durian.o
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Here is the step-by-step to boot U-Boot on phytium durian board.
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Compile U-Boot
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==============
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> make durian_defconfig
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> make
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Get the prebuild binary about BPF
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=================================
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> cd ../
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> git clone https://github.com/phytium-durian/bpf.git
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Package the image
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=================
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> cd bpf
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> cp ../u-boot/u-boot.bin ./
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> ./dopack
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The fip-all.bin is the final image.
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Flash the image into the spi nor-flash
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======================================
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Any spi nor-flash and appropriate tool can be used to flash.
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For example, we choose the S25FL256 chip that produced from
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SPANSION company and EZP_XPro V1.2.
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Reset the board, you can get U-Boot log message from boot console:
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Power on...
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Start pcie setup!
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End pcie setup!
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Start ddr setup!
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End ddr setup!
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Jump to entrypoint: 0x500000
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U-Boot 2019.10-00594-g9ccc1b17ea-dirty (Oct 18 2019 - 00:17:09 +0800)
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DRAM: 1.9 GiB
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In: uart@28001000
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Out: uart@28001000
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Err: uart@28001000
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scanning bus for devices...
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Target spinup took 0 ms.
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SATA link 1 timeout.
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SATA link 2 timeout.
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SATA link 3 timeout.
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AHCI 0001.0000 32 slots 4 ports 6 Gbps 0xf impl SATA mode
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flags: 64bit ncq led only pmp fbss pio slum part sxs
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Device 0: (0:0) Vendor: ATA Prod.: ST1000DM010-2EP1 Rev: CC43
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Type: Hard Disk
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Capacity: 953869.7 MB = 931.5 GB (1953525168 x 512)
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SATA link 0 timeout.
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SATA link 1 timeout.
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SATA link 2 timeout.
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SATA link 3 timeout.
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AHCI 0001.0000 32 slots 4 ports 6 Gbps 0xf impl SATA mode
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flags: 64bit ncq led only pmp fbss pio slum part sxs
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Hit any key to stop autoboot: 0
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durian#
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2019
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* Phytium Technology Ltd <www.phytium.com>
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* shuyiqi <shuyiqi@phytium.com.cn>
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*/
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#ifndef _FT_DURIAN_H
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#define _FT_DURIAN_H
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/* FLUSH L3 CASHE */
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#define HNF_COUNT 0x8
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#define HNF_PSTATE_REQ (HNF_BASE + 0x10)
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#define HNF_PSTATE_STAT (HNF_BASE + 0x18)
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#define HNF_PSTATE_OFF 0x0
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#define HNF_PSTATE_SFONLY 0x1
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#define HNF_PSTATE_HALF 0x2
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#define HNF_PSTATE_FULL 0x3
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#define HNF_STRIDE 0x10000
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#define HNF_BASE (unsigned long)(0x3A200000)
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#endif /* _FT_DURIAN_H */
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@@ -0,0 +1,110 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019
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* shuyiqi <shuyiqi@phytium.com.cn>
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* liuhao <liuhao@phytium.com.cn>
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*/
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#include <common.h>
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#include <asm/armv8/mmu.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <linux/arm-smccc.h>
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#include <linux/kernel.h>
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#include <scsi.h>
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#include "cpu.h"
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->mem_clk = 0;
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
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debug("reset cpu error, %lx\n", res.a0);
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}
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static struct mm_region durian_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN |
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PTE_BLOCK_UXN
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},
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{
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.virt = (u64)PHYS_SDRAM_1,
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.phys = (u64)PHYS_SDRAM_1,
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.size = (u64)PHYS_SDRAM_1_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_NS |
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PTE_BLOCK_INNER_SHARE
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},
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{
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0,
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}
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};
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struct mm_region *mem_map = durian_mem_map;
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int print_cpuinfo(void)
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{
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printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk);
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return 0;
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}
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int __asm_flush_l3_dcache(void)
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{
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int i, pstate;
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for (i = 0; i < HNF_COUNT; i++)
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writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
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for (i = 0; i < HNF_COUNT; i++) {
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do {
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pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
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} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
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}
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for (i = 0; i < HNF_COUNT; i++)
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writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
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return 0;
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}
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int last_stage_init(void)
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{
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int ret;
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/* pci e */
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pci_init();
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/* scsi scan */
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ret = scsi_scan(true);
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if (ret) {
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printf("scsi scan failed\n");
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return CMD_RET_FAILURE;
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}
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return ret;
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}
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