GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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if TARGET_R2DPLUS
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config SYS_BOARD
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default "r2dplus"
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config SYS_VENDOR
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default "renesas"
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config SYS_CONFIG_NAME
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default "r2dplus"
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endif
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R2DPLUS BOARD
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M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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S: Maintained
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F: board/renesas/r2dplus/
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F: include/configs/r2dplus.h
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F: configs/r2dplus_defconfig
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2007,2008
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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obj-y := r2dplus.o
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extra-y += lowlevel_init.o
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/*
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* modified from SH-IPL+g (init-r0p751rlc0011rl.S)
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* Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
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* Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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write32 CCR_A, CCR_D_D
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write32 MMUCR_A, MMUCR_D
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write32 BCR1_A, BCR1_D
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write16 BCR2_A, BCR2_D
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write16 BCR3_A, BCR3_D
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write32 BCR4_A, BCR4_D
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write32 WCR1_A, WCR1_D
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write32 WCR2_A, WCR2_D
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write32 WCR3_A, WCR3_D
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write16 PCR_A, PCR_D
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write16 LED_A, LED_D
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write32 MCR_A, MCR_D1
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write16 RTCNT_A, RTCNT_D
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write16 RTCOR_A, RTCOR_D
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write16 RFCR_A, RFCR_D
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write16 RTCSR_A, RTCSR_D
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write8 SDMR3_A, SDMR3_D0
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/* Wait DRAM refresh 30 times */
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mov.l RFCR_A, r1
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mov #30, r3
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1:
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mov.w @r1, r0
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extu.w r0, r2
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cmp/hi r3, r2
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bf 1b
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write32 MCR_A, MCR_D2
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write8 SDMR3_A, SDMR3_D1
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write32 IRLMASK_A, IRLMASK_D
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write32 CCR_A, CCR_D_E
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rts
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nop
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.align 2
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CCR_A: .long CCR /* Cache Control Register */
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CCR_D_D: .long 0x0808 /* Flush the cache, disable */
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CCR_D_E: .long 0x8000090B
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FRQCR_A: .long FRQCR /* FRQCR Address */
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FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
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BCR1_A: .long BCR1 /* BCR1 Address */
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BCR1_D: .long 0x00180008
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BCR2_A: .long BCR2 /* BCR2 Address */
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BCR2_D: .long 0xabe8
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BCR3_A: .long BCR3 /* BCR3 Address */
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BCR3_D: .long 0x0000
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BCR4_A: .long BCR4 /* BCR4 Address */
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BCR4_D: .long 0x00000010
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WCR1_A: .long WCR1 /* WCR1 Address */
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WCR1_D: .long 0x33343333
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WCR2_A: .long WCR2 /* WCR2 Address */
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WCR2_D: .long 0xcff86fbf
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WCR3_A: .long WCR3 /* WCR3 Address */
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WCR3_D: .long 0x07777707
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LED_A: .long 0x04000036 /* LED Address */
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LED_D: .long 0xFF /* LED Data */
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RTCNT_A: .long RTCNT /* RTCNT Address */
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RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
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.align 2
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RTCOR_A: .long RTCOR /* RTCOR Address */
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RTCOR_D: .word 0xA534 /* RTCOR Write Code */
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.align 2
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RTCSR_A: .long RTCSR /* RTCSR Address */
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RTCSR_D: .word 0xA510 /* RTCSR Write Code */
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.align 2
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SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
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SDMR3_D0: .long 0x55
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SDMR3_D1: .long 0x00
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MCR_A: .long MCR /* MCR Address */
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MCR_D1: .long 0x081901F4 /* MRSET:'0' */
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MCR_D2: .long 0x481901F4 /* MRSET:'1' */
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RFCR_A: .long RFCR /* RFCR Address */
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RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
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PCR_A: .long PCR /* PCR Address */
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PCR_D: .long 0x0000
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MMUCR_A: .long MMUCR /* MMUCCR Address */
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MMUCR_D: .long 0x00000000 /* MMUCCR Data */
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IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */
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IRLMASK_D: .long 0x00000000 /* IRLMASK Data */
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@@ -0,0 +1,51 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2007,2008
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*/
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#include <common.h>
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#include <ide.h>
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#include <init.h>
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#include <netdev.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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int checkboard(void)
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{
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puts("BOARD: Renesas Solutions R2D Plus\n");
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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return 0;
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}
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#define FPGA_BASE 0xA4000000
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#define FPGA_CFCTL (FPGA_BASE + 0x04)
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#define CFCTL_EN (0x432)
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#define FPGA_CFPOW (FPGA_BASE + 0x06)
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#define CFPOW_ON (0x02)
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#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
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#define CFCDINTCLR_EN (0x01)
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void ide_set_reset(int idereset)
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{
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/* if reset = 1 IDE reset will be asserted */
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if (idereset) {
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outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */
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outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
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outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
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}
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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