GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_STOUT
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config SYS_BOARD
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default "stout"
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config SYS_VENDOR
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default "renesas"
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config SYS_CONFIG_NAME
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default "stout"
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endif
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@@ -0,0 +1,6 @@
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STOUT BOARD
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M: Cogent Embedded, Inc. <source@cogentembedded.com>
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S: Maintained
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F: board/renesas/stout/
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F: include/configs/stout.h
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F: configs/stout_defconfig
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@@ -0,0 +1,15 @@
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#
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# board/renesas/stout/Makefile
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#
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# Copyright (C) 2015 Renesas Electronics Europe GmbH
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# Copyright (C) 2015 Renesas Electronics Corporation
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# Copyright (C) 2015 Cogent Embedded, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0
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#
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ifdef CONFIG_SPL_BUILD
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obj-y := stout_spl.o
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else
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obj-y := stout.o cpld.o qos.o
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endif
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@@ -0,0 +1,166 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Stout board CPLD access support
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*
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* Copyright (C) 2015 Renesas Electronics Europe GmbH
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* Copyright (C) 2015 Renesas Electronics Corporation
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* Copyright (C) 2015 Cogent Embedded, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include "cpld.h"
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#define SCLK (92 + 24)
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#define SSTBZ (92 + 25)
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#define MOSI (92 + 26)
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#define MISO (92 + 27)
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#define CPLD_ADDR_MODE 0x00 /* RW */
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#define CPLD_ADDR_MUX 0x01 /* RW */
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#define CPLD_ADDR_HDMI 0x02 /* RW */
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#define CPLD_ADDR_DIPSW 0x08 /* R */
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#define CPLD_ADDR_RESET 0x80 /* RW */
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#define CPLD_ADDR_VERSION 0xFF /* R */
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static u32 cpld_read(u8 addr)
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{
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int i;
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u32 data = 0;
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for (i = 0; i < 8; i++) {
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gpio_set_value(MOSI, addr & 0x80); /* MSB first */
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gpio_set_value(SCLK, 1);
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addr <<= 1;
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gpio_set_value(SCLK, 0);
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}
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gpio_set_value(MOSI, 0); /* READ */
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gpio_set_value(SSTBZ, 0);
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gpio_set_value(SCLK, 1);
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gpio_set_value(SCLK, 0);
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gpio_set_value(SSTBZ, 1);
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for (i = 0; i < 32; i++) {
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gpio_set_value(SCLK, 1);
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data <<= 1;
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data |= gpio_get_value(MISO); /* MSB first */
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gpio_set_value(SCLK, 0);
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}
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return data;
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}
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static void cpld_write(u8 addr, u32 data)
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{
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int i;
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for (i = 0; i < 32; i++) {
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gpio_set_value(MOSI, data & (1 << 31)); /* MSB first */
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gpio_set_value(SCLK, 1);
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data <<= 1;
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gpio_set_value(SCLK, 0);
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}
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for (i = 0; i < 8; i++) {
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gpio_set_value(MOSI, addr & 0x80); /* MSB first */
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gpio_set_value(SCLK, 1);
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addr <<= 1;
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gpio_set_value(SCLK, 0);
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}
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gpio_set_value(MOSI, 1); /* WRITE */
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gpio_set_value(SSTBZ, 0);
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gpio_set_value(SCLK, 1);
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gpio_set_value(SCLK, 0);
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gpio_set_value(SSTBZ, 1);
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}
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/* LSI pin pull-up control */
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#define PUPR3 0xe606010C
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#define PUPR3_SD3_DAT1 (1 << 27)
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void cpld_init(void)
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{
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u32 val;
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/* PULL-UP on MISO line */
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val = readl(PUPR3);
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val |= PUPR3_SD3_DAT1;
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writel(val, PUPR3);
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gpio_request(SCLK, "SCLK");
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gpio_request(SSTBZ, "SSTBZ");
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gpio_request(MOSI, "MOSI");
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gpio_request(MISO, "MISO");
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gpio_direction_output(SCLK, 0);
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gpio_direction_output(SSTBZ, 1);
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gpio_direction_output(MOSI, 0);
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gpio_direction_input(MISO);
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/* dummy read */
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cpld_read(CPLD_ADDR_VERSION);
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printf("CPLD version: 0x%08x\n",
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cpld_read(CPLD_ADDR_VERSION));
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printf("H2 Mode setting (MD0..28): 0x%08x\n",
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cpld_read(CPLD_ADDR_MODE));
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printf("Multiplexer settings: 0x%08x\n",
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cpld_read(CPLD_ADDR_MUX));
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printf("HDMI setting: 0x%08x\n",
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cpld_read(CPLD_ADDR_HDMI));
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printf("DIPSW (SW3): 0x%08x\n",
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cpld_read(CPLD_ADDR_DIPSW));
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#ifdef CONFIG_SH_SDHI
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/* switch MUX to SD0 */
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val = cpld_read(CPLD_ADDR_MUX);
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val &= ~MUX_MSK_SD0;
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val |= MUX_VAL_SD0;
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cpld_write(CPLD_ADDR_MUX, val);
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#endif
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}
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static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 addr, val;
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if (argc < 3)
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return CMD_RET_USAGE;
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addr = simple_strtoul(argv[2], NULL, 16);
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if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
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addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_HDMI ||
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addr == CPLD_ADDR_DIPSW || addr == CPLD_ADDR_RESET)) {
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printf("cpld invalid addr\n");
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return CMD_RET_USAGE;
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}
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if (argc == 3 && strcmp(argv[1], "read") == 0) {
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printf("0x%x\n", cpld_read(addr));
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} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
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val = simple_strtoul(argv[3], NULL, 16);
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if (addr == CPLD_ADDR_MUX) {
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/* never mask SCIFA0 console */
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val &= ~MUX_MSK_SCIFA0_USB;
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val |= MUX_VAL_SCIFA0_USB;
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}
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cpld_write(addr, val);
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}
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return 0;
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}
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U_BOOT_CMD(
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cpld, 4, 1, do_cpld,
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"CPLD access",
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"read addr\n"
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"cpld write addr val\n"
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);
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void reset_cpu(ulong addr)
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{
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cpld_write(CPLD_ADDR_RESET, 1);
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}
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@@ -0,0 +1,182 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Stout board CPLD definition
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*
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* Copyright (C) 2015 Renesas Electronics Europe GmbH
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* Copyright (C) 2015 Renesas Electronics Corporation
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* Copyright (C) 2015 Cogent Embedded, Inc.
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*/
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#ifndef _CPLD_H_
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#define _CPLD_H_
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/* power-up behaviour */
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#define MODE_MSK_FREE_RUN 0x00000001
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#define MODE_VAL_FREE_RUN 0x00000000
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#define MODE_MSK_STEP_UP 0x00000001
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#define MODE_VAL_STEP_UP 0x00000000
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/* boot source */
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#define MODE_MSK_BOOT_SQPI_16KB_FAST 0x0000000E
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#define MODE_VAL_BOOT_SQPI_16KB_FAST 0x00000004
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#define MODE_MSK_BOOT_SQPI_16KB_SLOW 0x0000000E
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#define MODE_VAL_BOOT_SQPI_16KB_SLOW 0x00000008
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#define MODE_MSK_BOOT_SQPI_4KB_SLOW 0x0000000E
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#define MODE_VAL_BOOT_SQPI_4KB_SLOW 0x0000000C
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/* booting CPU */
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#define MODE_MSK_BOOT_CA15 0x000000C0
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#define MODE_VAL_BOOT_CA15 0x00000000
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#define MODE_MSK_BOOT_CA7 0x000000C0
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#define MODE_VAL_BOOT_CA7 0x00000040
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#define MODE_MSK_BOOT_SH4 0x000000C0
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#define MODE_VAL_BOOT_SH4 0x000000C0
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/* JTAG connection */
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#define MODE_MSK_JTAG_CORESIGHT 0xC0301C00
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#define MODE_VAL_JTAG_CORESIGHT 0x00200000
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#define MODE_MSK_JTAG_SH4 0xC0301C00
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#define MODE_VAL_JTAG_SH4 0x00300000
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/* DDR3 (PLL) speed */
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#define MODE_MSK_DDR3_1600 0x00080000
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#define MODE_VAL_DDR3_1600 0x00000000
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#define MODE_MSK_DDR3_1333 0x00080000
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#define MODE_VAL_DDR3_1333 0x00080000
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/* ComboPhy0 mode */
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#define MODE_MSK_PHY0_SATA0 0x01000000
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#define MODE_VAL_PHY0_SATA0 0x00000000
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#define MODE_MSK_PHY0_PCIE 0x01000000
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#define MODE_VAL_PHY0_PCIE 0x01000000
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/* ComboPhy1 mode */
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#define MODE_MSK_PHY1_SATA1 0x00800000
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#define MODE_VAL_PHY1_SATA1 0x00000000
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#define MODE_MSK_PHY1_USB3 0x00800000
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#define MODE_VAL_PHY1_USB3 0x00800000
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/*
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* Illegal multiplexer combinations.
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* MUX Conflicts
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* name with any one of
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* VIN0_BT656 VIN0_full, SD2
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* VIN0_full VIN0_BT656, SD2, AVB, VIN2_(all)
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* VIN1_BT656 VIN1_(others), SD0
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* VIN1_10bit VIN1_(others), SD0, VIN3_with*, I2C1
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* VIN1_12bit VIN1_(others), SD0, VIN3_with*, I2C1, SCIFA0_(all)
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* VIN2_BT656 VIN0_full, VIN2_(others), AVB,
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* VIN2_withSYNC VIN0_full, VIN2_(others), AVB, I2C1, SCIFA0_(all),
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* VIN3_with*
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* VIN2_withFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all)
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* VIN2_withSYNCandFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all), I2C1,
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* SCIFA0_(all), VIN3_with*
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* VIN3_BT656 VIN3_(others), IRQ3
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* VIN3_withFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC,
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* VIN2_withSYNCandFIELD, VIN1_10bit
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* VIN3_withSYNCandFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC,
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* VIN2_withSYNCandFIELD, VIN1_10bit, I2C1
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* AVB VIN0_full, VIN2_(all)
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* QSPI_ONBOARD VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_COMEXPRESS
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* QSPI_COMEXPRESS VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_ONBOARD
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* I2C1 VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
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* VIN3_withSYNCandFIELD
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* IRQ3 VIN3_(all)
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* SCIFA0_USB VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
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* SCIFA0_COMEXPRESS
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* SCIFA0_COMEXPRESS VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
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* SCIFA0_USB
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* SCIFA2 PWM210
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* ETH_ONBOARD ETH_COMEXPRESS
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* ETH_COMEXPRESS ETH_ONBOARD
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* SD0 VIN1_(all)
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* SD2 VIN0_(all)
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* PWM210 SCIFA2
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*/
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/* connected to COM Express connector and CN6 for camera, BT656 only */
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#define MUX_MSK_VIN0_BT656 0x00001001
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#define MUX_VAL_VIN0_BT656 0x00000000
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/* connected to COM Express connector and CN6 for camera, all modes */
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#define MUX_MSK_VIN0_full 0x00001007
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#define MUX_VAL_VIN0_full 0x00000002
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/* connected to COM Express connector, BT656 only */
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#define MUX_MSK_VIN1_BT656 0x00000801
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#define MUX_VAL_VIN1_BT656 0x00000800
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/* connected to COM Express connector, all 10-bit modes */
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#define MUX_MSK_VIN1_10bit 0x00000821
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#define MUX_VAL_VIN1_10bit 0x00000800
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/* connected to COM Express connector, all 12-bit modes */
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#define MUX_MSK_VIN1_12bit 0x000008A1
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#define MUX_VAL_VIN1_12bit 0x00000880
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/* connected to COM Express connector, BT656 only */
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#define MUX_MSK_VIN2_BT656 0x00000007
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#define MUX_VAL_VIN2_BT656 0x00000006
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/* connected to COM Express connector, modes with sync signals */
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#define MUX_MSK_VIN2_withSYNC 0x000000A7
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#define MUX_VAL_VIN2_withSYNC 0x00000086
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/* connected to COM Express connector, modes with field, clken signals */
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#define MUX_MSK_VIN2_withFIELD 0x0000000F
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#define MUX_VAL_VIN2_withFIELD 0x0000000E
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/* connected to COM Express connector, modes with sync, field, clken signals */
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#define MUX_MSK_VIN2_withSYNCandFIELD 0x000000AF
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#define MUX_VAL_VIN2_withSYNCandFIELD 0x0000008E
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/* connected to COM Express connector, BT656 only */
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#define MUX_MSK_VIN3_BT656 0x00000101
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#define MUX_VAL_VIN3_BT656 0x00000100
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/* connected to COM Express connector, modes with field, clken signals */
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#define MUX_MSK_VIN3_withFIELD 0x00000121
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#define MUX_VAL_VIN3_withFIELD 0x00000120
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/* connected to COM Express connector, modes with sync, field, clken signals */
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#define MUX_MSK_VIN3_withSYNCandFIELD 0x00000161
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#define MUX_VAL_VIN3_withSYNCandFIELD 0x00000120
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/* connected to COM Express connector (RGMII) */
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#define MUX_MSK_AVB 0x00000003
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#define MUX_VAL_AVB 0x00000000
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/* connected to on-board QSPI flash */
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#define MUX_MSK_QSPI_ONBOARD 0x00000019
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#define MUX_VAL_QSPI_ONBOARD 0x00000000
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/* connected to COM Express connector */
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#define MUX_MSK_QSPI_COMEXPRESS 0x00000019
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#define MUX_VAL_QSPI_COMEXPRESS 0x00000010
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/* connected to COM Express connector and PMIC */
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#define MUX_MSK_I2C1 0x00000061
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#define MUX_VAL_I2C1 0x00000060
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/* connected to HDMI driver */
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#define MUX_MSK_IRQ3 0x00000101
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#define MUX_VAL_IRQ3 0x00000000
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/* connected to USB/FTDI */
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#define MUX_MSK_SCIFA0_USB 0x00004081
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#define MUX_VAL_SCIFA0_USB 0x00004000
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/* connected to COM Express connector */
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#define MUX_MSK_SCIFA0_COMEXPRESS 0x00004081
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#define MUX_VAL_SCIFA0_COMEXPRESS 0x00000000
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/* connected to COM Express connector */
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#define MUX_MSK_SCIFA2 0x00002001
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#define MUX_VAL_SCIFA2 0x00000000
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/* connected to on-board 10/100 Phy */
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#define MUX_MSK_ETH_ONBOARD 0x00000600
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#define MUX_VAL_ETH_ONBOARD 0x00000000
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/* connected to COM Express connector (RMII) */
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#define MUX_MSK_ETH_COMEXPRESS 0x00000600
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||||
#define MUX_VAL_ETH_COMEXPRESS 0x00000400
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/* connected to on-board MicroSD slot */
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#define MUX_MSK_SD0 0x00000801
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#define MUX_VAL_SD0 0x00000000
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/* connected to COM Express connector */
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#define MUX_MSK_SD2 0x00001001
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#define MUX_VAL_SD2 0x00001000
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/* connected to COM Express connector */
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#define MUX_MSK_PWM210 0x00002001
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||||
#define MUX_VAL_PWM210 0x00002000
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||||
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||||
#define HDMI_MSK 0x07
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#define HDMI_OFF 0x00
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#define HDMI_ONBOARD 0x07
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#define HDMI_COMEXPRESS 0x05
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#define HDMI_ONBOARD_NODDC 0x03
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#define HDMI_COMEXPRESS_NODDC 0x01
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||||
void cpld_init(void);
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||||
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#endif /* _CPLD_H_ */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
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||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Europe GmbH
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation
|
||||
* Copyright (C) 2015 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __QOS_H__
|
||||
#define __QOS_H__
|
||||
|
||||
void qos_init(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,141 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* board/renesas/stout/stout.c
|
||||
* This file is Stout board support.
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Europe GmbH
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation
|
||||
* Copyright (C) 2015 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <malloc.h>
|
||||
#include <netdev.h>
|
||||
#include <dm.h>
|
||||
#include <dm/platform_data/serial_sh.h>
|
||||
#include <env_internal.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/rmobile.h>
|
||||
#include <asm/arch/rcar-mstp.h>
|
||||
#include <asm/arch/mmc.h>
|
||||
#include <asm/arch/sh_sdhi.h>
|
||||
#include <miiphy.h>
|
||||
#include <i2c.h>
|
||||
#include <mmc.h>
|
||||
#include "qos.h"
|
||||
#include "cpld.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define CLK2MHZ(clk) (clk / 1000 / 1000)
|
||||
void s_init(void)
|
||||
{
|
||||
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
|
||||
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
|
||||
|
||||
/* Watchdog init */
|
||||
writel(0xA5A5A500, &rwdt->rwtcsra);
|
||||
writel(0xA5A5A500, &swdt->swtcsra);
|
||||
|
||||
/* CPU frequency setting. Set to 1.4GHz */
|
||||
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
|
||||
u32 stat = 0;
|
||||
u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
|
||||
<< PLL0_STC_BIT;
|
||||
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
|
||||
|
||||
do {
|
||||
stat = readl(PLLECR) & PLL0ST;
|
||||
} while (stat == 0x0);
|
||||
}
|
||||
|
||||
/* QoS(Quality-of-Service) Init */
|
||||
qos_init();
|
||||
}
|
||||
|
||||
#define TMU0_MSTP125 BIT(25)
|
||||
|
||||
#define SD2CKCR 0xE6150078
|
||||
#define SD2_97500KHZ 0x7
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* TMU0 */
|
||||
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
||||
|
||||
/*
|
||||
* SD0 clock is set to 97.5MHz by default.
|
||||
* Set SD2 to the 97.5MHz as well.
|
||||
*/
|
||||
writel(SD2_97500KHZ, SD2CKCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define ETHERNET_PHY_RESET 123 /* GPIO 3 31 */
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
cpld_init();
|
||||
|
||||
/* Force ethernet PHY out of reset */
|
||||
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
|
||||
gpio_direction_output(ETHERNET_PHY_RESET, 0);
|
||||
mdelay(20);
|
||||
gpio_direction_output(ETHERNET_PHY_RESET, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
if (fdtdec_setup_mem_size_base() != 0)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
fdtdec_setup_memory_banksize();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Stout has KSZ8041NL/RNL */
|
||||
#define PHY_CONTROL1 0x1E
|
||||
#define PHY_LED_MODE 0xC000
|
||||
#define PHY_LED_MODE_ACK 0x4000
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
|
||||
ret &= ~PHY_LED_MODE;
|
||||
ret |= PHY_LED_MODE_ACK;
|
||||
ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
enum env_location env_get_location(enum env_operation op, int prio)
|
||||
{
|
||||
const u32 load_magic = 0xb33fc0de;
|
||||
|
||||
/* Block environment access if loaded using JTAG */
|
||||
if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
|
||||
(op != ENVOP_INIT))
|
||||
return ENVL_UNKNOWN;
|
||||
|
||||
if (prio)
|
||||
return ENVL_UNKNOWN;
|
||||
|
||||
return ENVL_SPI_FLASH;
|
||||
}
|
||||
@@ -0,0 +1,476 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* board/renesas/stout/stout_spl.c
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <dm/platform_data/serial_sh.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/rmobile.h>
|
||||
#include <asm/arch/rcar-mstp.h>
|
||||
|
||||
#include <spl.h>
|
||||
|
||||
#define TMU0_MSTP125 BIT(25)
|
||||
#define SCIFA0_MSTP204 BIT(4)
|
||||
#define QSPI_MSTP917 BIT(17)
|
||||
|
||||
#define SD2CKCR 0xE615026C
|
||||
#define SD_97500KHZ 0x7
|
||||
|
||||
struct reg_config {
|
||||
u16 off;
|
||||
u32 val;
|
||||
};
|
||||
|
||||
static void dbsc_wait(u16 reg)
|
||||
{
|
||||
static const u32 dbsc3_0_base = DBSC3_0_BASE;
|
||||
static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
|
||||
|
||||
while (!(readl(dbsc3_0_base + reg) & BIT(0)))
|
||||
;
|
||||
|
||||
while (!(readl(dbsc3_1_base + reg) & BIT(0)))
|
||||
;
|
||||
}
|
||||
|
||||
static void spl_init_sys(void)
|
||||
{
|
||||
u32 r0 = 0;
|
||||
|
||||
writel(0xa5a5a500, 0xe6020004);
|
||||
writel(0xa5a5a500, 0xe6030004);
|
||||
|
||||
asm volatile(
|
||||
/* ICIALLU - Invalidate I$ to PoU */
|
||||
"mcr 15, 0, %0, cr7, cr5, 0 \n"
|
||||
/* BPIALL - Invalidate branch predictors */
|
||||
"mcr 15, 0, %0, cr7, cr5, 6 \n"
|
||||
/* Set SCTLR[IZ] */
|
||||
"mrc 15, 0, %0, cr1, cr0, 0 \n"
|
||||
"orr %0, #0x1800 \n"
|
||||
"mcr 15, 0, %0, cr1, cr0, 0 \n"
|
||||
"isb sy \n"
|
||||
:"=r"(r0));
|
||||
}
|
||||
|
||||
static void spl_init_pfc(void)
|
||||
{
|
||||
static const struct reg_config pfc_with_unlock[] = {
|
||||
{ 0x0090, 0x00140300 },
|
||||
{ 0x0094, 0x09500000 },
|
||||
{ 0x0098, 0xc0000084 },
|
||||
{ 0x0020, 0x01a33492 },
|
||||
{ 0x0024, 0x10000000 },
|
||||
{ 0x0028, 0x08449252 },
|
||||
{ 0x002c, 0x2925b322 },
|
||||
{ 0x0030, 0x0c311249 },
|
||||
{ 0x0034, 0x10124000 },
|
||||
{ 0x0038, 0x00001295 },
|
||||
{ 0x003c, 0x50890000 },
|
||||
{ 0x0040, 0x0eaa56aa },
|
||||
{ 0x0044, 0x55550000 },
|
||||
{ 0x0048, 0x00000005 },
|
||||
{ 0x004c, 0x54800000 },
|
||||
{ 0x0050, 0x3736db55 },
|
||||
{ 0x0054, 0x29148da3 },
|
||||
{ 0x0058, 0x48c446e1 },
|
||||
{ 0x005c, 0x2a3a54dc },
|
||||
{ 0x0160, 0x00000023 },
|
||||
{ 0x0004, 0xfca0ffff },
|
||||
{ 0x0008, 0x3fbffbf0 },
|
||||
{ 0x000c, 0x3ffdffff },
|
||||
{ 0x0010, 0x00ffffff },
|
||||
{ 0x0014, 0xfc3ffff3 },
|
||||
{ 0x0018, 0xe4fdfff7 },
|
||||
};
|
||||
|
||||
static const struct reg_config pfc_without_unlock[] = {
|
||||
{ 0x0104, 0xffffbfff },
|
||||
{ 0x0108, 0xb1ffffe1 },
|
||||
{ 0x010c, 0xffffffff },
|
||||
{ 0x0110, 0xffffffff },
|
||||
{ 0x0114, 0xe047beab },
|
||||
{ 0x0118, 0x00000203 },
|
||||
};
|
||||
|
||||
static const u32 pfc_base = 0xe6060000;
|
||||
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
|
||||
writel(~pfc_with_unlock[i].val, pfc_base);
|
||||
writel(pfc_with_unlock[i].val,
|
||||
pfc_base | pfc_with_unlock[i].off);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
|
||||
writel(pfc_without_unlock[i].val,
|
||||
pfc_base | pfc_without_unlock[i].off);
|
||||
}
|
||||
|
||||
static void spl_init_gpio(void)
|
||||
{
|
||||
static const u16 gpio_offs[] = {
|
||||
0x1000, 0x3000, 0x4000, 0x5000
|
||||
};
|
||||
|
||||
static const struct reg_config gpio_set[] = {
|
||||
{ 0x4000, 0x00c00000 },
|
||||
{ 0x5000, 0x63020000 },
|
||||
};
|
||||
|
||||
static const struct reg_config gpio_clr[] = {
|
||||
{ 0x1000, 0x00000000 },
|
||||
{ 0x3000, 0x00000000 },
|
||||
{ 0x4000, 0x00c00000 },
|
||||
{ 0x5000, 0xe3020000 },
|
||||
};
|
||||
|
||||
static const u32 gpio_base = 0xe6050000;
|
||||
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
|
||||
writel(0, gpio_base | 0x20 | gpio_offs[i]);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
|
||||
writel(0, gpio_base | 0x00 | gpio_offs[i]);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
|
||||
writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
|
||||
writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
|
||||
}
|
||||
|
||||
static void spl_init_lbsc(void)
|
||||
{
|
||||
static const struct reg_config lbsc_config[] = {
|
||||
{ 0x00, 0x00000020 },
|
||||
{ 0x08, 0x00002020 },
|
||||
{ 0x30, 0x02150326 },
|
||||
{ 0x38, 0x077f077f },
|
||||
};
|
||||
|
||||
static const u16 lbsc_offs[] = {
|
||||
0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
|
||||
};
|
||||
|
||||
static const u32 lbsc_base = 0xfec00200;
|
||||
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
|
||||
writel(lbsc_config[i].val,
|
||||
lbsc_base | lbsc_config[i].off);
|
||||
writel(lbsc_config[i].val,
|
||||
lbsc_base | (lbsc_config[i].off + 4));
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
|
||||
writel(0, lbsc_base | lbsc_offs[i]);
|
||||
}
|
||||
|
||||
static void spl_init_dbsc(void)
|
||||
{
|
||||
static const struct reg_config dbsc_config1[] = {
|
||||
{ 0x0280, 0x0000a55a },
|
||||
{ 0x0018, 0x21000000 },
|
||||
{ 0x0018, 0x11000000 },
|
||||
{ 0x0018, 0x10000000 },
|
||||
{ 0x0290, 0x00000001 },
|
||||
{ 0x02a0, 0x80000000 },
|
||||
{ 0x0290, 0x00000004 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config2[] = {
|
||||
{ 0x0290, 0x00000006 },
|
||||
{ 0x02a0, 0x0001c000 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config3r0d0[] = {
|
||||
{ 0x0290, 0x0000000f },
|
||||
{ 0x02a0, 0x00181885 },
|
||||
{ 0x0290, 0x00000070 },
|
||||
{ 0x02a0, 0x7c000887 },
|
||||
{ 0x0290, 0x00000080 },
|
||||
{ 0x02a0, 0x7c000887 },
|
||||
{ 0x0290, 0x00000090 },
|
||||
{ 0x02a0, 0x7c000887 },
|
||||
{ 0x0290, 0x000000a0 },
|
||||
{ 0x02a0, 0x7c000887 },
|
||||
{ 0x0290, 0x000000b0 },
|
||||
{ 0x02a0, 0x7c000880 },
|
||||
{ 0x0290, 0x000000c0 },
|
||||
{ 0x02a0, 0x7c000880 },
|
||||
{ 0x0290, 0x000000d0 },
|
||||
{ 0x02a0, 0x7c000880 },
|
||||
{ 0x0290, 0x000000e0 },
|
||||
{ 0x02a0, 0x7c000880 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config3r0d1[] = {
|
||||
{ 0x0290, 0x0000000f },
|
||||
{ 0x02a0, 0x00181885 },
|
||||
{ 0x0290, 0x00000070 },
|
||||
{ 0x02a0, 0x7c000887 },
|
||||
{ 0x0290, 0x00000080 },
|
||||
{ 0x02a0, 0x7c000887 },
|
||||
{ 0x0290, 0x00000090 },
|
||||
{ 0x02a0, 0x7c000887 },
|
||||
{ 0x0290, 0x000000a0 },
|
||||
{ 0x02a0, 0x7c000887 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config3r2[] = {
|
||||
{ 0x0290, 0x0000000f },
|
||||
{ 0x02a0, 0x00181224 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config4[] = {
|
||||
{ 0x0290, 0x00000010 },
|
||||
{ 0x02a0, 0xf004649b },
|
||||
{ 0x0290, 0x00000061 },
|
||||
{ 0x02a0, 0x0000006d },
|
||||
{ 0x0290, 0x00000001 },
|
||||
{ 0x02a0, 0x00000073 },
|
||||
{ 0x0020, 0x00000007 },
|
||||
{ 0x0024, 0x0f030a02 },
|
||||
{ 0x0030, 0x00000001 },
|
||||
{ 0x00b0, 0x00000000 },
|
||||
{ 0x0040, 0x0000000b },
|
||||
{ 0x0044, 0x00000008 },
|
||||
{ 0x0048, 0x00000000 },
|
||||
{ 0x0050, 0x0000000b },
|
||||
{ 0x0054, 0x000c000b },
|
||||
{ 0x0058, 0x00000027 },
|
||||
{ 0x005c, 0x0000001c },
|
||||
{ 0x0060, 0x00000006 },
|
||||
{ 0x0064, 0x00000020 },
|
||||
{ 0x0068, 0x00000008 },
|
||||
{ 0x006c, 0x0000000c },
|
||||
{ 0x0070, 0x00000009 },
|
||||
{ 0x0074, 0x00000012 },
|
||||
{ 0x0078, 0x000000d0 },
|
||||
{ 0x007c, 0x00140005 },
|
||||
{ 0x0080, 0x00050004 },
|
||||
{ 0x0084, 0x70233005 },
|
||||
{ 0x0088, 0x000c0000 },
|
||||
{ 0x008c, 0x00000200 },
|
||||
{ 0x0090, 0x00000040 },
|
||||
{ 0x0100, 0x00000001 },
|
||||
{ 0x00c0, 0x00020001 },
|
||||
{ 0x00c8, 0x20042004 },
|
||||
{ 0x0380, 0x00020002 },
|
||||
{ 0x0390, 0x0000001f },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config5[] = {
|
||||
{ 0x0244, 0x00000011 },
|
||||
{ 0x0290, 0x00000003 },
|
||||
{ 0x02a0, 0x0300c4e1 },
|
||||
{ 0x0290, 0x00000023 },
|
||||
{ 0x02a0, 0x00fcdb60 },
|
||||
{ 0x0290, 0x00000011 },
|
||||
{ 0x02a0, 0x1000040b },
|
||||
{ 0x0290, 0x00000012 },
|
||||
{ 0x02a0, 0x9d9cbb66 },
|
||||
{ 0x0290, 0x00000013 },
|
||||
{ 0x02a0, 0x1a868400 },
|
||||
{ 0x0290, 0x00000014 },
|
||||
{ 0x02a0, 0x300214d8 },
|
||||
{ 0x0290, 0x00000015 },
|
||||
{ 0x02a0, 0x00000d70 },
|
||||
{ 0x0290, 0x00000016 },
|
||||
{ 0x02a0, 0x00000006 },
|
||||
{ 0x0290, 0x00000017 },
|
||||
{ 0x02a0, 0x00000018 },
|
||||
{ 0x0290, 0x0000001a },
|
||||
{ 0x02a0, 0x910035c7 },
|
||||
{ 0x0290, 0x00000004 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config6[] = {
|
||||
{ 0x0290, 0x00000001 },
|
||||
{ 0x02a0, 0x00000181 },
|
||||
{ 0x0018, 0x11000000 },
|
||||
{ 0x0290, 0x00000004 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config7[] = {
|
||||
{ 0x0290, 0x00000001 },
|
||||
{ 0x02a0, 0x0000fe01 },
|
||||
{ 0x0304, 0x00000000 },
|
||||
{ 0x00f4, 0x01004c20 },
|
||||
{ 0x00f8, 0x014000aa },
|
||||
{ 0x00e0, 0x00000140 },
|
||||
{ 0x00e4, 0x00081860 },
|
||||
{ 0x00e8, 0x00010000 },
|
||||
{ 0x0290, 0x00000004 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config8[] = {
|
||||
{ 0x0014, 0x00000001 },
|
||||
{ 0x0010, 0x00000001 },
|
||||
{ 0x0280, 0x00000000 },
|
||||
};
|
||||
|
||||
static const u32 dbsc3_0_base = DBSC3_0_BASE;
|
||||
static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
|
||||
static const u32 prr_base = 0xff000044;
|
||||
const u16 prr_rev = readl(prr_base) & 0x7fff;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
|
||||
writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
|
||||
writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
|
||||
}
|
||||
|
||||
dbsc_wait(0x2a0);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
|
||||
writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
|
||||
writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
|
||||
}
|
||||
|
||||
if (prr_rev == 0x4500) {
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
|
||||
writel(dbsc_config3r0d0[i].val,
|
||||
dbsc3_0_base | dbsc_config3r0d0[i].off);
|
||||
}
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
|
||||
writel(dbsc_config3r0d1[i].val,
|
||||
dbsc3_1_base | dbsc_config3r0d1[i].off);
|
||||
}
|
||||
} else if (prr_rev != 0x4510) {
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
|
||||
writel(dbsc_config3r2[i].val,
|
||||
dbsc3_0_base | dbsc_config3r2[i].off);
|
||||
writel(dbsc_config3r2[i].val,
|
||||
dbsc3_1_base | dbsc_config3r2[i].off);
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
|
||||
writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
|
||||
writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
|
||||
}
|
||||
|
||||
dbsc_wait(0x240);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
|
||||
writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
|
||||
writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
|
||||
}
|
||||
|
||||
dbsc_wait(0x2a0);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
|
||||
writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
|
||||
writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
|
||||
}
|
||||
|
||||
dbsc_wait(0x2a0);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
|
||||
writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
|
||||
writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
|
||||
}
|
||||
|
||||
dbsc_wait(0x2a0);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
|
||||
writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
|
||||
writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static void spl_init_qspi(void)
|
||||
{
|
||||
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
|
||||
|
||||
static const u32 qspi_base = 0xe6b10000;
|
||||
|
||||
writeb(0x08, qspi_base + 0x00);
|
||||
writeb(0x00, qspi_base + 0x01);
|
||||
writeb(0x06, qspi_base + 0x02);
|
||||
writeb(0x01, qspi_base + 0x0a);
|
||||
writeb(0x00, qspi_base + 0x0b);
|
||||
writeb(0x00, qspi_base + 0x0c);
|
||||
writeb(0x00, qspi_base + 0x0d);
|
||||
writeb(0x00, qspi_base + 0x0e);
|
||||
|
||||
writew(0xe080, qspi_base + 0x10);
|
||||
|
||||
writeb(0xc0, qspi_base + 0x18);
|
||||
writeb(0x00, qspi_base + 0x18);
|
||||
writeb(0x00, qspi_base + 0x08);
|
||||
writeb(0x48, qspi_base + 0x00);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
||||
mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
|
||||
|
||||
/*
|
||||
* SD0 clock is set to 97.5MHz by default.
|
||||
* Set SD2 to the 97.5MHz as well.
|
||||
*/
|
||||
writel(SD_97500KHZ, SD2CKCR);
|
||||
|
||||
spl_init_sys();
|
||||
spl_init_pfc();
|
||||
spl_init_gpio();
|
||||
spl_init_lbsc();
|
||||
spl_init_dbsc();
|
||||
spl_init_qspi();
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
}
|
||||
|
||||
void board_boot_order(u32 *spl_boot_list)
|
||||
{
|
||||
const u32 jtag_magic = 0x1337c0de;
|
||||
const u32 load_magic = 0xb33fc0de;
|
||||
|
||||
/*
|
||||
* If JTAG probe sets special word at 0xe6300020, then it must
|
||||
* put U-Boot into RAM and SPL will start it from RAM.
|
||||
*/
|
||||
if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
|
||||
printf("JTAG boot detected!\n");
|
||||
|
||||
while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
|
||||
;
|
||||
|
||||
spl_boot_list[0] = BOOT_DEVICE_RAM;
|
||||
spl_boot_list[1] = BOOT_DEVICE_NONE;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* Boot from SPI NOR with YMODEM UART fallback. */
|
||||
spl_boot_list[0] = BOOT_DEVICE_SPI;
|
||||
spl_boot_list[1] = BOOT_DEVICE_UART;
|
||||
spl_boot_list[2] = BOOT_DEVICE_NONE;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
Reference in New Issue
Block a user