GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_PM9261
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config SYS_BOARD
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default "pm9261"
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config SYS_VENDOR
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default "ronetix"
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config SYS_CONFIG_NAME
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default "pm9261"
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endif
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@@ -0,0 +1,6 @@
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PM9261 BOARD
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M: Ilko Iliev <iliev@ronetix.at>
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S: Maintained
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F: board/ronetix/pm9261/
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F: include/configs/pm9261.h
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F: configs/pm9261_defconfig
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@@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
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# Stelian Pop <stelian@popies.net>
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# Lead Tech Design <www.leadtechdesign.com>
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# Ilko Iliev <www.ronetix.at>
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obj-y += pm9261.o
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obj-$(CONFIG_RED_LED) += led.o
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@@ -0,0 +1,26 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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* Ilko Iliev <www.ronetix.at>
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*/
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#include <common.h>
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#include <status_led.h>
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#include <asm/gpio.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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void coloured_LED_init(void)
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{
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at91_periph_clk_enable(ATMEL_ID_PIOC);
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gpio_direction_output(CONFIG_RED_LED, 1);
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gpio_direction_output(CONFIG_GREEN_LED, 1);
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gpio_direction_output(CONFIG_YELLOW_LED, 1);
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gpio_set_value(CONFIG_RED_LED, 0);
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gpio_set_value(CONFIG_GREEN_LED, 1);
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gpio_set_value(CONFIG_YELLOW_LED, 1);
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}
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@@ -0,0 +1,184 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
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* Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*/
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#include <common.h>
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#include <vsprintf.h>
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#include <linux/sizes.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
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#include <net.h>
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#endif
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#include <netdev.h>
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#include <asm/mach-types.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_CMD_NAND
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static void pm9261_nand_hw_init(void)
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{
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unsigned long csa;
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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/* Enable CS3 */
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csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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at91_periph_clk_enable(ATMEL_ID_PIOA);
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at91_periph_clk_enable(ATMEL_ID_PIOC);
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/* Configure RDY/BSY */
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gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
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/* Enable NandFlash */
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gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
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at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
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}
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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static void pm9261_dm9000_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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/* Configure SMC CS2 for DM9000 */
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writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[2].setup);
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
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AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
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&smc->cs[2].pulse);
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writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
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&smc->cs[2].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
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AT91_SMC_MODE_TDF_CYCLE(1),
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&smc->cs[2].mode);
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/* Configure Interrupt pin as input, no pull-up */
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at91_periph_clk_enable(ATMEL_ID_PIOA);
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at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
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}
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#endif
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int board_early_init_f(void)
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{
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return 0;
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}
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int board_init(void)
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{
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/* arch number of PM9261-Board */
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gd->bd->bi_arch_number = MACH_TYPE_PM9261;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_CMD_NAND
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pm9261_nand_hw_init();
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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pm9261_dm9000_hw_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(bd_t *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
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PHYS_SDRAM_SIZE);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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#ifdef CONFIG_DRIVER_DM9000
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/*
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* Initialize ethernet HW addr prior to starting Linux,
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* needed for nfsroot
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*/
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eth_init();
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#endif
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}
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#endif
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard (void)
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{
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char buf[32];
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printf ("Board : Ronetix PM9261\n");
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printf ("Crystal frequency: %8s MHz\n",
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strmhz(buf, get_main_clk_rate()));
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printf ("CPU clock : %8s MHz\n",
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strmhz(buf, get_cpu_clk_rate()));
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printf ("Master clock : %8s MHz\n",
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strmhz(buf, get_mck_clk_rate()));
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return 0;
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}
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#endif
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@@ -0,0 +1,12 @@
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if TARGET_PM9263
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config SYS_BOARD
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default "pm9263"
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config SYS_VENDOR
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default "ronetix"
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config SYS_CONFIG_NAME
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default "pm9263"
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endif
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@@ -0,0 +1,6 @@
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PM9263 BOARD
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M: Ilko Iliev <iliev@ronetix.at>
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S: Maintained
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F: board/ronetix/pm9263/
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F: include/configs/pm9263.h
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F: configs/pm9263_defconfig
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@@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
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||||
# Stelian Pop <stelian@popies.net>
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# Lead Tech Design <www.leadtechdesign.com>
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# Ilko Iliev <www.ronetix.at>
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obj-y += pm9263.o
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obj-$(CONFIG_AT91_LED) += led.o
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@@ -0,0 +1,24 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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* Ilko Iliev <www.ronetix.at>
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||||
*/
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#include <common.h>
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#include <status_led.h>
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#include <asm/gpio.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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void coloured_LED_init(void)
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{
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at91_periph_clk_enable(ATMEL_ID_PIOB);
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gpio_direction_output(CONFIG_RED_LED, 1);
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gpio_direction_output(CONFIG_GREEN_LED, 1);
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gpio_set_value(CONFIG_RED_LED, 0);
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gpio_set_value(CONFIG_GREEN_LED, 1);
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}
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@@ -0,0 +1,302 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2008
|
||||
* Stelian Pop <stelian@popies.net>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
|
||||
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*/
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#include <common.h>
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#include <linux/sizes.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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#include <netdev.h>
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#include <asm/mach-types.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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||||
*/
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#ifdef CONFIG_CMD_NAND
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static void pm9263_nand_hw_init(void)
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{
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unsigned long csa;
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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/* Enable CS3 */
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csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa[0]);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
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/* Enable NandFlash */
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gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif
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#ifdef CONFIG_MACB
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static void pm9263_macb_hw_init(void)
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{
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||||
/*
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* PB27 enables the 50MHz oscillator for Ethernet PHY
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* 1 - enable
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||||
* 0 - disable
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||||
*/
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at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
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at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
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||||
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at91_periph_clk_enable(ATMEL_ID_EMAC);
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||||
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||||
/*
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||||
* Disable pull-up on:
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* RXDV (PC25) => PHY normal mode (not Test mode)
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* ERX0 (PE25) => PHY ADDR0
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||||
* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
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*
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||||
* PHY has internal pull-down
|
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*/
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||||
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at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
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at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
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at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
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/* Re-enable pull-up */
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at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
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at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
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at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
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at91_macb_hw_init();
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}
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||||
#endif
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||||
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#ifdef CONFIG_LCD
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||||
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||||
#ifdef CONFIG_LCD_IN_PSRAM
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#define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
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#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
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||||
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/* Initialize the PSRAM memory */
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static int pm9263_lcd_hw_psram_init(void)
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||||
{
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||||
unsigned long csa;
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
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||||
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
|
||||
|
||||
/* Enable CS3 3.3v, no pull-ups */
|
||||
csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
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||||
AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
|
||||
|
||||
writel(csa, &matrix->csa[1]);
|
||||
|
||||
/* Configure SMC1 CS0 for PSRAM - 16-bit */
|
||||
writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
|
||||
AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
|
||||
&smc->cs[0].setup);
|
||||
|
||||
writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
|
||||
AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
|
||||
&smc->cs[0].pulse);
|
||||
|
||||
writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
|
||||
&smc->cs[0].cycle);
|
||||
|
||||
writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
|
||||
&smc->cs[0].mode);
|
||||
|
||||
/* setup PB29 as output */
|
||||
at91_set_pio_output(PSRAM_CRE_PIN, 1);
|
||||
|
||||
at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
|
||||
|
||||
/* PSRAM: write BCR */
|
||||
readw(PSRAM_CTRL_REG);
|
||||
readw(PSRAM_CTRL_REG);
|
||||
writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
|
||||
writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
|
||||
|
||||
/* write RCR of the PSRAM */
|
||||
readw(PSRAM_CTRL_REG);
|
||||
readw(PSRAM_CTRL_REG);
|
||||
writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
|
||||
/* set RCR; 0x10-async mode,0x90-page mode */
|
||||
writew(0x90, PSRAM_CTRL_REG);
|
||||
|
||||
/*
|
||||
* test to see if the PSRAM is MT45W2M16A or MT45W2M16B
|
||||
* MT45W2M16B - CRE must be 0
|
||||
* MT45W2M16A - CRE must be 1
|
||||
*/
|
||||
writew(0x1234, PHYS_PSRAM);
|
||||
writew(0x5678, PHYS_PSRAM + 2);
|
||||
|
||||
/* test if the chip is MT45W2M16B */
|
||||
if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
|
||||
/* try with CRE=1 (MT45W2M16A) */
|
||||
at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
|
||||
|
||||
/* write RCR of the PSRAM */
|
||||
readw(PSRAM_CTRL_REG);
|
||||
readw(PSRAM_CTRL_REG);
|
||||
writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
|
||||
/* set RCR;0x10-async mode,0x90-page mode */
|
||||
writew(0x90, PSRAM_CTRL_REG);
|
||||
|
||||
|
||||
writew(0x1234, PHYS_PSRAM);
|
||||
writew(0x5678, PHYS_PSRAM+2);
|
||||
if ((readw(PHYS_PSRAM) != 0x1234)
|
||||
|| (readw(PHYS_PSRAM + 2) != 0x5678))
|
||||
return 1;
|
||||
|
||||
}
|
||||
|
||||
/* Bus matrix */
|
||||
writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
|
||||
writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void pm9263_lcd_hw_init(void)
|
||||
{
|
||||
/* Power Control */
|
||||
at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
|
||||
at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
|
||||
|
||||
#ifdef CONFIG_LCD_IN_PSRAM
|
||||
/* initialize te PSRAM */
|
||||
int stat = pm9263_lcd_hw_psram_init();
|
||||
|
||||
gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
|
||||
#else
|
||||
gd->fb_base = ATMEL_BASE_SRAM0;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif /* CONFIG_LCD */
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* arch number of AT91SAM9263EK-Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_PM9263;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
pm9263_nand_hw_init();
|
||||
#endif
|
||||
#ifdef CONFIG_MACB
|
||||
pm9263_macb_hw_init();
|
||||
#endif
|
||||
#ifdef CONFIG_USB_OHCI_NEW
|
||||
at91_uhp_hw_init();
|
||||
#endif
|
||||
#ifdef CONFIG_LCD
|
||||
pm9263_lcd_hw_init();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
|
||||
PHYS_SDRAM_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
void reset_phy(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_MACB
|
||||
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DISPLAY_BOARDINFO
|
||||
int checkboard (void)
|
||||
{
|
||||
char *ss;
|
||||
|
||||
printf ("Board : Ronetix PM9263\n");
|
||||
|
||||
switch (gd->fb_base) {
|
||||
case PHYS_PSRAM:
|
||||
ss = "(PSRAM)";
|
||||
break;
|
||||
|
||||
case ATMEL_BASE_SRAM0:
|
||||
ss = "(Internal SRAM)";
|
||||
break;
|
||||
|
||||
default:
|
||||
ss = "";
|
||||
break;
|
||||
}
|
||||
printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
|
||||
|
||||
printf ("\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_PM9G45
|
||||
|
||||
config SYS_BOARD
|
||||
default "pm9g45"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "ronetix"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "pm9g45"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
PM9G45 BOARD
|
||||
M: Ilko Iliev <iliev@ronetix.at>
|
||||
S: Maintained
|
||||
F: board/ronetix/pm9g45/
|
||||
F: include/configs/pm9g45.h
|
||||
F: configs/pm9g45_defconfig
|
||||
@@ -0,0 +1,10 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2003-2008
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2008
|
||||
# Stelian Pop <stelian@popies.net>
|
||||
# Lead Tech Design <www.leadtechdesign.com>
|
||||
|
||||
obj-y += pm9g45.o
|
||||
@@ -0,0 +1,175 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Ilko Iliev <iliev@ronetix.at>
|
||||
* Asen Dimov <dimov@ronetix.at>
|
||||
* Ronetix GmbH <www.ronetix.at>
|
||||
*
|
||||
* (C) Copyright 2007-2008
|
||||
* Stelian Pop <stelian@popies.net>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/at91sam9_smc.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/at91_matrix.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
|
||||
#include <net.h>
|
||||
#endif
|
||||
#include <netdev.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
static void pm9g45_nand_hw_init(void)
|
||||
{
|
||||
unsigned long csa;
|
||||
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
|
||||
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
|
||||
|
||||
/* Enable CS3 */
|
||||
csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
|
||||
writel(csa, &matrix->ccr[6]);
|
||||
|
||||
/* Configure SMC CS3 for NAND/SmartMedia */
|
||||
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
|
||||
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
|
||||
&smc->cs[3].setup);
|
||||
|
||||
writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
|
||||
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
|
||||
&smc->cs[3].pulse);
|
||||
|
||||
writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
|
||||
&smc->cs[3].cycle);
|
||||
|
||||
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
|
||||
AT91_SMC_MODE_EXNW_DISABLE |
|
||||
AT91_SMC_MODE_DBW_8 |
|
||||
AT91_SMC_MODE_TDF_CYCLE(3),
|
||||
&smc->cs[3].mode);
|
||||
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOC);
|
||||
|
||||
#ifdef CONFIG_SYS_NAND_READY_PIN
|
||||
/* Configure RDY/BSY */
|
||||
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
|
||||
#endif
|
||||
|
||||
/* Enable NandFlash */
|
||||
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACB
|
||||
static void pm9g45_macb_hw_init(void)
|
||||
{
|
||||
/*
|
||||
* PD2 enables the 50MHz oscillator for Ethernet PHY
|
||||
* 1 - enable
|
||||
* 0 - disable
|
||||
*/
|
||||
at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
|
||||
at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
|
||||
|
||||
at91_periph_clk_enable(ATMEL_ID_EMAC);
|
||||
|
||||
/*
|
||||
* Disable pull-up on:
|
||||
* RXDV (PA15) => PHY normal mode (not Test mode)
|
||||
* ERX0 (PA12) => PHY ADDR0
|
||||
* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
|
||||
*
|
||||
* PHY has internal pull-down
|
||||
*/
|
||||
at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
|
||||
at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
|
||||
at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
|
||||
|
||||
/* Re-enable pull-up */
|
||||
at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
|
||||
at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
|
||||
at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
|
||||
|
||||
at91_macb_hw_init();
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOA);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOB);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOC);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIODE);
|
||||
|
||||
at91_seriald_hw_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* arch number of AT91SAM9M10G45EK-Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
pm9g45_nand_hw_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACB
|
||||
pm9g45_macb_hw_init();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
|
||||
CONFIG_SYS_SDRAM_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
||||
gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
void reset_phy(void)
|
||||
{
|
||||
#ifdef CONFIG_MACB
|
||||
/*
|
||||
* Initialize ethernet HW addr prior to starting Linux,
|
||||
* needed for nfsroot
|
||||
*/
|
||||
eth_init();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_MACB
|
||||
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
Reference in New Issue
Block a user