GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_SOFTING_VINING_2000
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config SYS_BOARD
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default "vining_2000"
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config SYS_VENDOR
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default "softing"
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config SYS_CONFIG_NAME
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default "vining_2000"
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endif
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@@ -0,0 +1,6 @@
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VINING_2000 BOARD
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M: Silvio Fricke <open-source@softing.de>
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S: Maintained
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F: board/softing/vining_2000/
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F: include/configs/vining_2000.h
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F: configs/vining_2000_defconfig
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@@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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# (C) Copyright 2016 samtec automotive software & electronics gmbh
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# Copyright (C) 2017-2019 softing automotive electronics gmbH
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obj-y := vining_2000.o
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@@ -0,0 +1,132 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 samtec automotive software & electronics gmbh
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* Copyright (C) 2017-2019 softing automotive electronics gmbH
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi/sd/nand/onenand, qspi/nor
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* Enable all clocks */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020c4084 0xffffffff
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/* IOMUX - DDR IO Type */
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DATA 4 0x020e0618 0x000c0000
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DATA 4 0x020e05fc 0x00000000
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/* Clock */
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DATA 4 0x020e032c 0x00000030
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/* Address */
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DATA 4 0x020e0300 0x00000028
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DATA 4 0x020e02fc 0x00000028
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DATA 4 0x020e05f4 0x00000028
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/* Control */
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DATA 4 0x020e0340 0x00000028
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DATA 4 0x020e0320 0x00000000
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DATA 4 0x020e0310 0x00000028
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DATA 4 0x020e0314 0x00000028
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DATA 4 0x020e0614 0x00000028
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/* Data Strobe */
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DATA 4 0x020e05f8 0x00020000
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DATA 4 0x020e0330 0x00000028
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DATA 4 0x020e0334 0x00000028
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DATA 4 0x020e0338 0x00000028
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DATA 4 0x020e033c 0x00000028
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/* Data */
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DATA 4 0x020e0608 0x00020000
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DATA 4 0x020e060c 0x00000028
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DATA 4 0x020e0610 0x00000028
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DATA 4 0x020e061c 0x00000028
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DATA 4 0x020e0620 0x00000028
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DATA 4 0x020e02ec 0x00000028
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DATA 4 0x020e02f0 0x00000028
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DATA 4 0x020e02f4 0x00000028
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DATA 4 0x020e02f8 0x00000028
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/* Calibrations - ZQ */
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DATA 4 0x021b0800 0xa1390003
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/* Write leveling */
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DATA 4 0x021b080c 0x00290025
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DATA 4 0x021b0810 0x00210022
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/* DQS Read Gate */
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DATA 4 0x021b083c 0x4142013a
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DATA 4 0x021b0840 0x012e0123
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/* Read/Write Delay */
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DATA 4 0x021b0848 0x43474949
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DATA 4 0x021b0850 0x38383c38
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/* Read data bit delay */
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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/* Complete calibration by forced measurement */
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DATA 4 0x021b08b8 0x00000800
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/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
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DATA 4 0x021b0004 0x0002002d
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DATA 4 0x021b0008 0x00333040
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DATA 4 0x021b000c 0x676b52f2
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DATA 4 0x021b0010 0x926e8b63
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DATA 4 0x021b0014 0x01ff00db
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DATA 4 0x021b0018 0x00011740
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b002c 0x000026d2
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DATA 4 0x021b0030 0x006b1023
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DATA 4 0x021b0040 0x0000005f
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DATA 4 0x021b0000 0x84190000
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/* Initialize MT41K256M16HA-125 - MR2 */
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DATA 4 0x021b001c 0x02008032
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/* MR3 */
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DATA 4 0x021b001c 0x00008033
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/* MR1 */
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DATA 4 0x021b001c 0x00048031
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/* MR0 */
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DATA 4 0x021b001c 0x15108030
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/* DDR device ZQ calibration */
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DATA 4 0x021b001c 0x04008040
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/* Final DDR setup, before operation start */
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DATA 4 0x021b0020 0x00007800
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DATA 4 0x021b0818 0x00022227
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DATA 4 0x021b001c 0x00000000
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@@ -0,0 +1,625 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 samtec automotive software & electronics gmbh
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* Copyright (C) 2017-2019 softing automotive electronics gmbH
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*
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* Author: Christoph Fritz <chf.fritz@googlemail.com>
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*/
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <env.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <fsl_esdhc_imx.h>
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#include <mmc.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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#include <pwm.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
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PAD_CTL_SRE_FAST)
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#define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
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PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
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PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
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PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm)
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#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
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#define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST)
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#define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
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#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
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PAD_CTL_PKE)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const pwm_led_pads[] = {
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MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
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MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
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MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
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};
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static int board_net_init(void)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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unsigned char eth1addr[6];
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int ret;
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/* just to get second mac address */
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imx_get_mac_from_fuse(1, eth1addr);
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if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
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eth_env_set_enetaddr("eth1addr", eth1addr);
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/*
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* Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
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* ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
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* ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
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*/
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clrsetbits_le32(&iomuxc_regs->gpr[1],
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IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
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IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
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IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
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IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
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ret = enable_fec_anatop_clock(0, ENET_50MHZ);
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if (ret)
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goto eth_fail;
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ret = enable_fec_anatop_clock(1, ENET_50MHZ);
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if (ret)
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goto eth_fail;
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return ret;
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eth_fail:
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printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
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return ret;
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}
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1 for PMIC */
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
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.gp = IMX_GPIO_NR(1, 0),
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
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.gp = IMX_GPIO_NR(1, 1),
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},
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};
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static struct pmic *pfuze_init(unsigned char i2cbus)
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{
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struct pmic *p;
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int ret;
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u32 reg;
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ret = power_pfuze100_init(i2cbus);
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if (ret)
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return NULL;
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p = pmic_get("PFUZE100");
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ret = pmic_probe(p);
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if (ret)
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return NULL;
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pmic_reg_read(p, PFUZE100_DEVICEID, ®);
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printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
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/* Set SW1AB stanby volage to 0.975V */
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pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
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reg &= ~SW1x_STBY_MASK;
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reg |= SW1x_0_975V;
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pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
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/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
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pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
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reg &= ~SW1xCONF_DVSSPEED_MASK;
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reg |= SW1xCONF_DVSSPEED_4US;
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pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
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|
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/* Set SW1C standby voltage to 0.975V */
|
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pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
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reg &= ~SW1x_STBY_MASK;
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reg |= SW1x_0_975V;
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pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
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|
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/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
|
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pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
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reg &= ~SW1xCONF_DVSSPEED_MASK;
|
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reg |= SW1xCONF_DVSSPEED_4US;
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pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
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|
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return p;
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}
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|
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static int pfuze_mode_init(struct pmic *p, u32 mode)
|
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{
|
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unsigned char offset, i, switch_num;
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u32 id;
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int ret;
|
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|
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pmic_reg_read(p, PFUZE100_DEVICEID, &id);
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id = id & 0xf;
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|
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if (id == 0) {
|
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switch_num = 6;
|
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offset = PFUZE100_SW1CMODE;
|
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} else if (id == 1) {
|
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switch_num = 4;
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offset = PFUZE100_SW2MODE;
|
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} else {
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printf("Not supported, id=%d\n", id);
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return -EINVAL;
|
||||
}
|
||||
|
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ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
|
||||
if (ret < 0) {
|
||||
printf("Set SW1AB mode error!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < switch_num - 1; i++) {
|
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ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
|
||||
if (ret < 0) {
|
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printf("Set switch 0x%x mode error!\n",
|
||||
offset + i * SWITCH_SIZE);
|
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return ret;
|
||||
}
|
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}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct pmic *p;
|
||||
int ret;
|
||||
|
||||
p = pfuze_init(I2C_PMIC);
|
||||
if (!p)
|
||||
return -ENODEV;
|
||||
|
||||
ret = pfuze_mode_init(p, APS_PFM);
|
||||
if (ret < 0)
|
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return ret;
|
||||
|
||||
set_ldo_voltage(LDO_ARM, 1175); /* Set VDDARM to 1.175V */
|
||||
set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
static iomux_v3_cfg_t const usb_otg_pads[] = {
|
||||
/* OGT1 */
|
||||
MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
|
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/* OTG2 */
|
||||
MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
|
||||
};
|
||||
|
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static void setup_iomux_usb(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
|
||||
ARRAY_SIZE(usb_otg_pads));
|
||||
}
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
if (port == 1)
|
||||
return USB_INIT_HOST;
|
||||
else
|
||||
return usb_phy_mode(port);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PWM_IMX
|
||||
static int set_pwm_leds(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
|
||||
ARRAY_SIZE(pwm_led_pads));
|
||||
/* enable backlight PWM 2, green LED */
|
||||
ret = pwm_init(1, 0, 0);
|
||||
if (ret)
|
||||
goto error;
|
||||
/* duty cycle 200ns, period: 8000ns */
|
||||
ret = pwm_config(1, 200, 8000);
|
||||
if (ret)
|
||||
goto error;
|
||||
ret = pwm_enable(1);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
/* enable backlight PWM 1, blue LED */
|
||||
ret = pwm_init(0, 0, 0);
|
||||
if (ret)
|
||||
goto error;
|
||||
/* duty cycle 200ns, period: 8000ns */
|
||||
ret = pwm_config(0, 200, 8000);
|
||||
if (ret)
|
||||
goto error;
|
||||
ret = pwm_enable(0);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
/* enable backlight PWM 6, red LED */
|
||||
ret = pwm_init(5, 0, 0);
|
||||
if (ret)
|
||||
goto error;
|
||||
/* duty cycle 200ns, period: 8000ns */
|
||||
ret = pwm_config(5, 200, 8000);
|
||||
if (ret)
|
||||
goto error;
|
||||
ret = pwm_enable(5);
|
||||
|
||||
error:
|
||||
return ret;
|
||||
}
|
||||
#else
|
||||
static int set_pwm_leds(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define ADCx_HC0 0x00
|
||||
#define ADCx_HS 0x08
|
||||
#define ADCx_HS_C0 BIT(0)
|
||||
#define ADCx_R0 0x0c
|
||||
#define ADCx_CFG 0x14
|
||||
#define ADCx_CFG_SWMODE 0x308
|
||||
#define ADCx_GC 0x18
|
||||
#define ADCx_GC_CAL BIT(7)
|
||||
|
||||
static int read_adc(u32 *val)
|
||||
{
|
||||
int ret;
|
||||
void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
|
||||
|
||||
/* use software mode */
|
||||
writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
|
||||
|
||||
/* start auto calibration */
|
||||
setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
|
||||
ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
|
||||
if (ret)
|
||||
goto adc_exit;
|
||||
|
||||
/* start conversion */
|
||||
writel(0, b + ADCx_HC0);
|
||||
|
||||
/* wait for conversion */
|
||||
ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
|
||||
if (ret)
|
||||
goto adc_exit;
|
||||
|
||||
/* read result */
|
||||
*val = readl(b + ADCx_R0);
|
||||
|
||||
adc_exit:
|
||||
if (ret)
|
||||
printf("ADC failure (ret=%i)\n", ret);
|
||||
unmap_physmem(b, MAP_NOCACHE);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define VAL_UPPER 2498
|
||||
#define VAL_LOWER 1550
|
||||
|
||||
static int set_pin_state(void)
|
||||
{
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = read_adc(&val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (val >= VAL_UPPER)
|
||||
env_set("pin_state", "connected");
|
||||
else if (val < VAL_UPPER && val > VAL_LOWER)
|
||||
env_set("pin_state", "open");
|
||||
else
|
||||
env_set("pin_state", "button");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = set_pwm_leds();
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = set_pin_state();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_usb();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
#endif
|
||||
|
||||
return board_net_init();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: VIN|ING 2000\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define PCIE_PHY_PUP_REQ BIT(7)
|
||||
|
||||
void board_preboot_os(void)
|
||||
{
|
||||
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
|
||||
|
||||
/* Bring the PCI power domain up, so that old vendorkernel works. */
|
||||
setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
|
||||
setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
|
||||
setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <linux/libfdt.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
|
||||
|
||||
static iomux_v3_cfg_t const pcie_pads[] = {
|
||||
MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const uart_pads[] = {
|
||||
MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc4_pads[] = {
|
||||
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void vining2000_spl_setup_iomux_pcie(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
|
||||
}
|
||||
|
||||
static void vining2000_spl_setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
|
||||
u32 val;
|
||||
u32 port;
|
||||
|
||||
val = readl(&src_regs->sbmr1);
|
||||
|
||||
if ((val & 0xc0) != 0x40) {
|
||||
printf("Not boot from USDHC!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
port = (val >> 11) & 0x3;
|
||||
printf("port %d\n", port);
|
||||
switch (port) {
|
||||
case 3:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
||||
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR;
|
||||
break;
|
||||
}
|
||||
|
||||
gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg);
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
|
||||
.dram_dqm0 = 0x00000028,
|
||||
.dram_dqm1 = 0x00000028,
|
||||
.dram_dqm2 = 0x00000028,
|
||||
.dram_dqm3 = 0x00000028,
|
||||
.dram_ras = 0x00000028,
|
||||
.dram_cas = 0x00000028,
|
||||
.dram_odt0 = 0x00000028,
|
||||
.dram_odt1 = 0x00000028,
|
||||
.dram_sdba2 = 0x00000000,
|
||||
.dram_sdcke0 = 0x00003000,
|
||||
.dram_sdcke1 = 0x00003000,
|
||||
.dram_sdclk_0 = 0x00000030,
|
||||
.dram_sdqs0 = 0x00000028,
|
||||
.dram_sdqs1 = 0x00000028,
|
||||
.dram_sdqs2 = 0x00000028,
|
||||
.dram_sdqs3 = 0x00000028,
|
||||
.dram_reset = 0x00000028,
|
||||
};
|
||||
|
||||
const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
|
||||
.grp_addds = 0x00000028,
|
||||
.grp_b0ds = 0x00000028,
|
||||
.grp_b1ds = 0x00000028,
|
||||
.grp_b2ds = 0x00000028,
|
||||
.grp_b3ds = 0x00000028,
|
||||
.grp_ctlds = 0x00000028,
|
||||
.grp_ddr_type = 0x000c0000,
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
.grp_ddrpke = 0x00000000,
|
||||
};
|
||||
|
||||
const struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
||||
.p0_mpwldectrl0 = 0x0022001C,
|
||||
.p0_mpwldectrl1 = 0x001F001A,
|
||||
.p0_mpdgctrl0 = 0x01380134,
|
||||
.p0_mpdgctrl1 = 0x0124011C,
|
||||
.p0_mprddlctl = 0x42404444,
|
||||
.p0_mpwrdlctl = 0x36383C38,
|
||||
};
|
||||
|
||||
static struct mx6_ddr3_cfg mem_ddr = {
|
||||
.mem_speed = 1600,
|
||||
.density = 4,
|
||||
.width = 32,
|
||||
.banks = 8,
|
||||
.rowaddr = 15,
|
||||
.coladdr = 10,
|
||||
.pagesz = 2,
|
||||
.trcd = 1391,
|
||||
.trcmin = 4875,
|
||||
.trasmin = 3500,
|
||||
};
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */
|
||||
writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */
|
||||
writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */
|
||||
writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */
|
||||
writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */
|
||||
writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */
|
||||
writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */
|
||||
}
|
||||
|
||||
static void vining2000_spl_dram_init(void)
|
||||
{
|
||||
struct mx6_ddr_sysinfo sysinfo = {
|
||||
.dsize = mem_ddr.width / 32,
|
||||
.cs_density = 24,
|
||||
.ncs = 1,
|
||||
.cs1_mirror = 0,
|
||||
.rtt_wr = 1, /* RTT_wr = RZQ/4 */
|
||||
.rtt_nom = 1, /* RTT_Nom = RZQ/4 */
|
||||
.walat = 1, /* Write additional latency */
|
||||
.ralat = 5, /* Read additional latency */
|
||||
.mif3_mode = 3, /* Command prediction working mode */
|
||||
.bi_on = 1, /* Bank interleaving enabled */
|
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
||||
.ddr_type = DDR_TYPE_DDR3,
|
||||
.refsel = 1, /* Refresh cycles at 32KHz */
|
||||
.refr = 7, /* 8 refresh commands per refresh cycle */
|
||||
};
|
||||
|
||||
mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
||||
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
||||
|
||||
/* Perform DDR DRAM calibration */
|
||||
udelay(100);
|
||||
mmdc_do_write_level_calibration(&sysinfo);
|
||||
mmdc_do_dqs_calibration(&sysinfo);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
ccgr_init();
|
||||
|
||||
/* iomux setup */
|
||||
vining2000_spl_setup_iomux_pcie();
|
||||
vining2000_spl_setup_iomux_uart();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* reset the PCIe device */
|
||||
gpio_set_value(IMX_GPIO_NR(4, 6), 1);
|
||||
udelay(50);
|
||||
gpio_set_value(IMX_GPIO_NR(4, 6), 0);
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* DDR initialization */
|
||||
vining2000_spl_dram_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* load/boot image from boot device */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,5 @@
|
||||
VINING FPGA BOARD
|
||||
M: Marek Vasut <marex@denx.de>
|
||||
S: Maintained
|
||||
F: include/configs/socfpga_vining_fpga.h
|
||||
F: configs/socfpga_vining_fpga_defconfig
|
||||
@@ -0,0 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
|
||||
|
||||
obj-y := socfpga.o
|
||||
@@ -0,0 +1,659 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Altera SoCFPGA IOCSR configuration
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
|
||||
#define __SOCFPGA_IOCSR_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
|
||||
const unsigned long iocsr_scan_chain0_table[] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0xC0000000,
|
||||
0x0000003F,
|
||||
0x00008000,
|
||||
0x00060180,
|
||||
0x18060000,
|
||||
0x18000000,
|
||||
0x00018060,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x000300C0,
|
||||
0x0C030000,
|
||||
0x0C000000,
|
||||
0x00000030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x00018060,
|
||||
0x06018000,
|
||||
0x06000000,
|
||||
0x00000018,
|
||||
0x00006018,
|
||||
0x00001000,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain1_table[] = {
|
||||
0x00000000,
|
||||
0x300C0000,
|
||||
0x000000C0,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00008000,
|
||||
0x00060180,
|
||||
0x18060000,
|
||||
0x18000000,
|
||||
0x00000060,
|
||||
0x00018060,
|
||||
0x00004000,
|
||||
0x000300C0,
|
||||
0x0C030000,
|
||||
0x0C000000,
|
||||
0x00000030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x06018060,
|
||||
0x06018000,
|
||||
0x01FE0000,
|
||||
0xF8000000,
|
||||
0x00000007,
|
||||
0x00001000,
|
||||
0x0000C030,
|
||||
0x0300C000,
|
||||
0x03000000,
|
||||
0x0000300C,
|
||||
0x0000300C,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x01800000,
|
||||
0x00000006,
|
||||
0x00601806,
|
||||
0x00000400,
|
||||
0x00000000,
|
||||
0x00C03000,
|
||||
0x00000003,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,
|
||||
0x00601806,
|
||||
0x00000000,
|
||||
0x80600000,
|
||||
0x80000601,
|
||||
0x00000601,
|
||||
0x00000100,
|
||||
0x00300C03,
|
||||
0xC0300C00,
|
||||
0xC0300000,
|
||||
0xC0000300,
|
||||
0x000C0300,
|
||||
0x00000080,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain2_table[] = {
|
||||
0x300C0300,
|
||||
0x300C0000,
|
||||
0x0FF00000,
|
||||
0x00000000,
|
||||
0x000300C0,
|
||||
0x00008000,
|
||||
0x18060180,
|
||||
0x18060000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00018060,
|
||||
0x00004000,
|
||||
0x000300C0,
|
||||
0x0C030000,
|
||||
0x00000030,
|
||||
0x00000000,
|
||||
0x0300C030,
|
||||
0x00002000,
|
||||
0x00018060,
|
||||
0x06018000,
|
||||
0x06000000,
|
||||
0x00000018,
|
||||
0x00006018,
|
||||
0x00001000,
|
||||
0x0000C030,
|
||||
0x00000000,
|
||||
0x03000000,
|
||||
0x0000000C,
|
||||
0x00C0300C,
|
||||
0x00000800,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain3_table[] = {
|
||||
0x0C420D80,
|
||||
0x082000FF,
|
||||
0x0A804001,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0xD4380000,
|
||||
0xE0003000,
|
||||
0x00C00350,
|
||||
0x00000000,
|
||||
0x00000021,
|
||||
0x82000004,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x04010000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x6A1C0000,
|
||||
0x70001800,
|
||||
0x006001A8,
|
||||
0x8006A1C0,
|
||||
0x00000001,
|
||||
0x40000002,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x350E0000,
|
||||
0x38000C00,
|
||||
0x003000D4,
|
||||
0xC00350E0,
|
||||
0x0D438000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0x40680A28,
|
||||
0x41034051,
|
||||
0x12481A00,
|
||||
0x80A280D0,
|
||||
0x34051406,
|
||||
0x01A02490,
|
||||
0x080D0000,
|
||||
0x51406802,
|
||||
0x02490340,
|
||||
0xD000001A,
|
||||
0x0680A280,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0xC0000000,
|
||||
0x018006A1,
|
||||
0x001A8700,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x0A800001,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0xD4380000,
|
||||
0xE0003000,
|
||||
0x00C00350,
|
||||
0x00000FF0,
|
||||
0x350E0000,
|
||||
0x80000C00,
|
||||
0x05400000,
|
||||
0x02480000,
|
||||
0x04000000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x6A1C0000,
|
||||
0x70001800,
|
||||
0x006001A8,
|
||||
0x8006A1C0,
|
||||
0x1A870001,
|
||||
0x40000600,
|
||||
0x02A00040,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x350E0000,
|
||||
0x38000C00,
|
||||
0x003000D4,
|
||||
0xC00350E0,
|
||||
0x0D438000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0x40680208,
|
||||
0x49034051,
|
||||
0x12481A02,
|
||||
0x80A280D0,
|
||||
0x34030C06,
|
||||
0x01A00040,
|
||||
0x280D0002,
|
||||
0x5140680A,
|
||||
0x01450340,
|
||||
0xD00A281A,
|
||||
0x0680E380,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0xC0000000,
|
||||
0x018006A1,
|
||||
0x001A8700,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x99300001,
|
||||
0x34343400,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x01000000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0xD438090C,
|
||||
0x00003000,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0x8A28A3DD,
|
||||
0xF6D1451E,
|
||||
0x034AD348,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x05140680,
|
||||
0xDD59647A,
|
||||
0x1E8A28A3,
|
||||
0x48F6D145,
|
||||
0x00034AD3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00003FC2,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00015000,
|
||||
0x0000F200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x70120800,
|
||||
0x006001A8,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0x8A28A3DD,
|
||||
0xF6D1451E,
|
||||
0x034AD348,
|
||||
0x821A0186,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xDD59647A,
|
||||
0x1E8A28A3,
|
||||
0x48F6D145,
|
||||
0x00034AD3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0xD438090C,
|
||||
0x00003000,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0x8A28A3DD,
|
||||
0xF6D1451E,
|
||||
0x034AD348,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xDD59647A,
|
||||
0x1E8A28A3,
|
||||
0x48F6D145,
|
||||
0x00034AD3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00400000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F1690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0x8A28A3DD,
|
||||
0xF6D1451E,
|
||||
0x034AD348,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xDD59647A,
|
||||
0x1E8A28A3,
|
||||
0x48F6D145,
|
||||
0x00034AD3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0x00489800,
|
||||
0x801A1A1A,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x00000004,
|
||||
0x00040000,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00010000,
|
||||
0x40002000,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x00000002,
|
||||
0x00020000,
|
||||
0x08000000,
|
||||
0x00000000,
|
||||
0x00000020,
|
||||
0x00008000,
|
||||
0x20001000,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x00000001,
|
||||
0x00010000,
|
||||
0x04000000,
|
||||
0x00FF0000,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x00000800,
|
||||
0xC0000001,
|
||||
0x00041419,
|
||||
0x40000000,
|
||||
0x04000816,
|
||||
0x000D0000,
|
||||
0x00006800,
|
||||
0x00000340,
|
||||
0xD000001A,
|
||||
0x06800000,
|
||||
0x00340000,
|
||||
0x0001A000,
|
||||
0x00000D00,
|
||||
0x40000068,
|
||||
0x1A000003,
|
||||
0x00D00000,
|
||||
0x00068000,
|
||||
0x00003400,
|
||||
0x000001A0,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x80000008,
|
||||
0x0000007F,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0xE0000080,
|
||||
0x0000001F,
|
||||
0x00004000,
|
||||
};
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
|
||||
@@ -0,0 +1,218 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Altera SoCFPGA PinMux configuration
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_PINMUX_CONFIG_H__
|
||||
#define __SOCFPGA_PINMUX_CONFIG_H__
|
||||
|
||||
const u8 sys_mgr_init_table[] = {
|
||||
0, /* EMACIO0 */
|
||||
2, /* EMACIO1 */
|
||||
2, /* EMACIO2 */
|
||||
2, /* EMACIO3 */
|
||||
2, /* EMACIO4 */
|
||||
2, /* EMACIO5 */
|
||||
2, /* EMACIO6 */
|
||||
2, /* EMACIO7 */
|
||||
2, /* EMACIO8 */
|
||||
0, /* EMACIO9 */
|
||||
2, /* EMACIO10 */
|
||||
2, /* EMACIO11 */
|
||||
2, /* EMACIO12 */
|
||||
2, /* EMACIO13 */
|
||||
0, /* EMACIO14 */
|
||||
0, /* EMACIO15 */
|
||||
0, /* EMACIO16 */
|
||||
0, /* EMACIO17 */
|
||||
0, /* EMACIO18 */
|
||||
0, /* EMACIO19 */
|
||||
2, /* FLASHIO0 */
|
||||
2, /* FLASHIO1 */
|
||||
2, /* FLASHIO2 */
|
||||
2, /* FLASHIO3 */
|
||||
2, /* FLASHIO4 */
|
||||
2, /* FLASHIO5 */
|
||||
2, /* FLASHIO6 */
|
||||
2, /* FLASHIO7 */
|
||||
2, /* FLASHIO8 */
|
||||
2, /* FLASHIO9 */
|
||||
2, /* FLASHIO10 */
|
||||
2, /* FLASHIO11 */
|
||||
0, /* GENERALIO0 */
|
||||
1, /* GENERALIO1 */
|
||||
1, /* GENERALIO2 */
|
||||
1, /* GENERALIO3 */
|
||||
1, /* GENERALIO4 */
|
||||
0, /* GENERALIO5 */
|
||||
0, /* GENERALIO6 */
|
||||
1, /* GENERALIO7 */
|
||||
1, /* GENERALIO8 */
|
||||
3, /* GENERALIO9 */
|
||||
3, /* GENERALIO10 */
|
||||
3, /* GENERALIO11 */
|
||||
3, /* GENERALIO12 */
|
||||
0, /* GENERALIO13 */
|
||||
0, /* GENERALIO14 */
|
||||
2, /* GENERALIO15 */
|
||||
2, /* GENERALIO16 */
|
||||
0, /* GENERALIO17 */
|
||||
0, /* GENERALIO18 */
|
||||
0, /* GENERALIO19 */
|
||||
0, /* GENERALIO20 */
|
||||
0, /* GENERALIO21 */
|
||||
0, /* GENERALIO22 */
|
||||
0, /* GENERALIO23 */
|
||||
0, /* GENERALIO24 */
|
||||
0, /* GENERALIO25 */
|
||||
0, /* GENERALIO26 */
|
||||
0, /* GENERALIO27 */
|
||||
0, /* GENERALIO28 */
|
||||
0, /* GENERALIO29 */
|
||||
0, /* GENERALIO30 */
|
||||
0, /* GENERALIO31 */
|
||||
2, /* MIXED1IO0 */
|
||||
2, /* MIXED1IO1 */
|
||||
2, /* MIXED1IO2 */
|
||||
2, /* MIXED1IO3 */
|
||||
2, /* MIXED1IO4 */
|
||||
2, /* MIXED1IO5 */
|
||||
2, /* MIXED1IO6 */
|
||||
2, /* MIXED1IO7 */
|
||||
2, /* MIXED1IO8 */
|
||||
2, /* MIXED1IO9 */
|
||||
2, /* MIXED1IO10 */
|
||||
2, /* MIXED1IO11 */
|
||||
2, /* MIXED1IO12 */
|
||||
2, /* MIXED1IO13 */
|
||||
2, /* MIXED1IO14 */
|
||||
3, /* MIXED1IO15 */
|
||||
3, /* MIXED1IO16 */
|
||||
3, /* MIXED1IO17 */
|
||||
3, /* MIXED1IO18 */
|
||||
3, /* MIXED1IO19 */
|
||||
3, /* MIXED1IO20 */
|
||||
0, /* MIXED1IO21 */
|
||||
0, /* MIXED2IO0 */
|
||||
0, /* MIXED2IO1 */
|
||||
0, /* MIXED2IO2 */
|
||||
0, /* MIXED2IO3 */
|
||||
0, /* MIXED2IO4 */
|
||||
0, /* MIXED2IO5 */
|
||||
0, /* MIXED2IO6 */
|
||||
0, /* MIXED2IO7 */
|
||||
0, /* GPLINMUX48 */
|
||||
0, /* GPLINMUX49 */
|
||||
0, /* GPLINMUX50 */
|
||||
0, /* GPLINMUX51 */
|
||||
0, /* GPLINMUX52 */
|
||||
0, /* GPLINMUX53 */
|
||||
0, /* GPLINMUX54 */
|
||||
0, /* GPLINMUX55 */
|
||||
0, /* GPLINMUX56 */
|
||||
0, /* GPLINMUX57 */
|
||||
0, /* GPLINMUX58 */
|
||||
0, /* GPLINMUX59 */
|
||||
0, /* GPLINMUX60 */
|
||||
0, /* GPLINMUX61 */
|
||||
0, /* GPLINMUX62 */
|
||||
0, /* GPLINMUX63 */
|
||||
0, /* GPLINMUX64 */
|
||||
0, /* GPLINMUX65 */
|
||||
0, /* GPLINMUX66 */
|
||||
0, /* GPLINMUX67 */
|
||||
0, /* GPLINMUX68 */
|
||||
0, /* GPLINMUX69 */
|
||||
0, /* GPLINMUX70 */
|
||||
1, /* GPLMUX0 */
|
||||
1, /* GPLMUX1 */
|
||||
1, /* GPLMUX2 */
|
||||
1, /* GPLMUX3 */
|
||||
1, /* GPLMUX4 */
|
||||
1, /* GPLMUX5 */
|
||||
1, /* GPLMUX6 */
|
||||
1, /* GPLMUX7 */
|
||||
1, /* GPLMUX8 */
|
||||
1, /* GPLMUX9 */
|
||||
1, /* GPLMUX10 */
|
||||
1, /* GPLMUX11 */
|
||||
1, /* GPLMUX12 */
|
||||
1, /* GPLMUX13 */
|
||||
1, /* GPLMUX14 */
|
||||
1, /* GPLMUX15 */
|
||||
1, /* GPLMUX16 */
|
||||
1, /* GPLMUX17 */
|
||||
1, /* GPLMUX18 */
|
||||
1, /* GPLMUX19 */
|
||||
1, /* GPLMUX20 */
|
||||
1, /* GPLMUX21 */
|
||||
1, /* GPLMUX22 */
|
||||
1, /* GPLMUX23 */
|
||||
1, /* GPLMUX24 */
|
||||
1, /* GPLMUX25 */
|
||||
1, /* GPLMUX26 */
|
||||
1, /* GPLMUX27 */
|
||||
1, /* GPLMUX28 */
|
||||
1, /* GPLMUX29 */
|
||||
1, /* GPLMUX30 */
|
||||
1, /* GPLMUX31 */
|
||||
1, /* GPLMUX32 */
|
||||
1, /* GPLMUX33 */
|
||||
1, /* GPLMUX34 */
|
||||
1, /* GPLMUX35 */
|
||||
1, /* GPLMUX36 */
|
||||
1, /* GPLMUX37 */
|
||||
1, /* GPLMUX38 */
|
||||
1, /* GPLMUX39 */
|
||||
1, /* GPLMUX40 */
|
||||
1, /* GPLMUX41 */
|
||||
1, /* GPLMUX42 */
|
||||
1, /* GPLMUX43 */
|
||||
1, /* GPLMUX44 */
|
||||
1, /* GPLMUX45 */
|
||||
1, /* GPLMUX46 */
|
||||
1, /* GPLMUX47 */
|
||||
1, /* GPLMUX48 */
|
||||
1, /* GPLMUX49 */
|
||||
1, /* GPLMUX50 */
|
||||
1, /* GPLMUX51 */
|
||||
1, /* GPLMUX52 */
|
||||
1, /* GPLMUX53 */
|
||||
1, /* GPLMUX54 */
|
||||
1, /* GPLMUX55 */
|
||||
1, /* GPLMUX56 */
|
||||
1, /* GPLMUX57 */
|
||||
1, /* GPLMUX58 */
|
||||
1, /* GPLMUX59 */
|
||||
1, /* GPLMUX60 */
|
||||
1, /* GPLMUX61 */
|
||||
1, /* GPLMUX62 */
|
||||
1, /* GPLMUX63 */
|
||||
1, /* GPLMUX64 */
|
||||
1, /* GPLMUX65 */
|
||||
1, /* GPLMUX66 */
|
||||
1, /* GPLMUX67 */
|
||||
1, /* GPLMUX68 */
|
||||
1, /* GPLMUX69 */
|
||||
1, /* GPLMUX70 */
|
||||
0, /* NANDUSEFPGA */
|
||||
0, /* UART0USEFPGA */
|
||||
0, /* RGMII1USEFPGA */
|
||||
0, /* SPIS0USEFPGA */
|
||||
0, /* CAN0USEFPGA */
|
||||
0, /* I2C0USEFPGA */
|
||||
0, /* SDMMCUSEFPGA */
|
||||
0, /* QSPIUSEFPGA */
|
||||
0, /* SPIS1USEFPGA */
|
||||
1, /* RGMII0USEFPGA */
|
||||
0, /* UART1USEFPGA */
|
||||
0, /* CAN1USEFPGA */
|
||||
0, /* USB1USEFPGA */
|
||||
0, /* I2C3USEFPGA */
|
||||
0, /* I2C2USEFPGA */
|
||||
0, /* I2C1USEFPGA */
|
||||
1, /* SPIM1USEFPGA */
|
||||
0, /* USB0USEFPGA */
|
||||
0 /* SPIM0USEFPGA */
|
||||
};
|
||||
#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
|
||||
@@ -0,0 +1,84 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Altera SoCFPGA Clock and PLL configuration
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_PLL_CONFIG_H__
|
||||
#define __SOCFPGA_PLL_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
||||
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
|
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_NAND_HZ 488281
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ 320000000
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ 12500000
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ 12500000
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
||||
|
||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
|
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
|
||||
@@ -0,0 +1,343 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Altera SoCFPGA SDRAM configuration
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_SDRAM_CONFIG_H__
|
||||
#define __SOCFPGA_SDRAM_CONFIG_H__
|
||||
|
||||
/* SDRAM configuration */
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
|
||||
/* Sequencer auto configuration */
|
||||
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
|
||||
#define RW_MGR_ACTIVATE_1 0x0F
|
||||
#define RW_MGR_CLEAR_DQS_ENABLE 0x49
|
||||
#define RW_MGR_GUARANTEED_READ 0x4C
|
||||
#define RW_MGR_GUARANTEED_READ_CONT 0x54
|
||||
#define RW_MGR_GUARANTEED_WRITE 0x18
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
|
||||
#define RW_MGR_IDLE 0x00
|
||||
#define RW_MGR_IDLE_LOOP1 0x7B
|
||||
#define RW_MGR_IDLE_LOOP2 0x7A
|
||||
#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
|
||||
#define RW_MGR_INIT_RESET_1_CKE_0 0x74
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
|
||||
#define RW_MGR_MRS0_DLL_RESET 0x02
|
||||
#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
|
||||
#define RW_MGR_MRS0_USER 0x07
|
||||
#define RW_MGR_MRS0_USER_MIRR 0x0C
|
||||
#define RW_MGR_MRS1 0x03
|
||||
#define RW_MGR_MRS1_MIRR 0x09
|
||||
#define RW_MGR_MRS2 0x04
|
||||
#define RW_MGR_MRS2_MIRR 0x0A
|
||||
#define RW_MGR_MRS3 0x05
|
||||
#define RW_MGR_MRS3_MIRR 0x0B
|
||||
#define RW_MGR_PRECHARGE_ALL 0x12
|
||||
#define RW_MGR_READ_B2B 0x59
|
||||
#define RW_MGR_READ_B2B_WAIT1 0x61
|
||||
#define RW_MGR_READ_B2B_WAIT2 0x6B
|
||||
#define RW_MGR_REFRESH_ALL 0x14
|
||||
#define RW_MGR_RETURN 0x01
|
||||
#define RW_MGR_SGLE_READ 0x7D
|
||||
#define RW_MGR_ZQCL 0x06
|
||||
|
||||
/* Sequencer defines configuration */
|
||||
#define AFI_RATE_RATIO 1
|
||||
#define CALIB_LFIFO_OFFSET 7
|
||||
#define CALIB_VFIFO_OFFSET 5
|
||||
#define ENABLE_SUPER_QUICK_CALIBRATION 0
|
||||
#define IO_DELAY_PER_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_OPA_TAP 312
|
||||
#define IO_DLL_CHAIN_LENGTH 8
|
||||
#define IO_DQDQS_OUT_PHASE_MAX 0
|
||||
#define IO_DQS_EN_DELAY_MAX 31
|
||||
#define IO_DQS_EN_DELAY_OFFSET 0
|
||||
#define IO_DQS_EN_PHASE_MAX 7
|
||||
#define IO_DQS_IN_DELAY_MAX 31
|
||||
#define IO_DQS_IN_RESERVE 4
|
||||
#define IO_DQS_OUT_RESERVE 4
|
||||
#define IO_IO_IN_DELAY_MAX 31
|
||||
#define IO_IO_OUT1_DELAY_MAX 31
|
||||
#define IO_IO_OUT2_DELAY_MAX 0
|
||||
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
|
||||
#define MAX_LATENCY_COUNT_WIDTH 5
|
||||
#define READ_VALID_FIFO_SIZE 16
|
||||
#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b4
|
||||
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
|
||||
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
|
||||
#define RW_MGR_MEM_DATA_WIDTH 32
|
||||
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
|
||||
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
|
||||
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
|
||||
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
|
||||
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
|
||||
#define TINIT_CNTR0_VAL 99
|
||||
#define TINIT_CNTR1_VAL 32
|
||||
#define TINIT_CNTR2_VAL 32
|
||||
#define TRESET_CNTR0_VAL 99
|
||||
#define TRESET_CNTR1_VAL 99
|
||||
#define TRESET_CNTR2_VAL 10
|
||||
|
||||
/* Sequencer ac_rom_init configuration */
|
||||
const u32 ac_rom_init[] = {
|
||||
0x20700000,
|
||||
0x20780000,
|
||||
0x10080421,
|
||||
0x10080520,
|
||||
0x10090046,
|
||||
0x100a0088,
|
||||
0x100b0000,
|
||||
0x10380400,
|
||||
0x10080441,
|
||||
0x100804c0,
|
||||
0x100a0026,
|
||||
0x10090110,
|
||||
0x100b0000,
|
||||
0x30780000,
|
||||
0x38780000,
|
||||
0x30780000,
|
||||
0x10680000,
|
||||
0x106b0000,
|
||||
0x10280400,
|
||||
0x10480000,
|
||||
0x1c980000,
|
||||
0x1c9b0000,
|
||||
0x1c980008,
|
||||
0x1c9b0008,
|
||||
0x38f80000,
|
||||
0x3cf80000,
|
||||
0x38780000,
|
||||
0x18180000,
|
||||
0x18980000,
|
||||
0x13580000,
|
||||
0x135b0000,
|
||||
0x13580008,
|
||||
0x135b0008,
|
||||
0x33780000,
|
||||
0x10580008,
|
||||
0x10780000
|
||||
};
|
||||
|
||||
/* Sequencer inst_rom_init configuration */
|
||||
const u32 inst_rom_init[] = {
|
||||
0x80000,
|
||||
0x80680,
|
||||
0x8180,
|
||||
0x8200,
|
||||
0x8280,
|
||||
0x8300,
|
||||
0x8380,
|
||||
0x8100,
|
||||
0x8480,
|
||||
0x8500,
|
||||
0x8580,
|
||||
0x8600,
|
||||
0x8400,
|
||||
0x800,
|
||||
0x8680,
|
||||
0x880,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x900,
|
||||
0x80680,
|
||||
0x980,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xb68,
|
||||
0xcce8,
|
||||
0xae8,
|
||||
0x8ce8,
|
||||
0xb88,
|
||||
0xec88,
|
||||
0xa08,
|
||||
0xac88,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x60e80,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x70e80,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0x1158,
|
||||
0x6d8,
|
||||
0x80680,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0x87e8,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0xa7e8,
|
||||
0x80680,
|
||||
0x40e88,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x40f68,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0xa680,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x41008,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x1100,
|
||||
0xc680,
|
||||
0x8680,
|
||||
0xe680,
|
||||
0x80680,
|
||||
0x0,
|
||||
0x8000,
|
||||
0xa000,
|
||||
0xc000,
|
||||
0x80000,
|
||||
0x80,
|
||||
0x8080,
|
||||
0xa080,
|
||||
0xc080,
|
||||
0x80080,
|
||||
0x9180,
|
||||
0x8680,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x40f08,
|
||||
0x80680
|
||||
};
|
||||
|
||||
#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
|
||||
@@ -0,0 +1,98 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <eeprom.h>
|
||||
#include <env.h>
|
||||
#include <init.h>
|
||||
#include <status_led.h>
|
||||
#include <asm/arch/reset_manager.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <i2c.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
int board_late_init(void)
|
||||
{
|
||||
const unsigned int phy_nrst_gpio = 0;
|
||||
const unsigned int usb_nrst_gpio = 35;
|
||||
int ret;
|
||||
|
||||
status_led_set(1, CONFIG_LED_STATUS_ON);
|
||||
status_led_set(2, CONFIG_LED_STATUS_ON);
|
||||
|
||||
/* Address of boot parameters for ATAG (if ATAG is used) */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio");
|
||||
if (!ret)
|
||||
gpio_direction_output(phy_nrst_gpio, 1);
|
||||
else
|
||||
printf("Cannot remove PHY from reset!\n");
|
||||
|
||||
ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio");
|
||||
if (!ret)
|
||||
gpio_direction_output(usb_nrst_gpio, 1);
|
||||
else
|
||||
printf("Cannot remove USB from reset!\n");
|
||||
|
||||
mdelay(50);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
int misc_init_r(void)
|
||||
{
|
||||
uchar data[128];
|
||||
char str[32];
|
||||
u32 serial;
|
||||
int ret;
|
||||
|
||||
/* EEPROM is at address 0x50 (at bus CONFIG_SYS_EEPROM_BUS_NUM). */
|
||||
ret = eeprom_read(0x50, 0, data, sizeof(data));
|
||||
if (ret) {
|
||||
puts("Cannot read I2C EEPROM.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Check EEPROM signature. */
|
||||
if (!(data[0] == 0xa5 && data[1] == 0x5a)) {
|
||||
puts("Invalid I2C EEPROM signature.\n");
|
||||
env_set("unit_serial", "invalid");
|
||||
env_set("unit_ident", "VINing-xxxx-STD");
|
||||
env_set("hostname", "vining-invalid");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* If 'unit_serial' is already set, do nothing. */
|
||||
if (!env_get("unit_serial")) {
|
||||
/* This field is Big Endian ! */
|
||||
serial = (data[0x54] << 24) | (data[0x55] << 16) |
|
||||
(data[0x56] << 8) | (data[0x57] << 0);
|
||||
memset(str, 0, sizeof(str));
|
||||
sprintf(str, "%07i", serial);
|
||||
env_set("unit_serial", str);
|
||||
}
|
||||
|
||||
if (!env_get("unit_ident")) {
|
||||
memset(str, 0, sizeof(str));
|
||||
memcpy(str, &data[0x2e], 18);
|
||||
env_set("unit_ident", str);
|
||||
}
|
||||
|
||||
/* Set ethernet address from EEPROM. */
|
||||
if (!env_get("ethaddr") && is_valid_ethaddr(&data[0x62]))
|
||||
eth_env_set_enetaddr("ethaddr", &data[0x62]);
|
||||
if (!env_get("eth1addr") && is_valid_ethaddr(&data[0x6a]))
|
||||
eth_env_set_enetaddr("eth1addr", &data[0x6a]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user