GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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CLEARFOG BOARD
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M: Stefan Roese <sr@denx.de>
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S: Maintained
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F: board/soldrun/clearfog/
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F: include/configs/clearfog.h
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F: configs/clearfog_defconfig
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F: configs/clearfog_gt_8k_defconfig
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2015 Stefan Roese <sr@denx.de>
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obj-y := clearfog.o
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Update from original Marvell U-Boot to mainline U-Boot:
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-------------------------------------------------------
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Generate the U-Boot image with these commands:
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$ make clearfog_defconfig
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$ make
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The resulting image including the SPL binary with the
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full DDR setup is "u-boot-spl.kwb".
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Now all you need to do is copy this image on a SD card.
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For example with this command:
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$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
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Please use the correct device node for your setup instead
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of "/dev/sdX" here!
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Install U-Boot on eMMC:
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-----------------------
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The ROM loads the bootloader from eMMC first boot partition at offset 0. This
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is unlike load from SD card that is at offset 512. As a result, the offset of
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the main U-Boot image on the eMMC boot partition changes. Set
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x140 for SPL to load U-Boot from
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the correct location.
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To make SPL load the main U-Boot image from the eMMC boot partition enable
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eMMC boot acknowledgement and boot partition with the following U-Boot
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command:
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mmc partconf 0 1 1 0
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Install U-Boot on eMMC boot partition from Linux running on Clearfog:
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echo 0 > /sys/block/mmcblk0boot0/force_ro
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dd if=u-boot-spl.kwb of=/dev/mmcblk0boot0
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Note that the SD card is not accessible when the Clearfog SOM has eMMC.
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Consider initial boot from UART (see below).
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Install U-Boot on SATA:
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-----------------------
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When loading the main U-Boot image from raw SATA sector, set
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CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR to 0x141.
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Boot selection:
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---------------
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Before powering up the board, boot selection should be done via the SW1 dip
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switch (0: OFF, 1: ON):
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- SPI: 00010
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- SD/eMMC: 00111
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- M.2 SSD: 11100
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- UART: 01001 [1]
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[1]: According to SolidRun's manual, 11110 should be used for UART booting on
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the ClearFog 'Pro' variant.
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However, this doesn't work (anymore) at least on Rev. 2.1 (but '01001' as
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mentionend for the 'Base' variant does).
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Boot from UART:
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---------------
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Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5)
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to your host.
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Set the SW1 DIP switches to UART boot (see above).
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Run the following command to initiate U-Boot download:
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./tools/kwboot -b u-boot-spl.kwb /dev/ttyUSBX
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Use the correct UART device node for /dev/ttyUSBX.
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When download finishes start your favorite terminal emulator
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on /dev/ttyUSBX.
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
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#include <../serdes/a38x/high_speed_env_spec.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Those values and defines are taken from the Marvell U-Boot version
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* "u-boot-2013.01-15t1-clearfog"
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*/
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#define BOARD_GPP_OUT_ENA_LOW 0xffffffff
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#define BOARD_GPP_OUT_ENA_MID 0xffffffff
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#define BOARD_GPP_OUT_VAL_LOW 0x0
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#define BOARD_GPP_OUT_VAL_MID 0x0
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#define BOARD_GPP_POL_LOW 0x0
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#define BOARD_GPP_POL_MID 0x0
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static struct serdes_map board_serdes_map[] = {
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{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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};
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int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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{
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*serdes_map_array = board_serdes_map;
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*count = ARRAY_SIZE(board_serdes_map);
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return 0;
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}
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/*
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* Define the DDR layout / topology here in the board file. This will
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* be used by the DDR3 init code in the SPL U-Boot version to configure
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* the DDR3 controller.
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*/
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static struct mv_ddr_topology_map board_topology_map = {
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1600K, /* speed_bin */
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MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
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MV_DDR_DIE_CAP_4GBIT, /* mem_size */
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MV_DDR_FREQ_800, /* frequency */
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0, 0, /* cas_wl cas_l */
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MV_DDR_TEMP_LOW, /* temperature */
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MV_DDR_TIM_DEFAULT} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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};
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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/* Return the board topology as defined in the board code */
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return &board_topology_map;
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}
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(0x11111111, MVEBU_MPP_BASE + 0x00);
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writel(0x11111111, MVEBU_MPP_BASE + 0x04);
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writel(0x10400011, MVEBU_MPP_BASE + 0x08);
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writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
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writel(0x44400002, MVEBU_MPP_BASE + 0x10);
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writel(0x41144004, MVEBU_MPP_BASE + 0x14);
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writel(0x40333333, MVEBU_MPP_BASE + 0x18);
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writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
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/* Set GPP Out value */
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writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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/* Set GPP Polarity */
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writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
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/* Set GPP Out Enable */
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writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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/* Toggle GPIO41 to reset onboard switch and phy */
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clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
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clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
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/* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
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clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
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clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
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mdelay(1);
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setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
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setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
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mdelay(10);
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: SolidRun ClearFog\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis); /* Built in controller(s) come first */
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return pci_eth_init(bis);
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}
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