GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,15 @@
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if TARGET_SPEAR300
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config SYS_BOARD
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default "spear300"
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config SYS_VENDOR
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default "spear"
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config SYS_SOC
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default "spear"
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config SYS_CONFIG_NAME
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default "spear3xx_evb"
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endif
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@@ -0,0 +1,13 @@
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SPEAR300 BOARD
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M: Vipin Kumar <vipin.kumar@st.com>
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S: Maintained
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F: board/spear/spear300/
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F: include/configs/spear3xx_evb.h
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F: configs/spear300_defconfig
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SPEAR300_NAND BOARD
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#M: -
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S: Maintained
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F: configs/spear300_nand_defconfig
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F: configs/spear300_usbtty_defconfig
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F: configs/spear300_usbtty_nand_defconfig
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@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y := spear300.o
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@@ -0,0 +1,60 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <linux/mtd/fsmc_nand.h>
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#include <asm/mach-types.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_defs.h>
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#include <asm/arch/spr_misc.h>
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static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
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int board_init(void)
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{
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return spear_board_init(MACH_TYPE_SPEAR300);
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}
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/*
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* board_nand_init - Board specific NAND initialization
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* @nand: mtd private chip structure
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*
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* Called by nand_init_chip to initialize the board specific functions
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*/
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void board_nand_init()
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{
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struct misc_regs *const misc_regs_p =
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(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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struct nand_chip *nand = &nand_chip[0];
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#if defined(CONFIG_NAND_FSMC)
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if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
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MISC_SOCCFG30) ||
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((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
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MISC_SOCCFG31)) {
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fsmc_nand_init(nand);
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}
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#endif
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return;
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}
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int board_eth_init(bd_t *bis)
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{
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int ret = 0;
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#if defined(CONFIG_ETH_DESIGNWARE)
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u32 interface = PHY_INTERFACE_MODE_MII;
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if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
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ret++;
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#endif
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return ret;
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}
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@@ -0,0 +1,15 @@
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if TARGET_SPEAR310
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config SYS_BOARD
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default "spear310"
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config SYS_VENDOR
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default "spear"
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config SYS_SOC
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default "spear"
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config SYS_CONFIG_NAME
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default "spear3xx_evb"
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endif
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@@ -0,0 +1,15 @@
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SPEAR310 BOARD
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M: Vipin Kumar <vipin.kumar@st.com>
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S: Maintained
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F: board/spear/spear310/
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F: include/configs/spear3xx_evb.h
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F: configs/spear310_defconfig
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SPEAR310_NAND BOARD
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#M: -
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S: Maintained
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F: configs/spear310_nand_defconfig
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F: configs/spear310_pnor_defconfig
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F: configs/spear310_usbtty_defconfig
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F: configs/spear310_usbtty_nand_defconfig
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F: configs/spear310_usbtty_pnor_defconfig
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@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y := spear310.o
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@@ -0,0 +1,78 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <linux/mtd/fsmc_nand.h>
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#include <asm/mach-types.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_defs.h>
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#include <asm/arch/spr_misc.h>
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static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
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int board_init(void)
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{
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return spear_board_init(MACH_TYPE_SPEAR310);
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}
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/*
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* board_nand_init - Board specific NAND initialization
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* @nand: mtd private chip structure
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*
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* Called by nand_init_chip to initialize the board specific functions
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*/
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void board_nand_init()
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{
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struct misc_regs *const misc_regs_p =
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(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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struct nand_chip *nand = &nand_chip[0];
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#if defined(CONFIG_NAND_FSMC)
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if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
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MISC_SOCCFG30) ||
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((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
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MISC_SOCCFG31)) {
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fsmc_nand_init(nand);
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}
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#endif
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return;
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}
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int board_eth_init(bd_t *bis)
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{
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int ret = 0;
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#if defined(CONFIG_ETH_DESIGNWARE)
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u32 interface = PHY_INTERFACE_MODE_MII;
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if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
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ret++;
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#endif
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#if defined(CONFIG_MACB)
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if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
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CONFIG_MACB0_PHY) >= 0)
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ret++;
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if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE,
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CONFIG_MACB1_PHY) >= 0)
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ret++;
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if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE,
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CONFIG_MACB2_PHY) >= 0)
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ret++;
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if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE,
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CONFIG_MACB3_PHY) >= 0)
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ret++;
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#endif
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return ret;
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}
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@@ -0,0 +1,15 @@
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if TARGET_SPEAR320
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config SYS_BOARD
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default "spear320"
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config SYS_VENDOR
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default "spear"
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config SYS_SOC
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default "spear"
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config SYS_CONFIG_NAME
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default "spear3xx_evb"
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endif
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@@ -0,0 +1,15 @@
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SPEAR320 BOARD
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M: Vipin Kumar <vipin.kumar@st.com>
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S: Maintained
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F: board/spear/spear320/
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F: include/configs/spear3xx_evb.h
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F: configs/spear320_defconfig
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SPEAR320_NAND BOARD
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#M: -
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S: Maintained
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F: configs/spear320_nand_defconfig
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F: configs/spear320_pnor_defconfig
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F: configs/spear320_usbtty_defconfig
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F: configs/spear320_usbtty_nand_defconfig
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F: configs/spear320_usbtty_pnor_defconfig
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@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y := spear320.o
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@@ -0,0 +1,77 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <linux/mtd/fsmc_nand.h>
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#include <asm/mach-types.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_defs.h>
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#include <asm/arch/spr_misc.h>
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#define PLGPIO_SEL_36 0xb3000028
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#define PLGPIO_IO_36 0xb3000038
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static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
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static void spear_phy_reset(void)
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{
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writel(0x10, PLGPIO_IO_36);
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writel(0x10, PLGPIO_SEL_36);
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}
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int board_init(void)
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{
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spear_phy_reset();
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return spear_board_init(MACH_TYPE_SPEAR320);
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}
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/*
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* board_nand_init - Board specific NAND initialization
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* @nand: mtd private chip structure
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*
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* Called by nand_init_chip to initialize the board specific functions
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*/
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void board_nand_init()
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{
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struct misc_regs *const misc_regs_p =
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(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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struct nand_chip *nand = &nand_chip[0];
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#if defined(CONFIG_NAND_FSMC)
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if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
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MISC_SOCCFG30) ||
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((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
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MISC_SOCCFG31)) {
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fsmc_nand_init(nand);
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}
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#endif
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return;
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}
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int board_eth_init(bd_t *bis)
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{
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int ret = 0;
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#if defined(CONFIG_ETH_DESIGNWARE)
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u32 interface = PHY_INTERFACE_MODE_MII;
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if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
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ret++;
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#endif
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#if defined(CONFIG_MACB)
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if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
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CONFIG_MACB0_PHY) >= 0)
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ret++;
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#endif
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return ret;
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}
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@@ -0,0 +1,15 @@
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if TARGET_SPEAR600
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config SYS_BOARD
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default "spear600"
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config SYS_VENDOR
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default "spear"
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config SYS_SOC
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default "spear"
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config SYS_CONFIG_NAME
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default "spear6xx_evb"
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endif
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@@ -0,0 +1,13 @@
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SPEAR600 BOARD
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M: Vipin Kumar <vipin.kumar@st.com>
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S: Maintained
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F: board/spear/spear600/
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F: include/configs/spear6xx_evb.h
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F: configs/spear600_defconfig
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SPEAR600_NAND BOARD
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#M: -
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||||
S: Maintained
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F: configs/spear600_nand_defconfig
|
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F: configs/spear600_usbtty_defconfig
|
||||
F: configs/spear600_usbtty_nand_defconfig
|
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@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
||||
obj-y += spear600.o
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||||
@@ -0,0 +1,55 @@
|
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// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <nand.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/mtd/fsmc_nand.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/spr_defs.h>
|
||||
#include <asm/arch/spr_misc.h>
|
||||
|
||||
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return spear_board_init(MACH_TYPE_SPEAR600);
|
||||
}
|
||||
|
||||
/*
|
||||
* board_nand_init - Board specific NAND initialization
|
||||
* @nand: mtd private chip structure
|
||||
*
|
||||
* Called by nand_init_chip to initialize the board specific functions
|
||||
*/
|
||||
|
||||
void board_nand_init()
|
||||
{
|
||||
struct misc_regs *const misc_regs_p =
|
||||
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
|
||||
struct nand_chip *nand = &nand_chip[0];
|
||||
|
||||
#if defined(CONFIG_NAND_FSMC)
|
||||
if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
|
||||
fsmc_nand_init(nand);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
#if defined(CONFIG_ETH_DESIGNWARE)
|
||||
u32 interface = PHY_INTERFACE_MODE_MII;
|
||||
if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
|
||||
ret++;
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
@@ -0,0 +1,18 @@
|
||||
if TARGET_X600
|
||||
|
||||
config SPL_LDSCRIPT
|
||||
default "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
|
||||
|
||||
config SYS_BOARD
|
||||
default "x600"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "spear"
|
||||
|
||||
config SYS_SOC
|
||||
default "spear"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "x600"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
X600 BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/spear/x600/
|
||||
F: include/configs/x600.h
|
||||
F: configs/x600_defconfig
|
||||
@@ -0,0 +1,11 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
# necessary to create built-in.o
|
||||
obj- := __dummy__.o
|
||||
else
|
||||
obj-y := fpga.o x600.o
|
||||
endif
|
||||
@@ -0,0 +1,263 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spartan3.h>
|
||||
#include <command.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/spr_misc.h>
|
||||
#include <asm/arch/spr_ssp.h>
|
||||
|
||||
/*
|
||||
* FPGA program pin configuration on X600:
|
||||
*
|
||||
* Only PROG and DONE are connected to GPIOs. INIT is not connected to the
|
||||
* SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
|
||||
* 16bit serial writes via this SSP port to write the data bits into the
|
||||
* FPGA.
|
||||
*/
|
||||
#define CONFIG_SYS_FPGA_PROG 2
|
||||
#define CONFIG_SYS_FPGA_DONE 3
|
||||
|
||||
/*
|
||||
* Set the active-low FPGA reset signal.
|
||||
*/
|
||||
static void fpga_reset(int assert)
|
||||
{
|
||||
/*
|
||||
* On x600 we have no means to toggle the FPGA reset signal
|
||||
*/
|
||||
debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the FPGA's active-low SelectMap program line to the specified level
|
||||
*/
|
||||
static int fpga_pgm_fn(int assert, int flush, int cookie)
|
||||
{
|
||||
debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
|
||||
|
||||
gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
|
||||
|
||||
return assert;
|
||||
}
|
||||
|
||||
/*
|
||||
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
|
||||
* asserted (low).
|
||||
*/
|
||||
static int fpga_init_fn(int cookie)
|
||||
{
|
||||
static int state;
|
||||
|
||||
debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
|
||||
|
||||
/*
|
||||
* On x600, the FPGA INIT signal is not connected to the SoC.
|
||||
* We can't read the INIT status. Let's return the "correct"
|
||||
* INIT signal state generated via a local state-machine.
|
||||
*/
|
||||
if (++state == 1) {
|
||||
return 1;
|
||||
} else {
|
||||
state = 0;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Test the state of the active-high FPGA DONE pin
|
||||
*/
|
||||
static int fpga_done_fn(int cookie)
|
||||
{
|
||||
struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
|
||||
|
||||
/*
|
||||
* Wait for Tx-FIFO to become empty before looking for DONE
|
||||
*/
|
||||
while (!(readl(&ssp->sspsr) & SSPSR_TFE))
|
||||
;
|
||||
|
||||
if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* FPGA pre-configuration function. Just make sure that
|
||||
* FPGA reset is asserted to keep the FPGA from starting up after
|
||||
* configuration.
|
||||
*/
|
||||
static int fpga_pre_config_fn(int cookie)
|
||||
{
|
||||
debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
|
||||
fpga_reset(true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* FPGA post configuration function. Blip the FPGA reset line and then see if
|
||||
* the FPGA appears to be running.
|
||||
*/
|
||||
static int fpga_post_config_fn(int cookie)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
|
||||
|
||||
fpga_reset(true);
|
||||
udelay(100);
|
||||
fpga_reset(false);
|
||||
udelay(100);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int fpga_clk_fn(int assert_clk, int flush, int cookie)
|
||||
{
|
||||
/*
|
||||
* No dedicated clock signal on x600 (data & clock generated)
|
||||
* in SSP interface. So we don't have to do anything here.
|
||||
*/
|
||||
return assert_clk;
|
||||
}
|
||||
|
||||
static int fpga_wr_fn(int assert_write, int flush, int cookie)
|
||||
{
|
||||
struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
|
||||
static int count;
|
||||
static u16 data;
|
||||
|
||||
/*
|
||||
* First collect 16 bits of data
|
||||
*/
|
||||
data = data << 1;
|
||||
if (assert_write)
|
||||
data |= 1;
|
||||
|
||||
/*
|
||||
* If 16 bits are not available, return for more bits
|
||||
*/
|
||||
count++;
|
||||
if (count != 16)
|
||||
return assert_write;
|
||||
|
||||
count = 0;
|
||||
|
||||
/*
|
||||
* Wait for Tx-FIFO to become ready
|
||||
*/
|
||||
while (!(readl(&ssp->sspsr) & SSPSR_TNF))
|
||||
;
|
||||
|
||||
/* Send 16 bits to FPGA via SSP bus */
|
||||
writel(data, &ssp->sspdr);
|
||||
|
||||
return assert_write;
|
||||
}
|
||||
|
||||
static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
|
||||
fpga_pre_config_fn,
|
||||
fpga_pgm_fn,
|
||||
fpga_clk_fn,
|
||||
fpga_init_fn,
|
||||
fpga_done_fn,
|
||||
fpga_wr_fn,
|
||||
fpga_post_config_fn,
|
||||
};
|
||||
|
||||
static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
|
||||
XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize the SelectMap interface. We assume that the mode and the
|
||||
* initial state of all of the port pins have already been set!
|
||||
*/
|
||||
static void fpga_serialslave_init(void)
|
||||
{
|
||||
debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
|
||||
fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
|
||||
}
|
||||
|
||||
static int expi_setup(int freq)
|
||||
{
|
||||
struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
|
||||
int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
|
||||
|
||||
pll2_m = (freq * 2) / 1000;
|
||||
pll2_n = 15;
|
||||
pll2_p = 1;
|
||||
expi_x = 1;
|
||||
expi_y = 2;
|
||||
|
||||
/*
|
||||
* Disable reset, Low compression, Disable retiming, Enable Expi,
|
||||
* Enable soft reset, DMA, PLL2, Internal
|
||||
*/
|
||||
writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
|
||||
EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
|
||||
EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
|
||||
&misc->expi_clk_cfg);
|
||||
|
||||
/*
|
||||
* 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
|
||||
* Enable PLL2, Disable reset
|
||||
*/
|
||||
writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
|
||||
writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
|
||||
PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
|
||||
|
||||
/*
|
||||
* Disable soft reset
|
||||
*/
|
||||
clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the fpga
|
||||
*/
|
||||
int x600_init_fpga(void)
|
||||
{
|
||||
struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
|
||||
struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
|
||||
|
||||
/* Enable SSP2 clock */
|
||||
writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
|
||||
&misc->periph1_clken);
|
||||
|
||||
/* Set EXPI clock to 45 MHz */
|
||||
expi_setup(45000);
|
||||
|
||||
/* Configure GPIO directions */
|
||||
gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
|
||||
gpio_direction_input(CONFIG_SYS_FPGA_DONE);
|
||||
|
||||
writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
|
||||
writel(SSPCR1_SSE, &ssp->sspcr1);
|
||||
|
||||
/*
|
||||
* Set lowest prescale divisor value (CPSDVSR) of 2 for max download
|
||||
* speed.
|
||||
*
|
||||
* Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
|
||||
* With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
|
||||
*/
|
||||
writel(2, &ssp->sspcpsr);
|
||||
|
||||
fpga_init();
|
||||
fpga_serialslave_init();
|
||||
|
||||
debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
|
||||
fpga_add(fpga_xilinx, &fpga[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
int x600_init_fpga(void);
|
||||
@@ -0,0 +1,148 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
||||
*
|
||||
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <micrel.h>
|
||||
#include <nand.h>
|
||||
#include <netdev.h>
|
||||
#include <phy.h>
|
||||
#include <rtc.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/spr_defs.h>
|
||||
#include <asm/arch/spr_misc.h>
|
||||
#include <linux/mtd/fsmc_nand.h>
|
||||
#include "fpga.h"
|
||||
|
||||
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/*
|
||||
* X600 is equipped with an M41T82 RTC. This RTC has the
|
||||
* HT bit (Halt Update), which needs to be cleared upon
|
||||
* power-up. Otherwise the RTC is halted.
|
||||
*/
|
||||
rtc_reset();
|
||||
|
||||
return spear_board_init(MACH_TYPE_SPEAR600);
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
/*
|
||||
* Monitor and env protection on by default
|
||||
*/
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
|
||||
CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
|
||||
2 * CONFIG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
/* Init FPGA subsystem */
|
||||
x600_init_fpga();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* board_nand_init - Board specific NAND initialization
|
||||
* @nand: mtd private chip structure
|
||||
*
|
||||
* Called by nand_init_chip to initialize the board specific functions
|
||||
*/
|
||||
|
||||
void board_nand_init(void)
|
||||
{
|
||||
struct misc_regs *const misc_regs_p =
|
||||
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
|
||||
struct nand_chip *nand = &nand_chip[0];
|
||||
|
||||
if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
|
||||
fsmc_nand_init(nand);
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
unsigned short id1, id2;
|
||||
|
||||
/* check whether KSZ9031 or AR8035 has to be configured */
|
||||
id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
|
||||
id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
|
||||
|
||||
if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
|
||||
/* PHY configuration for Micrel KSZ9031 */
|
||||
printf("PHY KSZ9031 detected - ");
|
||||
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
|
||||
|
||||
/* control data pad skew - devaddr = 0x02, register = 0x04 */
|
||||
ksz9031_phy_extended_write(phydev, 0x02,
|
||||
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
0x0000);
|
||||
/* rx data pad skew - devaddr = 0x02, register = 0x05 */
|
||||
ksz9031_phy_extended_write(phydev, 0x02,
|
||||
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
0x0000);
|
||||
/* tx data pad skew - devaddr = 0x02, register = 0x05 */
|
||||
ksz9031_phy_extended_write(phydev, 0x02,
|
||||
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
0x0000);
|
||||
/* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */
|
||||
ksz9031_phy_extended_write(phydev, 0x02,
|
||||
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
0x03FF);
|
||||
} else {
|
||||
/* PHY configuration for Vitesse VSC8641 */
|
||||
printf("PHY VSC8641 detected - ");
|
||||
|
||||
/* Extended PHY control 1, select GMII */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
|
||||
|
||||
/* Software reset necessary after GMII mode selction */
|
||||
phy_reset(phydev);
|
||||
|
||||
/* Enable extended page register access */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
|
||||
|
||||
/* 17e: Enhanced LED behavior, needs to be written twice */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
|
||||
|
||||
/* 16e: Enhanced LED method select */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
|
||||
|
||||
/* Disable extended page register access */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
|
||||
|
||||
/* Enable clock output pin */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
|
||||
}
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (designware_initialize(CONFIG_SPEAR_ETHBASE,
|
||||
PHY_INTERFACE_MODE_GMII) >= 0)
|
||||
ret++;
|
||||
|
||||
return ret;
|
||||
}
|
||||
Reference in New Issue
Block a user