GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Soeren Moch <smoch@web.de>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/video.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart2_pads[] = {
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MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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int dram_init(void)
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{
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gd->ram_size = 2048ul * 1024 * 1024;
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
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}
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#ifdef CONFIG_FSL_ESDHC_IMX
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/* set environment device to boot device when booting from SD */
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int board_mmc_get_env_dev(int devno)
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{
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return devno - 1;
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}
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int board_mmc_get_env_part(int devno)
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{
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return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
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}
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#endif /* CONFIG_FSL_ESDHC_IMX */
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#ifdef CONFIG_VIDEO_IPUV3
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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struct display_info_t const displays[] = {{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = do_enable_hdmi,
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.mode = {
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.name = "HDMI",
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/* 1024x768@60Hz (VESA)*/
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15384,
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.left_margin = 160,
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.right_margin = 24,
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.upper_margin = 29,
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.lower_margin = 3,
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.hsync_len = 136,
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.vsync_len = 6,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} } };
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size_t display_count = ARRAY_SIZE(displays);
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static void setup_display(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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s32 timeout = 100000;
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enable_ipu_clock();
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imx_setup_hdmi();
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/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
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reg = readl(&ccm->analog_pll_video);
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reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
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writel(reg, &ccm->analog_pll_video);
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reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
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reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
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reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
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reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
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writel(reg, &ccm->analog_pll_video);
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writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
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writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
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reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
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writel(reg, &ccm->analog_pll_video);
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while (timeout--)
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if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
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break;
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if (timeout < 0)
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printf("Warning: video pll lock timeout!\n");
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reg = readl(&ccm->analog_pll_video);
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reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
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reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
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writel(reg, &ccm->analog_pll_video);
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/* gate ipu1_di0_clk */
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reg = readl(&ccm->CCGR3);
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reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
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writel(reg, &ccm->CCGR3);
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/* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
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reg = readl(&ccm->chsccdr);
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reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
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MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
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reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
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(6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
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(0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(reg, &ccm->chsccdr);
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/* enable ipu1_di0_clk */
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reg = readl(&ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
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writel(reg, &ccm->CCGR3);
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
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{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
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/* 8 bit bus width */
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{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_VIDEO_IPUV3
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setup_display();
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#endif
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#ifdef CONFIG_CMD_BMODE
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add_board_boot_modes(board_boot_modes);
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#endif
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return 0;
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}
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