GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,15 @@
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if TARGET_PICO_IMX6UL
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config SYS_BOARD
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default "pico-imx6ul"
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config SYS_VENDOR
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default "technexion"
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config SYS_SOC
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default "mx6"
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config SYS_CONFIG_NAME
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default "pico-imx6ul"
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endif
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@@ -0,0 +1,10 @@
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TechNexion PICO-IMX6UL board
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M: Richard Hu <richard.hu@technexion.com>
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M: Fabio Estevam <fabio.estevam@nxp.com>
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S: Maintained
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F: board/technexion/pico-imx6ul/
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F: include/configs/pico-imx6ul.h
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F: configs/pico-imx6ul_defconfig
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F: configs/pico-dwarf-imx6ul_defconfig
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F: configs/pico-hobbit-imx6ul_defconfig
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F: configs/pico-pi-imx6ul_defconfig
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@@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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# (C) Copyright 2015 Technexion Ltd.
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# (C) Copyright 2015 Freescale Semiconductor, Inc.
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obj-y := pico-imx6ul.o spl.o
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@@ -0,0 +1,159 @@
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How to Update U-Boot on Pico-imx6ul board
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-----------------------------------------
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Required software on the host PC:
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- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
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- dfu-util: http://dfu-util.sourceforge.net/releases/
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Build U-Boot for Pico:
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$ make mrproper
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$ make pico-imx6ul_defconfig
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$ make
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This generates the SPL and u-boot-dtb.img binaries.
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1. Loading U-Boot via USB Serial Download Protocol
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Note: This method is convenient for development purposes.
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If the eMMC has already a U-Boot flashed with DFU support then
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the user can go to step 2 below in order to update U-Boot.
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Put pico board in USB download mode (refer to the document
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http://www.wandboard.org/images/hobbit/hobbitboard-imx6ul-reva1.pdf
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page 15).
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Connect a USB to serial adapter between the host PC and pico.
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Connect a USB cable between the OTG pico port and the host PC.
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Open a terminal program such as minicom.
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Copy SPL and u-boot-dtb.img to the imx_usb_loader folder.
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Load the SPL binary via USB:
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$ sudo ./imx_usb SPL
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Load the u-boot-dtb.img binary via USB:
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$ sudo ./imx_usb u-boot-dtb.img
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Then U-Boot starts and its messages appear in the console program.
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Use the default environment variables:
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=> env default -f -a
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=> saveenv
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2. Flashing U-Boot into the eMMC
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Run the DFU agent so we can flash the new images using dfu-util tool:
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=> dfu 0 mmc 0
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Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC:
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$ sudo dfu-util -D SPL -a spl
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$ sudo dfu-util -D u-boot-dtb.img -a u-boot
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Remove power from the pico board.
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Put pico board into normal boot mode.
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Power up the board and the new updated U-Boot should boot from eMMC.
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Booting in Falcon mode
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======================
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Generate a uImage kernel:
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$ make imx_v6_v7_defconfig (Using the default imx_v6_v7_defconfig configuration
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just for an example. In order to boot faster the user should customize the
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defconfig by only enabling the minimal required drivers).
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$ make -j4 uImage LOADADDR=0x80008000
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$ cp arch/arm/boot/uImage /tftpboot
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$ cp arch/arm/boot/dts/imx6ul-pico-hobbit.dtb /tftpboot
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In the U-Boot prompt:
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Setup the server and board IP addresses:
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=> setenv serverip 192.168.0.10
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=> setenv ipaddr 192.168.0.11
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Get the dtb file:
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=> tftp ${fdt_addr} imx6ul-pico-hobbit.dtb
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Get the kernel:
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=> tftp ${loadaddr} uImage
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Write the kernel at 2MB offset:
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=> mmc write ${loadaddr} 0x1000 0x5000
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Setup the bootargs:
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=> setenv bootargs 'console=ttymxc5,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait rw'
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Prepare args:
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=> spl export fdt ${loadaddr} - ${fdt_addr}
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## Booting kernel from Legacy Image at 82000000 ...
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Image Name: Linux-4.19.0-rc2-next-20180905-0
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Image Type: ARM Linux Kernel Image (uncompressed)
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Data Size: 8365608 Bytes = 8 MiB
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Load Address: 80008000
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Entry Point: 80008000
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Verifying Checksum ... OK
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## Flattened Device Tree blob at 83000000
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Booting using the fdt blob at 0x83000000
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Loading Kernel Image ... OK
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Using Device Tree in place at 83000000, end 83009c63
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subcommand not supported
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subcommand not supported
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Using Device Tree in place at 83000000, end 8300cc63
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Argument image is now in RAM: 0x83000000
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Write 1MB of args data (0x800 sectors) to 1MB offset (0x800 sectors):
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=> mmc write ${fdt_addr} 0x800 0x800
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In order to boot with Falcon mode, activate the CONFIG_SPL_OS_BOOT
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option in the defconfig
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--- a/configs/pico-hobbit-imx6ul_defconfig
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+++ b/configs/pico-hobbit-imx6ul_defconfig
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@@ -53,3 +53,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
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CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
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CONFIG_CI_UDC=y
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CONFIG_OF_LIBFDT=y
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+CONFIG_SPL_OS_BOOT=y
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Then rebuild U-Boot:
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$ make pico-hobbit-imx6ul_defconfig
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$ make -j4
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Launch UMS:
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=> ums 0 mmc 0
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Flash the new binaries:
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$ sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync
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$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1k seek=69; sync
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And then SPL binary will load and jump directly to the kernel:
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U-Boot SPL 2018.09-rc2-00156-g8c46f15-dirty (Sep 05 2018 - 16:24:05 -0300)
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Trying to boot from MMC1
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[ 0.000000] Booting Linux on physical CPU 0x0
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[ 0.000000] Linux version 4.19.0-rc2-next-20180905-00001-gb805e2d (fabio@fabio-Latitude-E5450) (gcc version 5.4.0 20160609 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9)) #533 SMP Wed Sep 5 16:21:03 -03 2018
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[ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
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[ 0.000000] CPU: div instructions available: patching division code
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[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
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[ 0.000000] OF: fdt: Machine model: Technexion Pico i.MX6UL Board
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[ 0.000000] Memory policy: Data cache writealloc
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[ 0.000000] cma: Reserved 64 MiB at 0x8c000000
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...
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@@ -0,0 +1,96 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi/sd/nand/onenand, qspi/nor
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* Enable all clocks */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020E04B4 0x000C0000
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DATA 4 0x020E04AC 0x00000000
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DATA 4 0x020E027C 0x00000030
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DATA 4 0x020E0250 0x00000030
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DATA 4 0x020E024C 0x00000030
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DATA 4 0x020E0490 0x00000030
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DATA 4 0x020E0288 0x00000030
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DATA 4 0x020E0270 0x00000000
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DATA 4 0x020E0260 0x00000030
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DATA 4 0x020E0264 0x00000030
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DATA 4 0x020E04A0 0x00000030
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DATA 4 0x020E0494 0x00020000
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DATA 4 0x020E0280 0x00000030
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DATA 4 0x020E0284 0x00000030
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DATA 4 0x020E04B0 0x00020000
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DATA 4 0x020E0498 0x00000030
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DATA 4 0x020E04A4 0x00000030
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DATA 4 0x020E0244 0x00000030
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DATA 4 0x020E0248 0x00000030
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DATA 4 0x021B001C 0x00008000
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DATA 4 0x021B0800 0xA1390003
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DATA 4 0x021B080C 0x00000000
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DATA 4 0x021B083C 0x01380134
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DATA 4 0x021B0848 0x40404244
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DATA 4 0x021B0850 0x40405050
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DATA 4 0x021B081C 0x33333333
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DATA 4 0x021B0820 0x33333333
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DATA 4 0x021B082C 0xf3333333
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DATA 4 0x021B0830 0xf3333333
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DATA 4 0x021B08C0 0x00921012
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DATA 4 0x021B08b8 0x00000800
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DATA 4 0x021B0004 0x0002002D
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DATA 4 0x021B0008 0x00333030
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DATA 4 0x021B000C 0x676B52F3
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DATA 4 0x021B0010 0xB66D8B63
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DATA 4 0x021B0014 0x01FF00DB
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DATA 4 0x021B0018 0x00201740
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DATA 4 0x021B001C 0x00008000
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DATA 4 0x021B002C 0x000026D2
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DATA 4 0x021B0030 0x006B1023
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DATA 4 0x021B0040 0x00000047
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DATA 4 0x021B0000 0x83180000
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DATA 4 0x021B001C 0x02008032
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DATA 4 0x021B001C 0x00008033
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DATA 4 0x021B001C 0x00048031
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DATA 4 0x021B001C 0x15208030
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DATA 4 0x021B001C 0x04008040
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DATA 4 0x021B0020 0x00000800
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DATA 4 0x021B0818 0x00000227
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DATA 4 0x021B0004 0x0002552D
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DATA 4 0x021B0404 0x00011006
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DATA 4 0x021B001C 0x00000000
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@@ -0,0 +1,279 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Technexion Ltd.
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*
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* Author: Richard Hu <richard.hu@technexion.com>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <linux/sizes.h>
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#include <usb.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../../freescale/common/pfuze.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
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#define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
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static iomux_v3_cfg_t const fec_pads[] = {
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MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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int board_eth_init(bd_t *bis)
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{
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setup_iomux_fec();
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gpio_request(RMII_PHY_RESET, "enet_phy_reset");
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gpio_direction_output(RMII_PHY_RESET, 0);
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/*
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* According to KSZ8081MNX-RNB manual:
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* For warm reset, the reset (RST#) pin should be asserted low for a
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* minimum of 500μs. The strap-in pin values are read and updated
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* at the de-assertion of reset.
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*/
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udelay(500);
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gpio_direction_output(RMII_PHY_RESET, 1);
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/*
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* According to KSZ8081MNX-RNB manual:
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* After the de-assertion of reset, wait a minimum of 100μs before
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* starting programming on the MIIM (MDC/MDIO) interface.
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*/
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udelay(100);
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return fecmxc_initialize(bis);
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}
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static int setup_fec(void)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
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IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
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ret = enable_fec_anatop_clock(1, ENET_50MHZ);
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if (ret)
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return ret;
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enable_enet_clk(1);
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return 0;
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}
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#ifdef CONFIG_VIDEO_MXS
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static iomux_v3_cfg_t const lcd_pads[] = {
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MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
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MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
/* LCD_BLT_CTRL: GPIO for Brightness adjustment */
|
||||
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* LCD_VDD_EN: LCD enabled */
|
||||
MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
void setup_lcd(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
gpio_request(IMX_GPIO_NR(4, 10), "lcd_brightness");
|
||||
gpio_request(IMX_GPIO_NR(1, 11), "lcd_enable");
|
||||
/* Set Brightness to high */
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 10) , 1);
|
||||
/* Set LCD enable to high */
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = imx_ddr_size();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const uart6_pads[] = {
|
||||
MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define USB_OTHERREGS_OFFSET 0x800
|
||||
#define UCTRL_PWR_POL (1 << 9)
|
||||
|
||||
static iomux_v3_cfg_t const usb_otg_pad[] = {
|
||||
MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
|
||||
}
|
||||
|
||||
static void setup_usb(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DM_PMIC
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret, dev_id, rev_id;
|
||||
|
||||
ret = pmic_get("pfuze3000", &dev);
|
||||
if (ret == -ENODEV)
|
||||
return 0;
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
|
||||
rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
|
||||
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
|
||||
|
||||
/* disable Low Power Mode during standby mode */
|
||||
pmic_reg_write(dev, PFUZE3000_LDOGCTL, 0x1);
|
||||
|
||||
/* SW1B step ramp up time from 2us to 4us/25mV */
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
|
||||
|
||||
/* SW1B mode to APS/PFM */
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
|
||||
|
||||
/* SW1B standby voltage set to 0.975V */
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
if (port == 1)
|
||||
return USB_INIT_HOST;
|
||||
else
|
||||
return USB_INIT_DEVICE;
|
||||
}
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
u32 *usbnc_usb_ctrl;
|
||||
|
||||
if (port > 1)
|
||||
return -EINVAL;
|
||||
|
||||
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
||||
port * 4);
|
||||
|
||||
/* Set Power polarity */
|
||||
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
setup_fec();
|
||||
setup_usb();
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
setup_lcd();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: PICO-IMX6UL-EMMC\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,182 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/mx6ul_pins.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <spl.h>
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* Break into full U-Boot on 'c' */
|
||||
if (serial_tstc() && serial_getc() == 'c')
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
|
||||
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
|
||||
.grp_addds = 0x00000030,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
.grp_b0ds = 0x00000030,
|
||||
.grp_ctlds = 0x00000030,
|
||||
.grp_b1ds = 0x00000030,
|
||||
.grp_ddrpke = 0x00000000,
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_ddr_type = 0x00080000,
|
||||
};
|
||||
|
||||
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
|
||||
.dram_dqm0 = 0x00000030,
|
||||
.dram_dqm1 = 0x00000030,
|
||||
.dram_ras = 0x00000030,
|
||||
.dram_cas = 0x00000030,
|
||||
.dram_odt0 = 0x00000030,
|
||||
.dram_odt1 = 0x00000030,
|
||||
.dram_sdba2 = 0x00000000,
|
||||
.dram_sdclk_0 = 0x00000030,
|
||||
.dram_sdqs0 = 0x00000030,
|
||||
.dram_sdqs1 = 0x00000030,
|
||||
.dram_reset = 0x00000030,
|
||||
};
|
||||
|
||||
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
||||
.p0_mpwldectrl0 = 0x00000000,
|
||||
.p0_mpdgctrl0 = 0x01380134,
|
||||
.p0_mprddlctl = 0x40404244,
|
||||
.p0_mpwrdlctl = 0x40405050,
|
||||
};
|
||||
|
||||
static struct mx6_ddr_sysinfo ddr_sysinfo = {
|
||||
.dsize = 0,
|
||||
.cs1_mirror = 0,
|
||||
.cs_density = 32,
|
||||
.ncs = 1,
|
||||
.bi_on = 1,
|
||||
.rtt_nom = 1,
|
||||
.rtt_wr = 0,
|
||||
.ralat = 5,
|
||||
.walat = 0,
|
||||
.mif3_mode = 3,
|
||||
.rst_to_cke = 0x23,
|
||||
.sde_to_rst = 0x10,
|
||||
.refsel = 1,
|
||||
.refr = 3,
|
||||
};
|
||||
|
||||
static struct mx6_ddr3_cfg mem_ddr = {
|
||||
.mem_speed = 1333,
|
||||
.density = 2,
|
||||
.width = 16,
|
||||
.banks = 8,
|
||||
.coladdr = 10,
|
||||
.pagesz = 2,
|
||||
.trcd = 1350,
|
||||
.trcmin = 4950,
|
||||
.trasmin = 3600,
|
||||
};
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
writel(0xFFFFFFFF, &ccm->CCGR0);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR1);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR2);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR3);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR4);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR5);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR6);
|
||||
}
|
||||
|
||||
static void imx6ul_spl_dram_cfg_size(u32 ram_size)
|
||||
{
|
||||
if (ram_size == SZ_256M)
|
||||
mem_ddr.rowaddr = 14;
|
||||
else
|
||||
mem_ddr.rowaddr = 15;
|
||||
|
||||
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
||||
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
||||
}
|
||||
|
||||
static void imx6ul_spl_dram_cfg(void)
|
||||
{
|
||||
ulong ram_size_test, ram_size = 0;
|
||||
|
||||
for (ram_size = SZ_512M; ram_size >= SZ_256M; ram_size >>= 1) {
|
||||
imx6ul_spl_dram_cfg_size(ram_size);
|
||||
ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
|
||||
if (ram_size_test == ram_size)
|
||||
break;
|
||||
}
|
||||
|
||||
if (ram_size < SZ_256M) {
|
||||
puts("ERROR: DRAM size detection failed\n");
|
||||
hang();
|
||||
}
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
ccgr_init();
|
||||
arch_cpu_init();
|
||||
board_early_init_f();
|
||||
timer_init();
|
||||
preloader_console_init();
|
||||
imx6ul_spl_dram_cfg();
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
static iomux_v3_cfg_t const usdhc1_pads[] = {
|
||||
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
||||
{USDHC1_BASE_ADDR},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user