GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,15 @@
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if TARGET_PICO_IMX7D
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config SYS_BOARD
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default "pico-imx7d"
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config SYS_VENDOR
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default "technexion"
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config SYS_SOC
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default "mx7"
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config SYS_CONFIG_NAME
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default "pico-imx7d"
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endif
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@@ -0,0 +1,12 @@
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TechNexion PICO-IMX7D board
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M: Vanessa Maegima <vanessa.maegima@nxp.com>
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M: Otavio Salvador <otavio@ossystems.com.br>
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S: Maintained
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F: board/technexion/pico-imx7d/
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F: include/configs/pico-imx7d.h
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F: configs/pico-imx7d_defconfig
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F: configs/pico-imx7d_bl33_defconfig
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F: configs/pico-hobbit-imx7d_defconfig
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F: configs/pico-pi-imx7d_defconfig
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F: configs/pico-nymph-imx7d_defconfig
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F: configs/pico-dwarf-imx7d_defconfig
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@@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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# (C) Copyright 2017 NXP Semiconductors
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obj-y := pico-imx7d.o spl.o
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@@ -0,0 +1,159 @@
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How to update U-Boot on pico-imx7d board
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----------------------------------------
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Required software on the host PC:
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- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
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Build U-Boot for pico:
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$ make mrproper
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$ make pico-imx7d_defconfig
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$ make
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This generates the SPL and u-boot-dtb.img binaries.
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1. Loading U-Boot via USB Serial Download Protocol
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Note: This method is convenient for development purposes.
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If the eMMC has already a U-Boot flashed with DFU support then
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the user can go to step 2 below in order to update U-Boot.
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Put pico board in USB download mode (refer to the PICO-iMX7D Quick Start Guide
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page 3)
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Connect a USB to serial adapter between the host PC and pico.
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Connect a USB cable between the OTG pico port and the host PC.
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Note: Some computers may be a bit strict with USB current draw and will
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shut down their ports if the draw is too high. The solution for that is
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to use an externally powered USB hub between the board and the host computer.
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Open a terminal program such as minicom.
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Copy SPL and u-boot-dtb.img to the imx_usb_loader folder.
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Load the SPL binary via USB:
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$ sudo ./imx_usb SPL
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Load the u-boot-dtb.img binary via USB:
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$ sudo ./imx_usb u-boot-dtb.img
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Then U-Boot starts and its messages appear in the console program.
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Use the default environment variables:
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=> env default -f -a
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=> saveenv
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2. Flashing U-Boot into the eMMC
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Run the DFU agent so we can flash the new images using dfu-util tool:
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=> dfu 0 mmc 0
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Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC:
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$ sudo dfu-util -D SPL -a spl
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$ sudo dfu-util -D u-boot-dtb.img -a u-boot
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Remove power from the pico board.
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Put pico board into normal boot mode.
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Power up the board and the new updated U-Boot should boot from eMMC.
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Booting in Falcon mode
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======================
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Generate a uImage kernel:
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$ make imx_v6_v7_defconfig (Using the default imx_v6_v7_defconfig configuration
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just for an example. In order to boot faster the user should customize the
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defconfig by only enabling the minimal required drivers).
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$ make -j4 uImage LOADADDR=0x80008000
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$ cp arch/arm/boot/uImage /tftpboot
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$ cp arch/arm/boot/dts/imx7d-pico-pi.dtb /tftpboot
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In the U-Boot prompt:
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Setup the server and board IP addresses:
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=> setenv serverip 192.168.0.10
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=> setenv ipaddr 192.168.0.11
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Get the dtb file:
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=> tftp ${fdt_addr} imx7d-pico-pi.dtb
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Get the kernel:
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=> tftp ${loadaddr} uImage
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Write the kernel at 2MB offset:
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=> mmc write ${loadaddr} 0x1000 0x5000
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Setup the bootargs:
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=> setenv bootargs 'console=ttymxc4,115200 root=/dev/mmcblk2p1 rootfstype=ext4 rootwait rw'
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Prepare args:
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=> spl export fdt ${loadaddr} - ${fdt_addr}
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## Booting kernel from Legacy Image at 80800000 ...
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Image Name: Linux-5.2.14
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Image Type: ARM Linux Kernel Image (uncompressed)
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Data Size: 9077544 Bytes = 8.7 MiB
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Load Address: 80008000
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Entry Point: 80008000
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Verifying Checksum ... OK
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## Flattened Device Tree blob at 83000000
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Booting using the fdt blob at 0x83000000
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Loading Kernel Image
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Using Device Tree in place at 83000000, end 8300b615
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subcommand not supported
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subcommand not supported
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Using Device Tree in place at 83000000, end 8300e615
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Argument image is now in RAM: 0x83000000
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=>
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Write 1MB of args data (0x800 sectors) to 1MB offset (0x800 sectors):
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=> mmc write ${fdt_addr} 0x800 0x800
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In order to boot with Falcon mode, activate the CONFIG_SPL_OS_BOOT
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option in the defconfig
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--- a/configs/pico-imx7d_defconfig
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+++ b/configs/pico-imx7d_defconfig
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@@ -67,3 +67,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
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CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
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CONFIG_CI_UDC=y
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CONFIG_VIDEO=y
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+CONFIG_SPL_OS_BOOT=y
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Then rebuild U-Boot:
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$ make pico-imx7d_defconfig
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$ make -j4
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Launch UMS:
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=> ums 0 mmc 0
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Flash the new binaries:
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$ sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync
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$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1k seek=69; sync
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And then SPL binary will load and jump directly to the kernel:
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U-Boot SPL 2019.10-rc3-00284-g001c8ea94a-dirty (Sep 10 2019 - 12:46:01 -0300)
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Trying to boot from MMC1
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[ 0.000000] Booting Linux on physical CPU 0x0
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[ 0.000000] Linux version 5.2.14 (fabio@fabio-OptiPlex-7010) (gcc version 7.4.0 (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1)) #30 SMP Wed Sep 10 12:36:27 -03 2019
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[ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
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[ 0.000000] CPU: div instructions available: patching division code
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[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
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[ 0.000000] OF: fdt: Machine model: TechNexion PICO-IMX7D Board and PI baseboard
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...
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@@ -0,0 +1,44 @@
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This document describes the instruction to build and flash ATF/OPTEE/U-Boot on
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pico-imx7d board. U-Boot is loaded as part of FIP image by ATF in this setup.
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The boot sequence is ATF -> OPTEE -> U-Boot -> Linux. U-Boot is in non-secure
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world in this case.
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- Build u-boot
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Set environment variable of CROSS_COMPILE for your toolchain and ARCH=arm
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$ make pico-imx7d_bl33_defconfig
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$ make all
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- Download and build OPTEE
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$ git clone git@github.com:OP-TEE/optee_os.git
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$ make PLATFORM=imx PLATFORM_FLAVOR=mx7dpico_mbl CFG_BOOT_SECONDARY_REQUEST=y ARCH=arm
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- Download and build ATF
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$ git clone https://git.linaro.org/landing-teams/working/mbl/arm-trusted-firmware.git -b linaro-imx7
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$ make DEBUG=1 PLAT=picopi ARCH=aarch32 ARM_ARCH_MAJOR=7 \
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CROSS_COMPILE=arm-linux-gnueabihf- LOG_LEVEL=50 V=1 \
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CRASH_REPORTING=1 AARCH32_SP=optee all
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Save file content in this link to file pico-imx7d.cfg:
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http://git.linaro.org/landing-teams/working/mbl/u-boot.git/tree/board/technexion/pico-imx7d/pico-imx7d.cfg?h=linaro-imx
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$ u-boot/tools/mkimage -n pico-imx7d.cfg -T imximage -e 0x9df00000 -d \
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build/picopi/debug/bl2.bin bl2.imx
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- Create FIP image
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Create a fiptool_images/ folder in ATF folder, copy u-boot.bin in u-boot
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folder and tee*.bin in optee out/arm-plat-imx/core/tee/ folder to
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fiptool_images. Run below command in ATF folder to generate FIP image.
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$ make -C tools/fiptool/
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$ tools/fiptool/fiptool create --tos-fw fiptool_images/tee-header_v2.bin \
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--tos-fw-extra1 fiptool_images/tee-pager_v2.bin \
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--tos-fw-extra2 fiptool_images/tee-pageable_v2.bin \
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--nt-fw fiptool_images/u-boot.bin \
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fip.bin
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- Burn the images to eMMC for test.
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Run below command in atf folder:
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$ dd if=build/picopi/debug/bl2.bin.imx of=/dev/disk/by-id/usb-<your device> bs=1024 seek=1;sync
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$ dd if=fip.bin of=/dev/disk/by-id/usb-<your device> bs=1024 seek=1;sync
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- Test
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Just boot up your board and wait for u-boot start up after ATF's log.
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For booting Linux in FIT image, please reference the FIT files in
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u-boot doc/uImage.FIT/ folder.
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@@ -0,0 +1,291 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 NXP Semiconductors
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*/
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/io.h>
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../../freescale/common/pfuze.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
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#ifdef CONFIG_SYS_I2C_MXC
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C4 for PMIC */
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static struct i2c_pads_info i2c_pad_info4 = {
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.scl = {
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.i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
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.gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
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.gp = IMX_GPIO_NR(6, 16),
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},
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.sda = {
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.i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
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.gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
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.gp = IMX_GPIO_NR(6, 17),
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},
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};
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#endif
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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/* Subtract the defined OPTEE runtime firmware length */
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#ifdef CONFIG_OPTEE_TZDRAM_SIZE
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gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
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#endif
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return 0;
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}
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#ifdef CONFIG_POWER
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#define I2C_PMIC 3
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int power_init_board(void)
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{
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struct pmic *p;
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int ret;
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unsigned int reg, rev_id;
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ret = power_pfuze3000_init(I2C_PMIC);
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if (ret)
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return ret;
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p = pmic_get("PFUZE3000");
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ret = pmic_probe(p);
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if (ret) {
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printf("Warning: Cannot find PMIC PFUZE3000\n");
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printf("\tPower consumption is not optimized.\n");
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return 0;
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}
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pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
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pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
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printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
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/* disable Low Power Mode during standby mode */
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pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
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reg |= 0x1;
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pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
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/* SW1A/1B mode set to APS/APS */
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reg = 0x8;
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pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
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pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
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/* SW1A/1B standby voltage set to 1.025V */
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reg = 0xd;
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pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
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pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
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/* decrease SW1B normal voltage to 0.975V */
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pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
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reg &= ~0x1f;
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reg |= PFUZE3000_SW1AB_SETP(975);
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pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
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return 0;
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}
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#endif
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static iomux_v3_cfg_t const wdog_pads[] = {
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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart5_pads[] = {
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MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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#ifdef CONFIG_FEC_MXC
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
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MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11)
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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gpio_request(FEC1_RST_GPIO, "phy_rst");
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gpio_direction_output(FEC1_RST_GPIO, 0);
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||||
udelay(500);
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gpio_set_value(FEC1_RST_GPIO, 1);
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}
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||||
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int board_eth_init(bd_t *bis)
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||||
{
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setup_iomux_fec();
|
||||
|
||||
return fecmxc_initialize_multi(bis, 0,
|
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
|
||||
(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
|
||||
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
|
||||
|
||||
return set_clk_enet(ENET_125MHZ);
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
unsigned short val;
|
||||
|
||||
/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
|
||||
|
||||
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
|
||||
val &= 0xffe7;
|
||||
val |= 0x18;
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
|
||||
|
||||
/* introduce tx clock delay */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
|
||||
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
|
||||
val |= 0x0100;
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DM_VIDEO
|
||||
void setup_lcd(void)
|
||||
{
|
||||
gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness");
|
||||
gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable");
|
||||
/* Set Brightness to high */
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
|
||||
/* Set LCD enable to high */
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_DM_VIDEO
|
||||
|
||||
setup_lcd();
|
||||
|
||||
#endif
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
|
||||
set_wdog_reset(wdog);
|
||||
|
||||
/*
|
||||
* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
|
||||
* since we use PMIC_PWRON to reset the board.
|
||||
*/
|
||||
clrsetbits_le16(&wdog->wcr, 0, 0x10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: i.MX7D PICOSOM\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const usb_otg2_pads[] = {
|
||||
MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
switch (port) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
|
||||
ARRAY_SIZE(usb_otg2_pads));
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,164 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Technexion Ltd.
|
||||
*
|
||||
* Author: Richard Hu <richard.hu@technexion.com>
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/mx7-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch-mx7/mx7-ddr.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <spl.h>
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* Break into full U-Boot on 'c' */
|
||||
if (serial_tstc() && serial_getc() == 'c')
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct ddrc ddrc_regs_val = {
|
||||
.mstr = 0x01040001,
|
||||
.rfshtmg = 0x00400046,
|
||||
.init1 = 0x00690000,
|
||||
.init0 = 0x00020083,
|
||||
.init3 = 0x09300004,
|
||||
.init4 = 0x04080000,
|
||||
.init5 = 0x00100004,
|
||||
.rankctl = 0x0000033F,
|
||||
.dramtmg0 = 0x09081109,
|
||||
.dramtmg1 = 0x0007020d,
|
||||
.dramtmg2 = 0x03040407,
|
||||
.dramtmg3 = 0x00002006,
|
||||
.dramtmg4 = 0x04020205,
|
||||
.dramtmg5 = 0x03030202,
|
||||
.dramtmg8 = 0x00000803,
|
||||
.zqctl0 = 0x00800020,
|
||||
.dfitmg0 = 0x02098204,
|
||||
.dfitmg1 = 0x00030303,
|
||||
.dfiupd0 = 0x80400003,
|
||||
.dfiupd1 = 0x00100020,
|
||||
.dfiupd2 = 0x80100004,
|
||||
.addrmap4 = 0x00000F0F,
|
||||
.odtcfg = 0x06000604,
|
||||
.odtmap = 0x00000001,
|
||||
.rfshtmg = 0x00400046,
|
||||
.dramtmg0 = 0x09081109,
|
||||
.addrmap0 = 0x0000001f,
|
||||
.addrmap1 = 0x00080808,
|
||||
.addrmap4 = 0x00000f0f,
|
||||
.addrmap5 = 0x07070707,
|
||||
.addrmap6 = 0x0f0f0707,
|
||||
};
|
||||
|
||||
static struct ddrc_mp ddrc_mp_val = {
|
||||
.pctrl_0 = 0x00000001,
|
||||
};
|
||||
|
||||
static struct ddr_phy ddr_phy_regs_val = {
|
||||
.phy_con0 = 0x17420f40,
|
||||
.phy_con1 = 0x10210100,
|
||||
.phy_con4 = 0x00060807,
|
||||
.mdll_con0 = 0x1010007e,
|
||||
.drvds_con0 = 0x00000d6e,
|
||||
.cmd_sdll_con0 = 0x00000010,
|
||||
.offset_lp_con0 = 0x0000000f,
|
||||
.offset_rd_con0 = 0x08080808,
|
||||
.offset_wr_con0 = 0x08080808,
|
||||
};
|
||||
|
||||
static struct mx7_calibration calib_param = {
|
||||
.num_val = 5,
|
||||
.values = {
|
||||
0x0E407304,
|
||||
0x0E447304,
|
||||
0x0E447306,
|
||||
0x0E447304,
|
||||
0x0E447304,
|
||||
},
|
||||
};
|
||||
|
||||
static void gpr_init(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *gpr_regs =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
writel(0x4F400005, &gpr_regs->gpr[1]);
|
||||
}
|
||||
|
||||
static bool is_1g(void)
|
||||
{
|
||||
gpio_direction_input(IMX_GPIO_NR(1, 12));
|
||||
return !gpio_get_value(IMX_GPIO_NR(1, 12));
|
||||
}
|
||||
|
||||
static void ddr_init(void)
|
||||
{
|
||||
if (is_1g())
|
||||
ddrc_regs_val.addrmap6 = 0x0f070707;
|
||||
|
||||
mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
|
||||
&calib_param);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
arch_cpu_init();
|
||||
gpr_init();
|
||||
board_early_init_f();
|
||||
timer_init();
|
||||
preloader_console_init();
|
||||
ddr_init();
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
|
||||
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
|
||||
|
||||
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
||||
{USDHC3_BASE_ADDR},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
/* Assume uSDHC3 emmc is always present */
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user