GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,53 @@
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if TARGET_K2E_EVM
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config SYS_BOARD
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default "ks2_evm"
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config SYS_VENDOR
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default "ti"
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config SYS_CONFIG_NAME
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default "k2e_evm"
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endif
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if TARGET_K2HK_EVM
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config SYS_BOARD
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default "ks2_evm"
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config SYS_VENDOR
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default "ti"
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config SYS_CONFIG_NAME
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default "k2hk_evm"
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endif
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if TARGET_K2L_EVM
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config SYS_BOARD
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default "ks2_evm"
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config SYS_VENDOR
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default "ti"
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config SYS_CONFIG_NAME
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default "k2l_evm"
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endif
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if TARGET_K2G_EVM
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config SYS_BOARD
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default "ks2_evm"
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config SYS_VENDOR
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default "ti"
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config SYS_CONFIG_NAME
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default "k2g_evm"
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endif
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source "board/ti/common/Kconfig"
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@@ -0,0 +1,12 @@
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KS2_EVM BOARD
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M: Vitaly Andrianov <vitalya@ti.com>
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S: Maintained
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F: board/ti/ks2_evm/
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F: include/configs/k2hk_evm.h
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F: configs/k2hk_evm_defconfig
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F: include/configs/k2e_evm.h
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F: configs/k2e_evm_defconfig
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F: include/configs/k2l_evm.h
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F: configs/k2l_evm_defconfig
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F: include/configs/k2g_evm.h
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F: configs/k2g_evm_defconfig
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@@ -0,0 +1,17 @@
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#
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# KS2-EVM: board Makefile
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# (C) Copyright 2012-2015
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# Texas Instruments Incorporated, <www.ti.com>
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += board.o
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obj-$(CONFIG_TARGET_K2HK_EVM) += board_k2hk.o
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obj-$(CONFIG_TARGET_K2HK_EVM) += ddr3_k2hk.o
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obj-$(CONFIG_TARGET_K2E_EVM) += board_k2e.o
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obj-$(CONFIG_TARGET_K2E_EVM) += ddr3_k2e.o
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obj-$(CONFIG_TARGET_K2L_EVM) += board_k2l.o
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obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_k2l.o
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obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_cfg.o
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obj-$(CONFIG_TARGET_K2G_EVM) += board_k2g.o
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obj-$(CONFIG_TARGET_K2G_EVM) += ddr3_k2g.o
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@@ -0,0 +1,194 @@
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U-Boot port for Texas Instruments Keystone II EVM boards
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========================================================
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Author: Murali Karicheri <m-karicheri2@ti.com>
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This README has information on the U-Boot port for K2HK, K2E, and K2L EVM boards.
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Documentation for this board can be found at
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http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
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https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html
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https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html
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The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K.
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More details on these SoCs are available at company websites
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K2K: http://www.ti.com/product/tci6638k2k
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K2H: http://www.ti.com/product/tci6638k2h
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The K2E SoC details are available at
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http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
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The K2L SoC details are available at
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http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
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The K2G SoC details are available at
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http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
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Board configuration:
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====================
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Some of the peripherals that are configured by U-Boot
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+------+-------+-------+-----------+-----------+-------+-------+----+
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| |DDR3 |NAND |MSM SRAM |ETH ports |UART |I2C |SPI |
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+------+-------+-------+-----------+-----------+-------+-------+----+
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|K2HK |2 |512MB |6MB |4(2) |2 |3 |3 |
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|K2E |4 |512MB |2MB |8(2) |2 |3 |3 |
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|K2L |2 |512MB |2MB |4(2) |4 |3 |3 |
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|K2G |2 |256MB |1MB |1 |1 |1 |1 |
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+------+-------+-------+-----------+-----------+-------+-------+----+
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There are only 2 eth port installed on the boards.
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There are separate PLLs to drive clocks to Tetris ARM and Peripherals.
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To bring up SMP Linux on this board, there is a boot monitor
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code that will be installed in MSMC SRAM. There is command available
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to install this image from U-Boot.
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The port related files can be found at following folders
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keystone2 SoC related files: arch/arm/cpu/armv7/keystone/
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EVMs board files: board/ti/k2s_evm/
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Board configuration files:
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include/configs/k2hk_evm.h
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include/configs/k2e_evm.h
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include/configs/k2l_evm.h
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include/configs/k2g_evm.h
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As U-Boot is migrating to Kconfig there is also board defconfig files
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configs/k2e_evm_defconfig
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configs/k2hk_evm_defconfig
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configs/k2l_evm_defconfig
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configs/k2g_evm_defconfig
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Supported boot modes:
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- SPI NOR boot
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- AEMIF NAND boot (K2E, K2L and K2HK)
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- UART boot
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- MMC boot (Only on K2G)
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Supported image formats:
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- u-boot.bin: for loading and running u-boot.bin through
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Texas Instruments code composure studio (CCS) and for UART boot.
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- u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
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- MLO: gpimage for programming NAND flash for NAND boot, MMC boot.
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Build instructions:
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===================
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Examples for k2hk, for k2e, k2l and k2g just replace k2hk prefix accordingly.
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Don't forget to add ARCH=arm and CROSS_COMPILE.
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To build u-boot.bin, u-boot-spi.gph, MLO:
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>make k2hk_evm_defconfig
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>make
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Load and Run U-Boot on keystone EVMs using CCS
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=========================================
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Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin
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on EVM. See instructions at below link for installing CCS on a Windows PC.
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http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started#
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Installing_Code_Composer_Studio
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Use u-boot.bin from the build folder for loading and running U-Boot binary
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on EVM. Follow instructions at
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K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
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K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup
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K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup
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K2G http://processors.wiki.ti.com/index.php/66AK2G02_GP_EVM_Hardware_Setup
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to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
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and Power ON the EVM. Follow instructions to connect serial port of EVM to
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PC and start TeraTerm or Hyper Terminal.
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Start CCS on a Windows machine and Launch Target
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configuration as instructed at http://processors.wiki.ti.com/index.php/
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MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS.
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The instructions provided in the above link uses a script for
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loading the U-Boot binary on the target EVM. Instead do the following:-
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1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D
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is connected: Unknown)" at the debug window (This is created once Target
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configuration is launched) and select "Connect Target".
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2. Once target connect is successful, choose Tools->Load Memory option from the
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top level menu. At the Load Memory window, choose the file u-boot.bin
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through "Browse" button and click "next >" button. In the next window, enter
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Start address as 0xc000000, choose Type-size "32 bits" and click "Finish"
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button.
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3. Click View -> Registers from the top level menu to view registers window.
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4. From Registers, window expand "Core Registers" to view PC. Edit PC value
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to be 0xc000000. From the "Run" top level menu, select "Free Run"
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5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as
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below and type any key to stop autoboot as instructed :=
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U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59)
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I2C: ready
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Detected SO-DIMM [SQR-SD3T-2G1333SED]
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DRAM: 1.1 GiB
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NAND: 512 MiB
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Net: K2HK_EMAC
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Warning: K2HK_EMAC using MAC address from net device
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, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3
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Hit any key to stop autoboot: 0
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SPI NOR Flash programming instructions
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======================================
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U-Boot image can be flashed to first 512KB of the NOR flash using following
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instructions:
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1. Start CCS and run U-Boot as described above.
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2. Suspend Target. Select Run -> Suspend from top level menu
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CortexA15_1 (Free Running)"
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3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
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through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L
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EVM using CCS", but using address 0x87000000.
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4. Free Run the target as described earlier (step 4) to get U-Boot prompt
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5. At the U-Boot console type following to setup U-Boot environment variables.
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setenv addr_uboot 0x87000000
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setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
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run burn_uboot_spi
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Once U-Boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
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to "SPI Little Endian Boot mode" as per instruction at
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http://processors.wiki.ti.com/index.php/*_Hardware_Setup.
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6. Power ON the EVM. The EVM now boots with U-Boot image on the NOR flash.
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AEMIF NAND Flash programming instructions
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======================================
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U-Boot image can be flashed to first 1024KB of the NAND flash using following
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instructions:
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1. Start CCS and run U-Boot as described above.
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2. Suspend Target. Select Run -> Suspend from top level menu
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CortexA15_1 (Free Running)"
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3. Load MLO binary from build folder on to DDR address 0x87000000
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through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
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using CCS", but using address 0x87000000.
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4. Free Run the target as described earlier (step 4) to get U-Boot prompt
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5. At the U-Boot console type following to setup U-Boot environment variables.
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setenv filesize <size in hex of MLO rounded to hex 0x10000>
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run burn_uboot_nand
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Once U-Boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
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to "ARM NAND Boot mode" as per instruction at
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http://processors.wiki.ti.com/index.php/*_Hardware_Setup.
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6. Power ON the EVM. The EVM now boots with U-Boot image on the NAND flash.
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Load and Run U-Boot on keystone EVMs using UART download
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========================================================
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Open BMC and regular UART terminals.
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1. On the regular UART port start xmodem transfer of the u-boot.bin
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2. Using BMC terminal set the ARM-UART bootmode and reboot the EVM
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BMC> bootmode #4
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MBC> reboot
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3. When xmodem is complete you should see the U-Boot starts on the UART port
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Load and Run U-Boot on K2G EVMs using MMC
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========================================================
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Open BMC and regular UART terminals.
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1. Set the SW3 dip switch to "ARM MMC Boot mode" as per instruction at
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http://processors.wiki.ti.com/index.php/66AK2G02_GP_EVM_Hardware_Setup
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2. Create SD card partitions as per steps given in Hardware Setup Guide.
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3. Copy MLO to Boot Partition.
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4. Insert SD card and Power on the EVM.
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The EVM now boots with U-Boot image from SD card.
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@@ -0,0 +1,241 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Keystone : Board initialization
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#include <common.h>
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#include "board.h"
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#include <env.h>
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#include <spl.h>
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#include <exports.h>
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#include <fdt_support.h>
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#include <asm/arch/ddr3.h>
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#include <asm/arch/psc_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/ti-common/ti-aemif.h>
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#include <asm/ti-common/keystone_net.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_TI_AEMIF)
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static struct aemif_config aemif_configs[] = {
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{ /* CS0 */
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.mode = AEMIF_MODE_NAND,
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.wr_setup = 0xf,
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.wr_strobe = 0x3f,
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.wr_hold = 7,
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.rd_setup = 0xf,
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.rd_strobe = 0x3f,
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.rd_hold = 7,
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.turn_around = 3,
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.width = AEMIF_WIDTH_8,
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},
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};
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#endif
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int dram_init(void)
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{
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u32 ddr3_size;
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ddr3_size = ddr3_init();
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gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_MAX_RAM_BANK_SIZE);
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#if defined(CONFIG_TI_AEMIF)
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if (!board_is_k2g_ice())
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aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
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#endif
|
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|
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if (!board_is_k2g_ice()) {
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if (ddr3_size)
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ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
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else
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ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
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gd->ram_size >> 30);
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}
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return 0;
|
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}
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|
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struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
|
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{
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return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
|
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}
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|
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int board_init(void)
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{
|
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
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return 0;
|
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}
|
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|
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#ifdef CONFIG_SPL_BUILD
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void spl_board_init(void)
|
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{
|
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spl_init_keystone_plls();
|
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preloader_console_init();
|
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}
|
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|
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u32 spl_boot_device(void)
|
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{
|
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#if defined(CONFIG_SPL_SPI_LOAD)
|
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return BOOT_DEVICE_SPI;
|
||||
#else
|
||||
puts("Unknown boot device\n");
|
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hang();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int lpae;
|
||||
char *env;
|
||||
char *endp;
|
||||
int nbanks;
|
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u64 size[2];
|
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u64 start[2];
|
||||
u32 ddr3a_size;
|
||||
|
||||
env = env_get("mem_lpae");
|
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lpae = env && simple_strtol(env, NULL, 0);
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||||
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ddr3a_size = 0;
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||||
if (lpae) {
|
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ddr3a_size = ddr3_get_size();
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if ((ddr3a_size != 8) && (ddr3a_size != 4))
|
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ddr3a_size = 0;
|
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}
|
||||
|
||||
nbanks = 1;
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start[0] = bd->bi_dram[0].start;
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size[0] = bd->bi_dram[0].size;
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||||
/* adjust memory start address for LPAE */
|
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if (lpae) {
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start[0] -= CONFIG_SYS_SDRAM_BASE;
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start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
|
||||
}
|
||||
|
||||
if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
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size[1] = ((u64)ddr3a_size - 2) << 30;
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start[1] = 0x880000000;
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||||
nbanks++;
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}
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|
||||
/* reserve memory at start of bank */
|
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env = env_get("mem_reserve_head");
|
||||
if (env) {
|
||||
start[0] += ustrtoul(env, &endp, 0);
|
||||
size[0] -= ustrtoul(env, &endp, 0);
|
||||
}
|
||||
|
||||
env = env_get("mem_reserve");
|
||||
if (env)
|
||||
size[0] -= ustrtoul(env, &endp, 0);
|
||||
|
||||
fdt_fixup_memory_banks(blob, start, size, nbanks);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ft_board_setup_ex(void *blob, bd_t *bd)
|
||||
{
|
||||
int lpae;
|
||||
u64 size;
|
||||
char *env;
|
||||
u64 *reserve_start;
|
||||
int unitrd_fixup = 0;
|
||||
|
||||
env = env_get("mem_lpae");
|
||||
lpae = env && simple_strtol(env, NULL, 0);
|
||||
env = env_get("uinitrd_fixup");
|
||||
unitrd_fixup = env && simple_strtol(env, NULL, 0);
|
||||
|
||||
/* Fix up the initrd */
|
||||
if (lpae && unitrd_fixup) {
|
||||
int nodeoffset;
|
||||
int err;
|
||||
u64 *prop1, *prop2;
|
||||
u64 initrd_start, initrd_end;
|
||||
|
||||
nodeoffset = fdt_path_offset(blob, "/chosen");
|
||||
if (nodeoffset >= 0) {
|
||||
prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
|
||||
"linux,initrd-start", NULL);
|
||||
prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
|
||||
"linux,initrd-end", NULL);
|
||||
if (prop1 && prop2) {
|
||||
initrd_start = __be64_to_cpu(*prop1);
|
||||
initrd_start -= CONFIG_SYS_SDRAM_BASE;
|
||||
initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
|
||||
initrd_start = __cpu_to_be64(initrd_start);
|
||||
initrd_end = __be64_to_cpu(*prop2);
|
||||
initrd_end -= CONFIG_SYS_SDRAM_BASE;
|
||||
initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
|
||||
initrd_end = __cpu_to_be64(initrd_end);
|
||||
|
||||
err = fdt_delprop(blob, nodeoffset,
|
||||
"linux,initrd-start");
|
||||
if (err < 0)
|
||||
puts("error deleting initrd-start\n");
|
||||
|
||||
err = fdt_delprop(blob, nodeoffset,
|
||||
"linux,initrd-end");
|
||||
if (err < 0)
|
||||
puts("error deleting initrd-end\n");
|
||||
|
||||
err = fdt_setprop(blob, nodeoffset,
|
||||
"linux,initrd-start",
|
||||
&initrd_start,
|
||||
sizeof(initrd_start));
|
||||
if (err < 0)
|
||||
puts("error adding initrd-start\n");
|
||||
|
||||
err = fdt_setprop(blob, nodeoffset,
|
||||
"linux,initrd-end",
|
||||
&initrd_end,
|
||||
sizeof(initrd_end));
|
||||
if (err < 0)
|
||||
puts("error adding linux,initrd-end\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (lpae) {
|
||||
/*
|
||||
* the initrd and other reserved memory areas are
|
||||
* embedded in in the DTB itslef. fix up these addresses
|
||||
* to 36 bit format
|
||||
*/
|
||||
reserve_start = (u64 *)((char *)blob +
|
||||
fdt_off_mem_rsvmap(blob));
|
||||
while (1) {
|
||||
*reserve_start = __cpu_to_be64(*reserve_start);
|
||||
size = __cpu_to_be64(*(reserve_start + 1));
|
||||
if (size) {
|
||||
*reserve_start -= CONFIG_SYS_SDRAM_BASE;
|
||||
*reserve_start +=
|
||||
CONFIG_SYS_LPAE_SDRAM_BASE;
|
||||
*reserve_start =
|
||||
__cpu_to_be64(*reserve_start);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
reserve_start += 2;
|
||||
}
|
||||
}
|
||||
|
||||
ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
|
||||
}
|
||||
#endif /* CONFIG_OF_BOARD_SETUP */
|
||||
|
||||
#if defined(CONFIG_DTB_RESELECT)
|
||||
int __weak embedded_dtb_select(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* K2HK EVM : Board common header
|
||||
*
|
||||
* (C) Copyright 2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
|
||||
#ifndef _KS2_BOARD
|
||||
#define _KS2_BOARD
|
||||
|
||||
#include <asm/ti-common/keystone_net.h>
|
||||
#include "../common/board_detect.h"
|
||||
|
||||
#if defined(CONFIG_TI_I2C_BOARD_DETECT)
|
||||
static inline int board_is_k2g_gp(void)
|
||||
{
|
||||
return board_ti_is("66AK2GGP");
|
||||
}
|
||||
static inline int board_is_k2g_g1(void)
|
||||
{
|
||||
return board_ti_is("66AK2GG1");
|
||||
}
|
||||
static inline int board_is_k2g_ice(void)
|
||||
{
|
||||
return board_ti_is("66AK2GIC");
|
||||
}
|
||||
#else
|
||||
static inline int board_is_k2g_gp(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
static inline int board_is_k2g_ice(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
void spl_init_keystone_plls(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,116 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* K2E EVM : Board initialization
|
||||
*
|
||||
* (C) Copyright 2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/ddr3.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/ti-common/keystone_net.h>
|
||||
|
||||
unsigned int get_external_clk(u32 clk)
|
||||
{
|
||||
unsigned int clk_freq;
|
||||
|
||||
switch (clk) {
|
||||
case sys_clk:
|
||||
clk_freq = 100000000;
|
||||
break;
|
||||
case alt_core_clk:
|
||||
clk_freq = 100000000;
|
||||
break;
|
||||
case pa_clk:
|
||||
clk_freq = 100000000;
|
||||
break;
|
||||
case ddr3a_clk:
|
||||
clk_freq = 100000000;
|
||||
break;
|
||||
default:
|
||||
clk_freq = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return clk_freq;
|
||||
}
|
||||
|
||||
static struct pll_init_data core_pll_config[NUM_SPDS] = {
|
||||
[SPD800] = CORE_PLL_800,
|
||||
[SPD850] = CORE_PLL_850,
|
||||
[SPD1000] = CORE_PLL_1000,
|
||||
[SPD1250] = CORE_PLL_1250,
|
||||
[SPD1350] = CORE_PLL_1350,
|
||||
[SPD1400] = CORE_PLL_1400,
|
||||
[SPD1500] = CORE_PLL_1500,
|
||||
};
|
||||
|
||||
/* DEV and ARM speed definitions as specified in DEVSPEED register */
|
||||
int speeds[DEVSPEED_NUMSPDS] = {
|
||||
SPD850,
|
||||
SPD1000,
|
||||
SPD1250,
|
||||
SPD1350,
|
||||
SPD1400,
|
||||
SPD1500,
|
||||
SPD1400,
|
||||
SPD1350,
|
||||
SPD1250,
|
||||
SPD1000,
|
||||
SPD850,
|
||||
SPD800,
|
||||
};
|
||||
|
||||
s16 divn_val[16] = {
|
||||
0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
|
||||
};
|
||||
|
||||
static struct pll_init_data pa_pll_config =
|
||||
PASS_PLL_1000;
|
||||
|
||||
struct pll_init_data *get_pll_init_data(int pll)
|
||||
{
|
||||
int speed;
|
||||
struct pll_init_data *data;
|
||||
|
||||
switch (pll) {
|
||||
case MAIN_PLL:
|
||||
speed = get_max_dev_speed(speeds);
|
||||
data = &core_pll_config[speed];
|
||||
break;
|
||||
case PASS_PLL:
|
||||
data = &pa_pll_config;
|
||||
break;
|
||||
default:
|
||||
data = NULL;
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MULTI_DTB_FIT)
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
if (!strcmp(name, "keystone-k2e-evm"))
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BOARD_EARLY_INIT_F)
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
init_plls();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void spl_init_keystone_plls(void)
|
||||
{
|
||||
init_plls();
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,404 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* K2G EVM : Board initialization
|
||||
*
|
||||
* (C) Copyright 2015
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <eeprom.h>
|
||||
#include <env.h>
|
||||
#include <init.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/ti-common/keystone_net.h>
|
||||
#include <asm/arch/psc_defs.h>
|
||||
#include <asm/arch/mmc_host_def.h>
|
||||
#include <fdtdec.h>
|
||||
#include <i2c.h>
|
||||
#include <remoteproc.h>
|
||||
#include "mux-k2g.h"
|
||||
#include "../common/board_detect.h"
|
||||
|
||||
#define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
|
||||
|
||||
const unsigned int sysclk_array[MAX_SYSCLK] = {
|
||||
19200000,
|
||||
24000000,
|
||||
25000000,
|
||||
26000000,
|
||||
};
|
||||
|
||||
unsigned int get_external_clk(u32 clk)
|
||||
{
|
||||
unsigned int clk_freq;
|
||||
u8 sysclk_index = get_sysclk_index();
|
||||
|
||||
switch (clk) {
|
||||
case sys_clk:
|
||||
clk_freq = sysclk_array[sysclk_index];
|
||||
break;
|
||||
case pa_clk:
|
||||
clk_freq = sysclk_array[sysclk_index];
|
||||
break;
|
||||
case tetris_clk:
|
||||
clk_freq = sysclk_array[sysclk_index];
|
||||
break;
|
||||
case ddr3a_clk:
|
||||
clk_freq = sysclk_array[sysclk_index];
|
||||
break;
|
||||
case uart_clk:
|
||||
clk_freq = sysclk_array[sysclk_index];
|
||||
break;
|
||||
default:
|
||||
clk_freq = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return clk_freq;
|
||||
}
|
||||
|
||||
int speeds[DEVSPEED_NUMSPDS] = {
|
||||
SPD400,
|
||||
SPD600,
|
||||
SPD800,
|
||||
SPD900,
|
||||
SPD1000,
|
||||
SPD900,
|
||||
SPD800,
|
||||
SPD600,
|
||||
SPD400,
|
||||
SPD200,
|
||||
};
|
||||
|
||||
static int dev_speeds[DEVSPEED_NUMSPDS] = {
|
||||
SPD600,
|
||||
SPD800,
|
||||
SPD900,
|
||||
SPD1000,
|
||||
SPD900,
|
||||
SPD800,
|
||||
SPD600,
|
||||
SPD400,
|
||||
};
|
||||
|
||||
static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
|
||||
[SYSCLK_19MHz] = {
|
||||
[SPD400] = {MAIN_PLL, 125, 3, 2},
|
||||
[SPD600] = {MAIN_PLL, 125, 2, 2},
|
||||
[SPD800] = {MAIN_PLL, 250, 3, 2},
|
||||
[SPD900] = {MAIN_PLL, 187, 2, 2},
|
||||
[SPD1000] = {MAIN_PLL, 104, 1, 2},
|
||||
},
|
||||
[SYSCLK_24MHz] = {
|
||||
[SPD400] = {MAIN_PLL, 100, 3, 2},
|
||||
[SPD600] = {MAIN_PLL, 300, 6, 2},
|
||||
[SPD800] = {MAIN_PLL, 200, 3, 2},
|
||||
[SPD900] = {MAIN_PLL, 75, 1, 2},
|
||||
[SPD1000] = {MAIN_PLL, 250, 3, 2},
|
||||
},
|
||||
[SYSCLK_25MHz] = {
|
||||
[SPD400] = {MAIN_PLL, 32, 1, 2},
|
||||
[SPD600] = {MAIN_PLL, 48, 1, 2},
|
||||
[SPD800] = {MAIN_PLL, 64, 1, 2},
|
||||
[SPD900] = {MAIN_PLL, 72, 1, 2},
|
||||
[SPD1000] = {MAIN_PLL, 80, 1, 2},
|
||||
},
|
||||
[SYSCLK_26MHz] = {
|
||||
[SPD400] = {MAIN_PLL, 400, 13, 2},
|
||||
[SPD600] = {MAIN_PLL, 230, 5, 2},
|
||||
[SPD800] = {MAIN_PLL, 123, 2, 2},
|
||||
[SPD900] = {MAIN_PLL, 69, 1, 2},
|
||||
[SPD1000] = {MAIN_PLL, 384, 5, 2},
|
||||
},
|
||||
};
|
||||
|
||||
static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
|
||||
[SYSCLK_19MHz] = {
|
||||
[SPD200] = {TETRIS_PLL, 625, 6, 10},
|
||||
[SPD400] = {TETRIS_PLL, 125, 1, 6},
|
||||
[SPD600] = {TETRIS_PLL, 125, 1, 4},
|
||||
[SPD800] = {TETRIS_PLL, 333, 2, 4},
|
||||
[SPD900] = {TETRIS_PLL, 187, 2, 2},
|
||||
[SPD1000] = {TETRIS_PLL, 104, 1, 2},
|
||||
},
|
||||
[SYSCLK_24MHz] = {
|
||||
[SPD200] = {TETRIS_PLL, 250, 3, 10},
|
||||
[SPD400] = {TETRIS_PLL, 100, 1, 6},
|
||||
[SPD600] = {TETRIS_PLL, 100, 1, 4},
|
||||
[SPD800] = {TETRIS_PLL, 400, 3, 4},
|
||||
[SPD900] = {TETRIS_PLL, 75, 1, 2},
|
||||
[SPD1000] = {TETRIS_PLL, 250, 3, 2},
|
||||
},
|
||||
[SYSCLK_25MHz] = {
|
||||
[SPD200] = {TETRIS_PLL, 80, 1, 10},
|
||||
[SPD400] = {TETRIS_PLL, 96, 1, 6},
|
||||
[SPD600] = {TETRIS_PLL, 96, 1, 4},
|
||||
[SPD800] = {TETRIS_PLL, 128, 1, 4},
|
||||
[SPD900] = {TETRIS_PLL, 72, 1, 2},
|
||||
[SPD1000] = {TETRIS_PLL, 80, 1, 2},
|
||||
},
|
||||
[SYSCLK_26MHz] = {
|
||||
[SPD200] = {TETRIS_PLL, 307, 4, 10},
|
||||
[SPD400] = {TETRIS_PLL, 369, 4, 6},
|
||||
[SPD600] = {TETRIS_PLL, 369, 4, 4},
|
||||
[SPD800] = {TETRIS_PLL, 123, 1, 4},
|
||||
[SPD900] = {TETRIS_PLL, 69, 1, 2},
|
||||
[SPD1000] = {TETRIS_PLL, 384, 5, 2},
|
||||
},
|
||||
};
|
||||
|
||||
static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
|
||||
[SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
|
||||
[SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
|
||||
[SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
|
||||
[SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
|
||||
};
|
||||
|
||||
static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
|
||||
[SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
|
||||
[SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
|
||||
[SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
|
||||
[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
|
||||
};
|
||||
|
||||
static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
|
||||
[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
|
||||
[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
|
||||
[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
|
||||
[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
|
||||
};
|
||||
|
||||
static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
|
||||
[SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
|
||||
[SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
|
||||
[SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
|
||||
[SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
|
||||
};
|
||||
|
||||
struct pll_init_data *get_pll_init_data(int pll)
|
||||
{
|
||||
int speed;
|
||||
struct pll_init_data *data = NULL;
|
||||
u8 sysclk_index = get_sysclk_index();
|
||||
|
||||
switch (pll) {
|
||||
case MAIN_PLL:
|
||||
speed = get_max_dev_speed(dev_speeds);
|
||||
data = &main_pll_config[sysclk_index][speed];
|
||||
break;
|
||||
case TETRIS_PLL:
|
||||
speed = get_max_arm_speed(speeds);
|
||||
data = &tetris_pll_config[sysclk_index][speed];
|
||||
break;
|
||||
case NSS_PLL:
|
||||
data = &nss_pll_config[sysclk_index];
|
||||
break;
|
||||
case UART_PLL:
|
||||
data = &uart_pll_config[sysclk_index];
|
||||
break;
|
||||
case DDR3_PLL:
|
||||
if (cpu_revision() & CPU_66AK2G1x) {
|
||||
speed = get_max_arm_speed(speeds);
|
||||
if (speed == SPD1000)
|
||||
data = &ddr3_pll_config_1066[sysclk_index];
|
||||
else
|
||||
data = &ddr3_pll_config_800[sysclk_index];
|
||||
} else {
|
||||
data = &ddr3_pll_config_800[sysclk_index];
|
||||
}
|
||||
break;
|
||||
default:
|
||||
data = NULL;
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
s16 divn_val[16] = {
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
|
||||
};
|
||||
|
||||
#if defined(CONFIG_MMC)
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
if (psc_enable_module(KS2_LPSC_MMC)) {
|
||||
printf("%s module enabled failed\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (board_is_k2g_gp() || board_is_k2g_g1())
|
||||
omap_mmc_init(0, 0, 0, -1, -1);
|
||||
|
||||
omap_mmc_init(1, 0, 0, -1, -1);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MULTI_DTB_FIT)
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
bool eeprom_read = board_ti_was_eeprom_read();
|
||||
|
||||
if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
|
||||
return 0;
|
||||
else if (!strcmp(name, "keystone-k2g-evm") &&
|
||||
(board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
|
||||
return 0;
|
||||
else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
|
||||
return 0;
|
||||
else
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DTB_RESELECT)
|
||||
static int k2g_alt_board_detect(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C
|
||||
int rc;
|
||||
|
||||
rc = i2c_set_bus_num(1);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
|
||||
if (rc)
|
||||
return rc;
|
||||
#else
|
||||
struct udevice *bus, *dev;
|
||||
int rc;
|
||||
|
||||
rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
|
||||
if (rc)
|
||||
return rc;
|
||||
rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
|
||||
if (rc)
|
||||
return rc;
|
||||
#endif
|
||||
ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void k2g_reset_mux_config(void)
|
||||
{
|
||||
/* Unlock the reset mux register */
|
||||
clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
|
||||
|
||||
/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
|
||||
clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
|
||||
RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
|
||||
|
||||
/* lock the reset mux register to prevent any spurious writes. */
|
||||
setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
|
||||
}
|
||||
|
||||
int embedded_dtb_select(void)
|
||||
{
|
||||
int rc;
|
||||
rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
|
||||
CONFIG_EEPROM_CHIP_ADDRESS);
|
||||
if (rc) {
|
||||
rc = k2g_alt_board_detect();
|
||||
if (rc) {
|
||||
printf("Unable to do board detection\n");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
fdtdec_setup();
|
||||
|
||||
k2g_mux_config();
|
||||
|
||||
k2g_reset_mux_config();
|
||||
|
||||
if (board_is_k2g_gp() || board_is_k2g_g1()) {
|
||||
/* deassert FLASH_HOLD */
|
||||
clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
|
||||
BIT(9));
|
||||
setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
|
||||
BIT(9));
|
||||
} else if (board_is_k2g_ice()) {
|
||||
/* GBE Phy workaround. For Phy to latch the input
|
||||
* configuration, a GPIO reset is asserted at the
|
||||
* Phy reset pin to latch configuration correctly after SoC
|
||||
* reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
|
||||
* board. Just do a low to high transition.
|
||||
*/
|
||||
clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
|
||||
BIT(10));
|
||||
setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
|
||||
BIT(10));
|
||||
/* Delay just to get a transition to high */
|
||||
udelay(100);
|
||||
setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
|
||||
BIT(10));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INIT
|
||||
int board_late_init(void)
|
||||
{
|
||||
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
|
||||
int rc;
|
||||
|
||||
rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
|
||||
CONFIG_EEPROM_CHIP_ADDRESS);
|
||||
if (rc)
|
||||
printf("ti_i2c_eeprom_init failed %d\n", rc);
|
||||
|
||||
board_ti_set_ethaddr(1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
if (board_is_k2g_gp())
|
||||
env_set("board_name", "66AK2GGP\0");
|
||||
else if (board_is_k2g_g1())
|
||||
env_set("board_name", "66AK2GG1\0");
|
||||
else if (board_is_k2g_ice())
|
||||
env_set("board_name", "66AK2GIC\0");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
init_plls();
|
||||
|
||||
k2g_mux_config();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void spl_init_keystone_plls(void)
|
||||
{
|
||||
init_plls();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TI_SECURE_DEVICE
|
||||
void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
|
||||
{
|
||||
int id = env_get_ulong("dev_pmmc", 10, 0);
|
||||
int ret;
|
||||
|
||||
if (!rproc_is_initialized())
|
||||
rproc_init();
|
||||
|
||||
ret = rproc_load(id, pmmc_image, pmmc_size);
|
||||
printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
|
||||
id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
|
||||
|
||||
if (!ret)
|
||||
rproc_start(id);
|
||||
}
|
||||
|
||||
U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
|
||||
#endif
|
||||
@@ -0,0 +1,123 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* K2HK EVM : Board initialization
|
||||
*
|
||||
* (C) Copyright 2012-2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/ti-common/keystone_net.h>
|
||||
|
||||
unsigned int external_clk[ext_clk_count] = {
|
||||
[sys_clk] = 122880000,
|
||||
[alt_core_clk] = 125000000,
|
||||
[pa_clk] = 122880000,
|
||||
[tetris_clk] = 125000000,
|
||||
[ddr3a_clk] = 100000000,
|
||||
[ddr3b_clk] = 100000000,
|
||||
};
|
||||
|
||||
unsigned int get_external_clk(u32 clk)
|
||||
{
|
||||
unsigned int clk_freq;
|
||||
|
||||
switch (clk) {
|
||||
case sys_clk:
|
||||
clk_freq = 122880000;
|
||||
break;
|
||||
case alt_core_clk:
|
||||
clk_freq = 125000000;
|
||||
break;
|
||||
case pa_clk:
|
||||
clk_freq = 122880000;
|
||||
break;
|
||||
case tetris_clk:
|
||||
clk_freq = 125000000;
|
||||
break;
|
||||
case ddr3a_clk:
|
||||
clk_freq = 100000000;
|
||||
break;
|
||||
case ddr3b_clk:
|
||||
clk_freq = 100000000;
|
||||
break;
|
||||
default:
|
||||
clk_freq = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return clk_freq;
|
||||
}
|
||||
|
||||
static struct pll_init_data core_pll_config[NUM_SPDS] = {
|
||||
[SPD800] = CORE_PLL_799,
|
||||
[SPD1000] = CORE_PLL_999,
|
||||
[SPD1200] = CORE_PLL_1200,
|
||||
};
|
||||
|
||||
s16 divn_val[16] = {
|
||||
0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
|
||||
};
|
||||
|
||||
static struct pll_init_data tetris_pll_config[] = {
|
||||
[SPD800] = TETRIS_PLL_800,
|
||||
[SPD1000] = TETRIS_PLL_1000,
|
||||
[SPD1200] = TETRIS_PLL_1200,
|
||||
[SPD1350] = TETRIS_PLL_1350,
|
||||
[SPD1400] = TETRIS_PLL_1400,
|
||||
};
|
||||
|
||||
static struct pll_init_data pa_pll_config =
|
||||
PASS_PLL_983;
|
||||
|
||||
struct pll_init_data *get_pll_init_data(int pll)
|
||||
{
|
||||
int speed;
|
||||
struct pll_init_data *data;
|
||||
|
||||
switch (pll) {
|
||||
case MAIN_PLL:
|
||||
speed = get_max_dev_speed(speeds);
|
||||
data = &core_pll_config[speed];
|
||||
break;
|
||||
case TETRIS_PLL:
|
||||
speed = get_max_arm_speed(speeds);
|
||||
data = &tetris_pll_config[speed];
|
||||
break;
|
||||
case PASS_PLL:
|
||||
data = &pa_pll_config;
|
||||
break;
|
||||
default:
|
||||
data = NULL;
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
init_plls();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MULTI_DTB_FIT)
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
if (!strcmp(name, "keystone-k2hk-evm"))
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void spl_init_keystone_plls(void)
|
||||
{
|
||||
init_plls();
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,111 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* K2L EVM : Board initialization
|
||||
*
|
||||
* (C) Copyright 2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/ddr3.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/ti-common/keystone_net.h>
|
||||
|
||||
unsigned int get_external_clk(u32 clk)
|
||||
{
|
||||
unsigned int clk_freq;
|
||||
|
||||
switch (clk) {
|
||||
case sys_clk:
|
||||
clk_freq = 122880000;
|
||||
break;
|
||||
case alt_core_clk:
|
||||
clk_freq = 100000000;
|
||||
break;
|
||||
case pa_clk:
|
||||
clk_freq = 122880000;
|
||||
break;
|
||||
case tetris_clk:
|
||||
clk_freq = 122880000;
|
||||
break;
|
||||
case ddr3a_clk:
|
||||
clk_freq = 100000000;
|
||||
break;
|
||||
default:
|
||||
clk_freq = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return clk_freq;
|
||||
}
|
||||
|
||||
static struct pll_init_data core_pll_config[NUM_SPDS] = {
|
||||
[SPD800] = CORE_PLL_799,
|
||||
[SPD1000] = CORE_PLL_1000,
|
||||
[SPD1200] = CORE_PLL_1198,
|
||||
};
|
||||
|
||||
s16 divn_val[16] = {
|
||||
0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
|
||||
};
|
||||
|
||||
static struct pll_init_data tetris_pll_config[] = {
|
||||
[SPD800] = TETRIS_PLL_799,
|
||||
[SPD1000] = TETRIS_PLL_1000,
|
||||
[SPD1200] = TETRIS_PLL_1198,
|
||||
[SPD1350] = TETRIS_PLL_1352,
|
||||
[SPD1400] = TETRIS_PLL_1401,
|
||||
};
|
||||
|
||||
static struct pll_init_data pa_pll_config =
|
||||
PASS_PLL_983;
|
||||
|
||||
struct pll_init_data *get_pll_init_data(int pll)
|
||||
{
|
||||
int speed;
|
||||
struct pll_init_data *data;
|
||||
|
||||
switch (pll) {
|
||||
case MAIN_PLL:
|
||||
speed = get_max_dev_speed(speeds);
|
||||
data = &core_pll_config[speed];
|
||||
break;
|
||||
case TETRIS_PLL:
|
||||
speed = get_max_arm_speed(speeds);
|
||||
data = &tetris_pll_config[speed];
|
||||
break;
|
||||
case PASS_PLL:
|
||||
data = &pa_pll_config;
|
||||
break;
|
||||
default:
|
||||
data = NULL;
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
init_plls();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MULTI_DTB_FIT)
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
if (!strcmp(name, "keystone-k2l-evm"))
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void spl_init_keystone_plls(void)
|
||||
{
|
||||
init_plls();
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,48 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Keystone2: DDR3 configuration
|
||||
*
|
||||
* (C) Copyright 2012-2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <asm/arch/ddr3.h>
|
||||
#include "ddr3_cfg.h"
|
||||
|
||||
struct ddr3_phy_config ddr3phy_1600_2g = {
|
||||
.pllcr = 0x0001C000ul,
|
||||
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
|
||||
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
|
||||
.ptr0 = 0x42C21590ul,
|
||||
.ptr1 = 0xD05612C0ul,
|
||||
.ptr2 = 0, /* not set in gel */
|
||||
.ptr3 = 0x0D861A80ul,
|
||||
.ptr4 = 0x0C827100ul,
|
||||
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
|
||||
.dcr_val = ((1 << 10)),
|
||||
.dtpr0 = 0x9D5CBB66ul,
|
||||
.dtpr1 = 0x12868300ul,
|
||||
.dtpr2 = 0x5002D200ul,
|
||||
.mr0 = 0x00001C70ul,
|
||||
.mr1 = 0x00000006ul,
|
||||
.mr2 = 0x00000018ul,
|
||||
.dtcr = 0x710035C7ul,
|
||||
.pgcr2 = 0x00F07A12ul,
|
||||
.zq0cr1 = 0x0001005Dul,
|
||||
.zq1cr1 = 0x0001005Bul,
|
||||
.zq2cr1 = 0x0001005Bul,
|
||||
.pir_v1 = 0x00000033ul,
|
||||
.pir_v2 = 0x0000FF81ul,
|
||||
};
|
||||
|
||||
struct ddr3_emif_config ddr3_1600_2g = {
|
||||
.sdcfg = 0x6200CE62ul,
|
||||
.sdtim1 = 0x166C9855ul,
|
||||
.sdtim2 = 0x00001D4Aul,
|
||||
.sdtim3 = 0x435DFF53ul,
|
||||
.sdtim4 = 0x543F0CFFul,
|
||||
.zqcfg = 0x70073200ul,
|
||||
.sdrfc = 0x00001869ul,
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Keystone2: DDR3 configuration
|
||||
*
|
||||
* (C) Copyright 2012-2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
|
||||
#ifndef __DDR3_CFG_H
|
||||
#define __DDR3_CFG_H
|
||||
|
||||
#include <asm/arch/ddr3.h>
|
||||
|
||||
extern struct ddr3_phy_config ddr3phy_1600_2g;
|
||||
extern struct ddr3_emif_config ddr3_1600_2g;
|
||||
|
||||
int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb);
|
||||
|
||||
#endif /* __DDR3_CFG_H */
|
||||
@@ -0,0 +1,47 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Keystone2: DDR3 initialization
|
||||
*
|
||||
* (C) Copyright 2014-2015
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "ddr3_cfg.h"
|
||||
#include <asm/arch/ddr3.h>
|
||||
|
||||
static struct pll_init_data ddr3_400 = DDR3_PLL_400;
|
||||
static struct pll_init_data ddr3_333 = DDR3_PLL_333;
|
||||
|
||||
u32 ddr3_init(void)
|
||||
{
|
||||
struct ddr3_spd_cb spd_cb;
|
||||
|
||||
if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
|
||||
printf("Sorry, I don't know how to configure DDR3A.\n"
|
||||
"Bye :(\n");
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
|
||||
|
||||
printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
|
||||
if (spd_cb.ddrspdclock == 1600)
|
||||
init_pll(&ddr3_400);
|
||||
else
|
||||
init_pll(&ddr3_333);
|
||||
|
||||
/* Reset DDR3 PHY after PLL enabled */
|
||||
ddr3_reset_ddrphy();
|
||||
|
||||
spd_cb.phy_cfg.zq0cr1 |= 0x10000;
|
||||
spd_cb.phy_cfg.zq1cr1 |= 0x10000;
|
||||
spd_cb.phy_cfg.zq2cr1 |= 0x10000;
|
||||
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
|
||||
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
|
||||
|
||||
printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);
|
||||
|
||||
return (u32)spd_cb.ddr_size_gbyte;
|
||||
}
|
||||
@@ -0,0 +1,188 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* K2G: DDR3 initialization
|
||||
*
|
||||
* (C) Copyright 2015
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "ddr3_cfg.h"
|
||||
#include <asm/arch/ddr3.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include "board.h"
|
||||
|
||||
/* K2G GP EVM DDR3 Configuration */
|
||||
static struct ddr3_phy_config ddr3phy_800_2g = {
|
||||
.pllcr = 0x000DC000ul,
|
||||
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
|
||||
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
|
||||
.ptr0 = 0x42C21590ul,
|
||||
.ptr1 = 0xD05612C0ul,
|
||||
.ptr2 = 0,
|
||||
.ptr3 = 0x06C30D40ul,
|
||||
.ptr4 = 0x06413880ul,
|
||||
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
|
||||
.dcr_val = ((1 << 10)),
|
||||
.dtpr0 = 0x550F6644ul,
|
||||
.dtpr1 = 0x328341E0ul,
|
||||
.dtpr2 = 0x50022A00ul,
|
||||
.mr0 = 0x00001430ul,
|
||||
.mr1 = 0x00000006ul,
|
||||
.mr2 = 0x00000000ul,
|
||||
.dtcr = 0x710035C7ul,
|
||||
.pgcr2 = 0x00F03D09ul,
|
||||
.zq0cr1 = 0x0001005Dul,
|
||||
.zq1cr1 = 0x0001005Bul,
|
||||
.zq2cr1 = 0x0001005Bul,
|
||||
.pir_v1 = 0x00000033ul,
|
||||
.datx8_2_mask = 0,
|
||||
.datx8_2_val = 0,
|
||||
.datx8_3_mask = 0,
|
||||
.datx8_3_val = 0,
|
||||
.datx8_4_mask = 0,
|
||||
.datx8_4_val = ((1 << 0)),
|
||||
.datx8_5_mask = DXEN_MASK,
|
||||
.datx8_5_val = 0,
|
||||
.datx8_6_mask = DXEN_MASK,
|
||||
.datx8_6_val = 0,
|
||||
.datx8_7_mask = DXEN_MASK,
|
||||
.datx8_7_val = 0,
|
||||
.datx8_8_mask = DXEN_MASK,
|
||||
.datx8_8_val = 0,
|
||||
.pir_v2 = 0x00000F81ul,
|
||||
};
|
||||
|
||||
static struct ddr3_phy_config ddr3phy_1066_2g = {
|
||||
.pllcr = 0x000DC000ul,
|
||||
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
|
||||
.pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
|
||||
.ptr0 = 0x42C21590ul,
|
||||
.ptr1 = 0xD05612C0ul,
|
||||
.ptr2 = 0,
|
||||
.ptr3 = 0x0904111Dul,
|
||||
.ptr4 = 0x0859A072ul,
|
||||
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
|
||||
.dcr_val = ((1 << 10)),
|
||||
.dtpr0 = 0x6D147744ul,
|
||||
.dtpr1 = 0x32845A80ul,
|
||||
.dtpr2 = 0x50023600ul,
|
||||
.mr0 = 0x00001830ul,
|
||||
.mr1 = 0x00000006ul,
|
||||
.mr2 = 0x00000000ul,
|
||||
.dtcr = 0x710035C7ul,
|
||||
.pgcr2 = 0x00F05159ul,
|
||||
.zq0cr1 = 0x0001005Dul,
|
||||
.zq1cr1 = 0x0001005Bul,
|
||||
.zq2cr1 = 0x0001005Bul,
|
||||
.pir_v1 = 0x00000033ul,
|
||||
.datx8_2_mask = 0,
|
||||
.datx8_2_val = 0,
|
||||
.datx8_3_mask = 0,
|
||||
.datx8_3_val = 0,
|
||||
.datx8_4_mask = 0,
|
||||
.datx8_4_val = ((1 << 0)),
|
||||
.datx8_5_mask = DXEN_MASK,
|
||||
.datx8_5_val = 0,
|
||||
.datx8_6_mask = DXEN_MASK,
|
||||
.datx8_6_val = 0,
|
||||
.datx8_7_mask = DXEN_MASK,
|
||||
.datx8_7_val = 0,
|
||||
.datx8_8_mask = DXEN_MASK,
|
||||
.datx8_8_val = 0,
|
||||
.pir_v2 = 0x00000F81ul,
|
||||
};
|
||||
|
||||
static struct ddr3_emif_config ddr3_800_2g = {
|
||||
.sdcfg = 0x62005662ul,
|
||||
.sdtim1 = 0x0A385033ul,
|
||||
.sdtim2 = 0x00001CA5ul,
|
||||
.sdtim3 = 0x21ADFF32ul,
|
||||
.sdtim4 = 0x533F067Ful,
|
||||
.zqcfg = 0x70073200ul,
|
||||
.sdrfc = 0x00000C34ul,
|
||||
};
|
||||
|
||||
static struct ddr3_emif_config ddr3_1066_2g = {
|
||||
.sdcfg = 0x62005662ul,
|
||||
.sdtim1 = 0x0E4C6843ul,
|
||||
.sdtim2 = 0x00001CC6ul,
|
||||
.sdtim3 = 0x323DFF32ul,
|
||||
.sdtim4 = 0x533F08AFul,
|
||||
.zqcfg = 0x70073200ul,
|
||||
.sdrfc = 0x00001044ul,
|
||||
};
|
||||
|
||||
/* K2G ICE evm DDR3 Configuration */
|
||||
static struct ddr3_phy_config ddr3phy_800_512mb = {
|
||||
.pllcr = 0x000DC000ul,
|
||||
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
|
||||
.pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
|
||||
.ptr0 = 0x42C21590ul,
|
||||
.ptr1 = 0xD05612C0ul,
|
||||
.ptr2 = 0,
|
||||
.ptr3 = 0x06C30D40ul,
|
||||
.ptr4 = 0x06413880ul,
|
||||
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
|
||||
.dcr_val = ((1 << 10)),
|
||||
.dtpr0 = 0x550E6644ul,
|
||||
.dtpr1 = 0x32834200ul,
|
||||
.dtpr2 = 0x50022A00ul,
|
||||
.mr0 = 0x00001430ul,
|
||||
.mr1 = 0x00000006ul,
|
||||
.mr2 = 0x00000008ul,
|
||||
.dtcr = 0x710035C7ul,
|
||||
.pgcr2 = 0x00F03D09ul,
|
||||
.zq0cr1 = 0x0001005Dul,
|
||||
.zq1cr1 = 0x0001005Bul,
|
||||
.zq2cr1 = 0x0001005Bul,
|
||||
.pir_v1 = 0x00000033ul,
|
||||
.datx8_2_mask = DXEN_MASK,
|
||||
.datx8_2_val = 0,
|
||||
.datx8_3_mask = DXEN_MASK,
|
||||
.datx8_3_val = 0,
|
||||
.datx8_4_mask = DXEN_MASK,
|
||||
.datx8_4_val = 0,
|
||||
.datx8_5_mask = DXEN_MASK,
|
||||
.datx8_5_val = 0,
|
||||
.datx8_6_mask = DXEN_MASK,
|
||||
.datx8_6_val = 0,
|
||||
.datx8_7_mask = DXEN_MASK,
|
||||
.datx8_7_val = 0,
|
||||
.datx8_8_mask = DXEN_MASK,
|
||||
.datx8_8_val = 0,
|
||||
.pir_v2 = 0x00000F81ul,
|
||||
};
|
||||
|
||||
static struct ddr3_emif_config ddr3_800_512mb = {
|
||||
.sdcfg = 0x62006662ul,
|
||||
.sdtim1 = 0x0A385033ul,
|
||||
.sdtim2 = 0x00001CA5ul,
|
||||
.sdtim3 = 0x21ADFF32ul,
|
||||
.sdtim4 = 0x533F067Ful,
|
||||
.zqcfg = 0x70073200ul,
|
||||
.sdrfc = 0x00000C34ul,
|
||||
};
|
||||
|
||||
u32 ddr3_init(void)
|
||||
{
|
||||
/* Reset DDR3 PHY after PLL enabled */
|
||||
ddr3_reset_ddrphy();
|
||||
if (board_is_k2g_g1()) {
|
||||
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g);
|
||||
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1066_2g);
|
||||
} else if (board_is_k2g_gp()) {
|
||||
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
|
||||
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
|
||||
} else if (board_is_k2g_ice()) {
|
||||
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb);
|
||||
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
inline int ddr3_get_size(void)
|
||||
{
|
||||
return 2;
|
||||
}
|
||||
@@ -0,0 +1,67 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Keystone2: DDR3 initialization
|
||||
*
|
||||
* (C) Copyright 2012-2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "ddr3_cfg.h"
|
||||
#include <asm/arch/ddr3.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
|
||||
struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
|
||||
|
||||
u32 ddr3_init(void)
|
||||
{
|
||||
u32 ddr3_size;
|
||||
struct ddr3_spd_cb spd_cb;
|
||||
|
||||
if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
|
||||
printf("Sorry, I don't know how to configure DDR3A.\n"
|
||||
"Bye :(\n");
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
|
||||
|
||||
if ((cpu_revision() > 1) ||
|
||||
(__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) {
|
||||
printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
|
||||
if (spd_cb.ddrspdclock == 1600)
|
||||
init_pll(&ddr3a_400);
|
||||
else
|
||||
init_pll(&ddr3a_333);
|
||||
}
|
||||
|
||||
if (cpu_revision() > 0) {
|
||||
if (cpu_revision() > 1) {
|
||||
/* PG 2.0 */
|
||||
/* Reset DDR3A PHY after PLL enabled */
|
||||
ddr3_reset_ddrphy();
|
||||
spd_cb.phy_cfg.zq0cr1 |= 0x10000;
|
||||
spd_cb.phy_cfg.zq1cr1 |= 0x10000;
|
||||
spd_cb.phy_cfg.zq2cr1 |= 0x10000;
|
||||
}
|
||||
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
|
||||
|
||||
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
|
||||
|
||||
ddr3_size = spd_cb.ddr_size_gbyte;
|
||||
} else {
|
||||
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
|
||||
spd_cb.emif_cfg.sdcfg |= 0x1000;
|
||||
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
|
||||
ddr3_size = spd_cb.ddr_size_gbyte / 2;
|
||||
}
|
||||
printf("DRAM: %d GiB (includes reported below)\n", ddr3_size);
|
||||
|
||||
/* Apply the workaround for PG 1.0 and 1.1 Silicons */
|
||||
if (cpu_revision() <= 1)
|
||||
ddr3_err_reset_workaround();
|
||||
|
||||
return ddr3_size;
|
||||
}
|
||||
@@ -0,0 +1,29 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Keystone2: DDR3 initialization
|
||||
*
|
||||
* (C) Copyright 2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "ddr3_cfg.h"
|
||||
#include <asm/arch/ddr3.h>
|
||||
|
||||
static struct pll_init_data ddr3_400 = DDR3_PLL_400;
|
||||
|
||||
u32 ddr3_init(void)
|
||||
{
|
||||
init_pll(&ddr3_400);
|
||||
|
||||
/* No SO-DIMM, 2GB discreet DDR */
|
||||
printf("DRAM: 2 GiB\n");
|
||||
|
||||
/* Reset DDR3 PHY after PLL enabled */
|
||||
ddr3_reset_ddrphy();
|
||||
|
||||
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
|
||||
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
|
||||
|
||||
return 2;
|
||||
}
|
||||
@@ -0,0 +1,385 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* K2G EVM: Pinmux configuration
|
||||
*
|
||||
* (C) Copyright 2015
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mux-k2g.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include "board.h"
|
||||
|
||||
struct pin_cfg k2g_generic_pin_cfg[] = {
|
||||
/* UART0 */
|
||||
{ 115, MODE(0) }, /* SOC_UART0_RXD */
|
||||
{ 116, MODE(0) }, /* SOC_UART0_TXD */
|
||||
|
||||
/* I2C 0 */
|
||||
{ 223, MODE(0) }, /* SOC_I2C0_SCL */
|
||||
{ 224, MODE(0) }, /* SOC_I2C0_SDA */
|
||||
|
||||
/* I2C 1 */
|
||||
{ 225, MODE(0) }, /* SOC_I2C1_SCL */
|
||||
{ 226, MODE(0) }, /* SOC_I2C1_SDA */
|
||||
{ MAX_PIN_N, }
|
||||
};
|
||||
|
||||
struct pin_cfg k2g_evm_pin_cfg[] = {
|
||||
/* GPMC */
|
||||
{ 0, MODE(0) }, /* GPMCAD0 */
|
||||
{ 1, MODE(0) }, /* GPMCAD1 */
|
||||
{ 2, MODE(0) }, /* GPMCAD2 */
|
||||
{ 3, MODE(0) }, /* GPMCAD3 */
|
||||
{ 4, MODE(0) }, /* GPMCAD4 */
|
||||
{ 5, MODE(0) }, /* GPMCAD5 */
|
||||
{ 6, MODE(0) }, /* GPMCAD6 */
|
||||
{ 7, MODE(0) }, /* GPMCAD7 */
|
||||
{ 8, MODE(0) }, /* GPMCAD8 */
|
||||
{ 9, MODE(0) }, /* GPMCAD9 */
|
||||
{ 10, MODE(0) }, /* GPMCAD10 */
|
||||
{ 11, MODE(0) }, /* GPMCAD11 */
|
||||
{ 12, MODE(0) }, /* GPMCAD12 */
|
||||
{ 13, MODE(0) }, /* GPMCAD13 */
|
||||
{ 14, MODE(0) }, /* GPMCAD14 */
|
||||
{ 15, MODE(0) }, /* GPMCAD15 */
|
||||
{ 17, MODE(0) }, /* GPMCADVNALE */
|
||||
{ 18, MODE(0) }, /* GPMCOENREN */
|
||||
{ 19, MODE(0) }, /* GPMCWEN */
|
||||
{ 20, MODE(0) }, /* GPMCBE0NCLE */
|
||||
{ 22, MODE(0) }, /* GPMCWAIT0 */
|
||||
{ 24, MODE(0) }, /* GPMCWPN */
|
||||
{ 26, MODE(0) }, /* GPMCCSN0 */
|
||||
|
||||
/* GPIOs */
|
||||
{ 16, MODE(3) | PIN_IEN }, /* GPIO0_16 - PRSNT1# */
|
||||
{ 21, MODE(3) | PIN_IEN }, /* GPIO0_21 - DC_BRD_DET */
|
||||
{ 82, MODE(3) | PIN_IEN }, /* GPIO0_82 - TPS_INT1 */
|
||||
{ 83, MODE(3) }, /* GPIO0_83 - TPS_SLEEP */
|
||||
{ 84, MODE(3) }, /* GPIO0_84 - SEL_HDMIn_GPIO */
|
||||
{ 87, MODE(3) }, /* GPIO0_87 - SD_LP2996A */
|
||||
{ 106, MODE(3) | PIN_IEN}, /* GPIO0_100 - SOC_INT */
|
||||
{ 201, MODE(3) | PIN_IEN}, /* GPIO1_26 - GPIO_EXP_INT */
|
||||
{ 202, MODE(3) }, /* GPIO1_27 - SEL_LCDn_GPIO */
|
||||
{ 203, MODE(3) | PIN_IEN}, /* GPIO1_28 - SOC_MLB_GPIO2 */
|
||||
{ 204, MODE(3) | PIN_IEN}, /* GPIO1_29 - SOC_PCIE_WAKEn */
|
||||
{ 205, MODE(3) | PIN_IEN}, /* GPIO1_30 - BMC_INT1 */
|
||||
{ 206, MODE(3) | PIN_IEN}, /* GPIO1_31 - HDMI_INTn*/
|
||||
{ 207, MODE(3) | PIN_IEN}, /* GPIO1_32 - CS2000_AUX_OUT */
|
||||
{ 208, MODE(3) | PIN_IEN}, /* GPIO1_33 - TEMP_INT */
|
||||
{ 209, MODE(3) | PIN_IEN}, /* GPIO1_34 - WLAN_IRQ */
|
||||
{ 216, MODE(3) }, /* GPIO1_41 - FLASH_HOLD */
|
||||
{ 217, MODE(3) | PIN_IEN}, /* GPIO1_42 - TOUCH_INTn */
|
||||
|
||||
/* MLB */
|
||||
{ 23, MODE(2) }, /* SOC_MLBCLK */
|
||||
{ 25, MODE(2) }, /* SOC_MLBSIG */
|
||||
{ 27, MODE(2) }, /* SOC_MLBDAT */
|
||||
|
||||
/* DSS */
|
||||
{ 30, MODE(0) }, /* SOC_DSSDATA23 */
|
||||
{ 31, MODE(0) }, /* SOC_DSSDATA22 */
|
||||
{ 32, MODE(0) }, /* SOC_DSSDATA21 */
|
||||
{ 33, MODE(0) }, /* SOC_DSSDATA20 */
|
||||
{ 34, MODE(0) }, /* SOC_DSSDATA19 */
|
||||
{ 35, MODE(0) }, /* SOC_DSSDATA18 */
|
||||
{ 36, MODE(0) }, /* SOC_DSSDATA17 */
|
||||
{ 37, MODE(0) }, /* SOC_DSSDATA16 */
|
||||
{ 38, MODE(0) }, /* SOC_DSSDATA15 */
|
||||
{ 39, MODE(0) }, /* SOC_DSSDATA14 */
|
||||
{ 40, MODE(0) }, /* SOC_DSSDATA13 */
|
||||
{ 41, MODE(0) }, /* SOC_DSSDATA12 */
|
||||
{ 42, MODE(0) }, /* SOC_DSSDATA11 */
|
||||
{ 43, MODE(0) }, /* SOC_DSSDATA10 */
|
||||
{ 44, MODE(0) }, /* SOC_DSSDATA9 */
|
||||
{ 45, MODE(0) }, /* SOC_DSSDATA8 */
|
||||
{ 46, MODE(0) }, /* SOC_DSSDATA7 */
|
||||
{ 47, MODE(0) }, /* SOC_DSSDATA6 */
|
||||
{ 48, MODE(0) }, /* SOC_DSSDATA5 */
|
||||
{ 49, MODE(0) }, /* SOC_DSSDATA4 */
|
||||
{ 50, MODE(0) }, /* SOC_DSSDATA3 */
|
||||
{ 51, MODE(0) }, /* SOC_DSSDATA2 */
|
||||
{ 52, MODE(0) }, /* SOC_DSSDATA1 */
|
||||
{ 53, MODE(0) }, /* SOC_DSSDATA0 */
|
||||
{ 54, MODE(0) }, /* SOC_DSSVSYNC */
|
||||
{ 55, MODE(0) }, /* SOC_DSSHSYNC */
|
||||
{ 56, MODE(0) }, /* SOC_DSSPCLK */
|
||||
{ 57, MODE(0) }, /* SOC_DSS_DE */
|
||||
{ 58, MODE(0) }, /* SOC_DSS_FID */
|
||||
{ 221, MODE(4) }, /* PWM0 - SOC_BACKLIGHT_PWM */
|
||||
|
||||
/* MMC1 */
|
||||
{ 59, MODE(0) }, /* SOC_MMC1_DAT7 */
|
||||
{ 60, MODE(0) }, /* SOC_MMC1_DAT6 */
|
||||
{ 61, MODE(0) }, /* SOC_MMC1_DAT5 */
|
||||
{ 62, MODE(0) }, /* SOC_MMC1_DAT4 */
|
||||
{ 63, MODE(0) }, /* SOC_MMC1_DAT3 */
|
||||
{ 64, MODE(0) }, /* SOC_MMC1_DAT2 */
|
||||
{ 65, MODE(0) }, /* SOC_MMC1_DAT1 */
|
||||
{ 66, MODE(0) }, /* SOC_MMC1_DAT0 */
|
||||
{ 67, MODE(0) }, /* SOC_MMC1_CLK */
|
||||
{ 68, MODE(0) }, /* SOC_MMC1_CMD */
|
||||
{ 69, MODE(0) }, /* MMC1SDCD TP125 */
|
||||
{ 70, MODE(0) }, /* SOC_MMC1_SDWP */
|
||||
{ 71, MODE(0) }, /* MMC1POW TP124 */
|
||||
|
||||
/* EMAC */
|
||||
{ 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
|
||||
{ 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */
|
||||
{ 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
|
||||
{ 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
|
||||
{ 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */
|
||||
{ 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
|
||||
{ 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */
|
||||
{ 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
|
||||
{ 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
|
||||
{ 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
|
||||
{ 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
|
||||
{ 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */
|
||||
|
||||
/* MDIO */
|
||||
{ 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */
|
||||
{ 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
|
||||
|
||||
/* PWM */
|
||||
{ 73, MODE(4) }, /* SOC_EHRPWM3A */
|
||||
{ 74, MODE(4) }, /* SOC_EHRPWM3B */
|
||||
{ 75, MODE(4) }, /* SOC_EHRPWM3_SYNCI */
|
||||
{ 76, MODE(4) }, /* SOC_EHRPWM3_SYNCO */
|
||||
{ 96, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT3 */
|
||||
{ 198, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT4 */
|
||||
{ 199, MODE(4) }, /* SOC_EHRPWM4A */
|
||||
{ 200, MODE(4) }, /* SOC_EHRPWM4B */
|
||||
{ 218, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT5 */
|
||||
{ 219, MODE(4) }, /* SOC_EHRPWM5A */
|
||||
{ 220, MODE(4) }, /* SOC_EHRPWM5B */
|
||||
{ 222, MODE(4) }, /* SOC_ECAP1_IN_PWM1_OUT */
|
||||
|
||||
/* SPI3 */
|
||||
{ 86, MODE(1) }, /* SOC_SPI3_SCS0 */
|
||||
{ 88, MODE(1) }, /* SOC_SPI3_CLK */
|
||||
{ 89, MODE(1) }, /* SOC_SPI3_MISO */
|
||||
{ 90, MODE(1) }, /* SOC_SPI3_MOSI */
|
||||
|
||||
/* CLK */
|
||||
{ 97, MODE(0) }, /* SMD - TP132 */
|
||||
|
||||
/* SPI0 */
|
||||
{ 100, MODE(0) }, /* SOC_SPI0_SCS0 */
|
||||
{ 101, MODE(0) }, /* SOC_SPI0_SCS1 */
|
||||
{ 102, MODE(0) }, /* SOC_SPI0_CLK */
|
||||
{ 103, MODE(0) }, /* SOC_SPI0_MISO */
|
||||
{ 104, MODE(0) }, /* SOC_SPI0_MOSI */
|
||||
|
||||
/* SPI1 NORFLASH */
|
||||
{ 105, MODE(0) }, /* SOC_SPI1_SCS0 */
|
||||
{ 107, MODE(0) }, /* SOC_SPI1_CLK */
|
||||
{ 108, MODE(0) }, /* SOC_SPI1_MISO */
|
||||
{ 109, MODE(0) }, /* SOC_SPI1_MOSI */
|
||||
|
||||
/* SPI2 */
|
||||
{ 110, MODE(0) }, /* SOC_SPI2_SCS0 */
|
||||
{ 111, MODE(1) }, /* SOC_HOUT */
|
||||
{ 112, MODE(0) }, /* SOC_SPI2_CLK */
|
||||
{ 113, MODE(0) }, /* SOC_SPI2_MISO */
|
||||
{ 114, MODE(0) }, /* SOC_SPI2_MOSI */
|
||||
|
||||
/* UART0 */
|
||||
{ 115, MODE(0) }, /* SOC_UART0_RXD */
|
||||
{ 116, MODE(0) }, /* SOC_UART0_TXD */
|
||||
{ 117, MODE(0) }, /* SOC_UART0_CTSn */
|
||||
{ 118, MODE(0) }, /* SOC_UART0_RTSn */
|
||||
|
||||
/* UART1 */
|
||||
{ 119, MODE(0) }, /* SOC_UART1_RXD */
|
||||
{ 120, MODE(0) }, /* SOC_UART1_TXD */
|
||||
{ 121, MODE(0) }, /* SOC_UART1_CTSn */
|
||||
{ 122, MODE(0) }, /* SOC_UART1_RTSn */
|
||||
|
||||
/* UART2 */
|
||||
{ 123, MODE(0) }, /* SOC_UART2_RXD */
|
||||
{ 124, MODE(0) }, /* SOC_UART2_TXD */
|
||||
{ 125, MODE(0) }, /* UART0_TXVR_EN */
|
||||
{ 126, MODE(4) }, /* SOC_CPTS_TS_COMP */
|
||||
|
||||
/* DCAN */
|
||||
{ 127, MODE(0) }, /* SOC_DCAN0_TX */
|
||||
{ 128, MODE(0) }, /* SOC_DCAN0_RX */
|
||||
{ 137, MODE(1) }, /* SOC_DCAN1_TX */
|
||||
{ 138, MODE(1) }, /* SOC_DCAN1_RX */
|
||||
|
||||
/* QSPI */
|
||||
{ 129, MODE(0) }, /* SOC_QSPI_CLK */
|
||||
{ 130, MODE(0) }, /* SOC_QSPI_RTCLK */
|
||||
{ 131, MODE(0) }, /* SOC_QSPI_D0 */
|
||||
{ 132, MODE(0) }, /* SOC_QSPI_D1 */
|
||||
{ 133, MODE(0) }, /* SOC_QSPI_D2 */
|
||||
{ 134, MODE(0) }, /* SOC_QSPI_D3 */
|
||||
{ 135, MODE(0) }, /* SOC_QSPI_CSN0 */
|
||||
{ 136, MODE(1) }, /* DNI <-> WLAN_SLOW_CLK */
|
||||
|
||||
/* MCASP2 */
|
||||
{ 139, MODE(3) }, /* SOC_MCASP2AXR0 - (GPIO0_108)SOC_LED0 */
|
||||
{ 140, MODE(4) }, /* SOC_MCASP2AXR1 */
|
||||
{ 141, MODE(4) }, /* SOC_MCASP2AXR2 */
|
||||
{ 142, MODE(4) }, /* SOC_MCASP2AXR3 */
|
||||
{ 143, MODE(4) }, /* SOC_MCASP2AXR4 */
|
||||
{ 144, MODE(4) }, /* SOC_MCASP2AXR5 */
|
||||
{ 145, MODE(4) }, /* SOC_McASP2ACLKR */
|
||||
{ 146, MODE(4) }, /* SOC_McASP2FSR */
|
||||
{ 147, MODE(4) }, /* SOC_McASP2AHCLKR */
|
||||
{ 148, MODE(3) }, /* GPIO0_117 - WLAN_TRANS_EN */
|
||||
{ 149, MODE(4) }, /* SOC_McASP2FSX */
|
||||
{ 150, MODE(4) }, /* SOC_McASP2AHCLKX */
|
||||
{ 151, MODE(4) }, /* SOC_McASP2ACLKX */
|
||||
|
||||
/* MCASP1 */
|
||||
{ 152, MODE(4) }, /* SOC_MCASP1ACLKR */
|
||||
{ 153, MODE(4) }, /* SOC_MCASP1FSR */
|
||||
{ 154, MODE(4) }, /* SOC_MCASP1AHCLKR */
|
||||
{ 155, MODE(4) }, /* SOC_MCASP1ACLKX */
|
||||
{ 156, MODE(4) }, /* SOC_MCASP1FSX */
|
||||
{ 157, MODE(4) }, /* SOC_MCASP1AHCLKX */
|
||||
{ 158, MODE(4) }, /* SOC_MCASP1AMUTE */
|
||||
{ 159, MODE(4) }, /* SOC_MCASP1AXR0 */
|
||||
{ 160, MODE(4) }, /* SOC_MCASP1AXR1 */
|
||||
{ 161, MODE(4) }, /* SOC_MCASP1AXR2 */
|
||||
{ 162, MODE(4) }, /* SOC_MCASP1AXR3 */
|
||||
{ 163, MODE(4) }, /* SOC_MCASP1AXR4 */
|
||||
{ 164, MODE(4) }, /* SOC_MCASP1AXR5 */
|
||||
{ 165, MODE(4) }, /* SOC_MCASP1AXR6 */
|
||||
{ 166, MODE(4) }, /* SOC_MCASP1AXR7 */
|
||||
{ 167, MODE(4) }, /* SOC_MCASP1AXR8 */
|
||||
{ 168, MODE(4) }, /* SOC_MCASP1AXR9 */
|
||||
|
||||
/* MCASP0 */
|
||||
{ 169, MODE(4) }, /* SOC_MCASP0AMUTE */
|
||||
{ 170, MODE(4) }, /* SOC_MCASP0ACLKR */
|
||||
{ 171, MODE(4) }, /* SOC_MCASP0FSR */
|
||||
{ 172, MODE(4) }, /* SOC_MCASP0AHCLKR */
|
||||
{ 173, MODE(4) }, /* SOC_MCASP0ACLKX */
|
||||
{ 174, MODE(4) }, /* SOC_MCASP0FSX */
|
||||
{ 175, MODE(4) }, /* SOC_MCASP0AHCLKX */
|
||||
{ 176, MODE(4) }, /* SOC_MCASP0AXR0 */
|
||||
{ 177, MODE(4) }, /* SOC_MCASP0AXR1 */
|
||||
{ 178, MODE(4) }, /* SOC_MCASP0AXR2 */
|
||||
{ 179, MODE(4) }, /* SOC_MCASP0AXR3 */
|
||||
{ 180, MODE(4) }, /* SOC_MCASP0AXR4 */
|
||||
{ 181, MODE(4) }, /* SOC_MCASP0AXR5 */
|
||||
{ 182, MODE(4) }, /* SOC_MCASP0AXR6 */
|
||||
{ 183, MODE(4) }, /* SOC_MCASP0AXR7 */
|
||||
{ 184, MODE(4) }, /* SOC_MCASP0AXR8 */
|
||||
{ 185, MODE(4) }, /* SOC_MCASP0AXR9 */
|
||||
{ 186, MODE(3) }, /* SOC_MCASP0AXR10 - (GPIO1_11)SOC_LED1 */
|
||||
{ 188, MODE(4) }, /* SOC_MCASP0AXR12 */
|
||||
{ 189, MODE(4) }, /* SOC_MCASP0AXR13 */
|
||||
{ 190, MODE(4) }, /* SOC_MCASP0AXR14 */
|
||||
{ 191, MODE(4) }, /* SOC_MCASP0AXR15 */
|
||||
|
||||
/* MMC0 */
|
||||
{ 192, MODE(2) }, /* SOC_MMC0_DAT3 */
|
||||
{ 193, MODE(2) }, /* SOC_MMC0_DAT2 */
|
||||
{ 194, MODE(2) }, /* SOC_MMC0_DAT1 */
|
||||
{ 195, MODE(2) }, /* SOC_MMC0_DAT0 */
|
||||
{ 196, MODE(2) }, /* SOC_MMC0_CLK */
|
||||
{ 197, MODE(2) }, /* SOC_MMC0_CMD */
|
||||
{ 187, MODE(2) }, /* SOC_MMC0_SDCD */
|
||||
|
||||
/* McBSP */
|
||||
{ 28, MODE(2) | PIN_IEN }, /* SOC_TIMI1 */
|
||||
{ 29, MODE(2) }, /* SOC_TIMO1 */
|
||||
{ 210, MODE(2) }, /* SOC_MCBSPDR */
|
||||
{ 211, MODE(2) }, /* SOC_MCBSPDX */
|
||||
{ 212, MODE(2) }, /* SOC_MCBSPFSX */
|
||||
{ 213, MODE(2) }, /* SOC_MCBSPCLKX */
|
||||
{ 214, MODE(2) }, /* SOC_MCBSPFSR */
|
||||
{ 215, MODE(2) }, /* SOC_MCBSPCLKR */
|
||||
|
||||
/* I2C */
|
||||
{ 223, MODE(0) }, /* SOC_I2C0_SCL */
|
||||
{ 224, MODE(0) }, /* SOC_I2C0_SDA */
|
||||
{ 225, MODE(0) }, /* SOC_I2C1_SCL */
|
||||
{ 226, MODE(0) }, /* SOC_I2C1_SDA */
|
||||
{ 227, MODE(0) }, /* SOC_I2C2_SCL */
|
||||
{ 228, MODE(0) }, /* SOC_I2C2_SDA */
|
||||
{ 229, MODE(0) }, /* NMIz */
|
||||
{ 230, MODE(0) }, /* LRESETz */
|
||||
{ 231, MODE(0) }, /* LRESETNMIENz */
|
||||
|
||||
{ 235, MODE(0) },
|
||||
{ 236, MODE(0) },
|
||||
{ 237, MODE(0) },
|
||||
{ 238, MODE(0) },
|
||||
{ 239, MODE(0) },
|
||||
{ 240, MODE(0) },
|
||||
{ 241, MODE(0) },
|
||||
{ 242, MODE(0) },
|
||||
{ 243, MODE(0) },
|
||||
{ 244, MODE(0) },
|
||||
|
||||
{ 258, MODE(0) }, /* USB0DRVVBUS */
|
||||
{ 259, MODE(0) }, /* USB1DRVVBUS */
|
||||
{ MAX_PIN_N, }
|
||||
};
|
||||
|
||||
struct pin_cfg k2g_ice_evm_pin_cfg[] = {
|
||||
/* MMC 1 */
|
||||
{ 63, MODE(0) | PIN_PTD }, /* MMC1_DAT3.MMC1_DAT3 */
|
||||
{ 64, MODE(0) | PIN_PTU }, /* MMC1_DAT2.MMC1_DAT2 */
|
||||
{ 65, MODE(0) | PIN_PTU }, /* MMC1_DAT1.MMC1_DAT1 */
|
||||
{ 66, MODE(0) | PIN_PTD }, /* MMC1_DAT0.MMC1_DAT0 */
|
||||
{ 67, MODE(0) | PIN_PTD }, /* MMC1_CLK.MMC1_CLK */
|
||||
{ 68, MODE(0) | PIN_PTD }, /* MMC1_CMD.MMC1_CMD */
|
||||
{ 69, MODE(3) | PIN_PTU }, /* MMC1_SDCD.GPIO0_69 */
|
||||
{ 70, MODE(0) | PIN_PTU }, /* MMC1_SDWP.MMC1_SDWP */
|
||||
{ 71, MODE(0) | PIN_PTD }, /* MMC1_POW.MMC1_POW */
|
||||
|
||||
/* I2C 0 */
|
||||
{ 223, MODE(0) }, /* SOC_I2C0_SCL */
|
||||
{ 224, MODE(0) }, /* SOC_I2C0_SDA */
|
||||
|
||||
/* QSPI */
|
||||
{ 129, MODE(0) }, /* SOC_QSPI_CLK */
|
||||
{ 130, MODE(0) }, /* SOC_QSPI_RTCLK */
|
||||
{ 131, MODE(0) }, /* SOC_QSPI_D0 */
|
||||
{ 132, MODE(0) }, /* SOC_QSPI_D1 */
|
||||
{ 133, MODE(0) }, /* SOC_QSPI_D2 */
|
||||
{ 134, MODE(0) }, /* SOC_QSPI_D3 */
|
||||
{ 135, MODE(0) }, /* SOC_QSPI_CSN0 */
|
||||
|
||||
/* EMAC */
|
||||
{ 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
|
||||
{ 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */
|
||||
{ 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
|
||||
{ 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
|
||||
{ 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */
|
||||
{ 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
|
||||
{ 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */
|
||||
{ 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
|
||||
{ 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
|
||||
{ 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
|
||||
{ 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
|
||||
{ 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */
|
||||
|
||||
/* MDIO */
|
||||
{ 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */
|
||||
{ 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
|
||||
|
||||
{ MAX_PIN_N, }
|
||||
};
|
||||
|
||||
void k2g_mux_config(void)
|
||||
{
|
||||
if (!board_ti_was_eeprom_read()) {
|
||||
configure_pin_mux(k2g_generic_pin_cfg);
|
||||
} else if (board_is_k2g_gp() || board_is_k2g_g1()) {
|
||||
configure_pin_mux(k2g_evm_pin_cfg);
|
||||
} else if (board_is_k2g_ice()) {
|
||||
configure_pin_mux(k2g_ice_evm_pin_cfg);
|
||||
} else {
|
||||
puts("Unknown board, cannot configure pinmux.");
|
||||
hang();
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user