GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,30 @@
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if TARGET_APALIS_IMX8
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config SYS_BOARD
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default "apalis-imx8"
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config SYS_VENDOR
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default "toradex"
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config SYS_CONFIG_NAME
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default "apalis-imx8"
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config TDX_CFG_BLOCK
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default y
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config TDX_HAVE_MMC
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default y
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config TDX_CFG_BLOCK_DEV
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default "0"
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config TDX_CFG_BLOCK_PART
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default "1"
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# Toradex config block in eMMC, at the end of 1st "boot sector"
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config TDX_CFG_BLOCK_OFFSET
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default "-512"
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source "board/toradex/common/Kconfig"
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endif
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@@ -0,0 +1,9 @@
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Apalis iMX8
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M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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W: http://developer.toradex.com/software/linux/linux-software
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S: Maintained
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F: arch/arm/dts/fsl-imx8-apalis.dts
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F: arch/arm/dts/fsl-imx8-apalis-u-boot.dtsi
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F: board/toradex/apalis-imx8/
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F: configs/apalis-imx8qm_defconfig
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F: include/configs/apalis-imx8.h
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@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2019 Toradex
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#
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obj-y += apalis-imx8.o
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@@ -0,0 +1,66 @@
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U-Boot for the Toradex Apalis iMX8QM V1.0B Module
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Quick Start
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===========
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- Build the ARM trusted firmware binary
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- Get scfw_tcm.bin and ahab-container.img
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- Build U-Boot
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- Load U-Boot binary using uuu
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- Flash U-Boot binary into the eMMC
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- Boot
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Get and Build the ARM Trusted Firmware
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======================================
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$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
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$ cd imx-atf/
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$ make PLAT=imx8qm bl31
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Get scfw_tcm.bin and ahab-container.img
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=======================================
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$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qm-apalis-scfw-tcm.bin?raw=true
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$ mv mx8qm-apalis-scfw-tcm.bin\?raw\=true mx8qm-apalis-scfw-tcm.bin
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$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
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$ chmod +x firmware-imx-8.0.bin
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$ ./firmware-imx-8.0.bin
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Copy the following binaries to the U-Boot folder:
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$ cp imx-atf/build/imx8qm/release/bl31.bin .
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$ cp u-boot/u-boot.bin .
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Copy the following firmware to the U-Boot folder:
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$ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
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Build U-Boot
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============
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$ make apalis-imx8qm_defconfig
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$ make u-boot-dtb.imx
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Load the U-Boot Binary Using UUU
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================================
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Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
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https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
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Put the module into USB recovery aka serial downloader mode, connect USB device
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to your host and execute uuu:
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sudo ./uuu u-boot/u-boot-dtb.imx
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Flash the U-Boot Binary into the eMMC
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=====================================
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Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
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load mmc 1:1 $loadaddr u-boot-dtb.imx
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setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
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mmc dev 0 1
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mmc write ${loadaddr} 0x0 ${blkcnt}
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Boot
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@@ -0,0 +1,126 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Toradex
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8-pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sci/sci.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <env.h>
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#include <errno.h>
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#include <linux/libfdt.h>
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#include "../common/tdx-cfg-block.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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static iomux_cfg_t uart1_pads[] = {
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SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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int board_early_init_f(void)
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{
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sc_pm_clock_rate_t rate = SC_80MHZ;
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sc_err_t err = 0;
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/* Set UART1 clock root to 80 MHz and enable it */
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err = sc_pm_setup_uart(SC_R_UART_1, rate);
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if (err != SC_ERR_NONE)
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return 0;
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setup_iomux_uart();
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return 0;
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}
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#if IS_ENABLED(CONFIG_DM_GPIO)
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static void board_gpio_init(void)
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{
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/* TODO */
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}
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#else
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static inline void board_gpio_init(void) {}
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#endif
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#if IS_ENABLED(CONFIG_FEC_MXC)
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#include <miiphy.h>
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int checkboard(void)
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{
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puts("Model: Toradex Apalis iMX8\n");
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build_info();
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print_bootinfo();
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return 0;
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}
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int board_init(void)
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{
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board_gpio_init();
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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}
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/*
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* Board specific reset that is system reset.
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*/
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void reset_cpu(ulong addr)
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{
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/* TODO */
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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return ft_common_board_setup(blob, bd);
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}
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#endif
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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/* TODO move to common */
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env_set("board_name", "Apalis iMX8QM");
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env_set("board_rev", "v1.0");
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#endif
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return 0;
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}
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@@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 Toradex
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*
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* Refer doc/README.imx8image for more details about how-to configure
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* and create imx8image boot image
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*/
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#define __ASSEMBLY__
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/* Boot from SD, sector size 0x400 */
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BOOT_FROM EMMC_FASTBOOT 0x400
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/* SoC type IMX8QM */
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SOC_TYPE IMX8QM
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/* Append seco container image */
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APPEND mx8qm-ahab-container.img
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/* Create the 2nd container */
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CONTAINER
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/* Add scfw image with exec attribute */
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IMAGE SCU mx8qm-apalis-scfw-tcm.bin
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/* Add ATF image with exec attribute */
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IMAGE A35 bl31.bin 0x80000000
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/* Add U-Boot image with load attribute */
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DATA A35 u-boot-dtb.bin 0x80020000
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@@ -0,0 +1,38 @@
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if TARGET_APALIS_TK1
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config SYS_BOARD
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default "apalis-tk1"
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config SYS_VENDOR
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default "toradex"
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config SYS_CONFIG_NAME
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default "apalis-tk1"
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config TDX_CFG_BLOCK
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default y
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config TDX_HAVE_MMC
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default y
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config TDX_CFG_BLOCK_DEV
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default "0"
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config TDX_CFG_BLOCK_PART
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default "1"
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# Toradex config block in eMMC, at the end of 1st "boot sector"
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config TDX_CFG_BLOCK_OFFSET
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default "-512"
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config APALIS_TK1_PCIE_EVALBOARD_INIT
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bool "Apalis Evaluation Board PCIe Initialisation"
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help
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Bring up the Apalis PCIe port with the PCIe switch as found on the
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Apalis Evaluation board. Note that by default the PCIe port is also
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left disabled in the device tree which needs changing as well for this
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to actually work.
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source "board/toradex/common/Kconfig"
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endif
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@@ -0,0 +1,7 @@
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Apalis TK1
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M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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S: Maintained
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F: board/toradex/apalis-tk1/
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F: include/configs/apalis-tk1.h
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F: configs/apalis-tk1_defconfig
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F: arch/arm/dts/tegra124-apalis.dtb
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@@ -0,0 +1,5 @@
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# Copyright (c) 2016 Toradex, Inc.
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# SPDX-License-Identifier: GPL-2.0+
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obj-y += as3722_init.o
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obj-y += apalis-tk1.o
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@@ -0,0 +1,298 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016-2018 Toradex, Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pinmux.h>
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#include <env_internal.h>
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#include <pci_tegra.h>
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#include <power/as3722.h>
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#include <power/pmic.h>
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#include "../common/tdx-common.h"
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#include "pinmux-config-apalis-tk1.h"
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#define LAN_DEV_OFF_N TEGRA_GPIO(O, 6)
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#define LAN_RESET_N TEGRA_GPIO(S, 2)
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#define FAN_EN TEGRA_GPIO(DD, 2)
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#define LAN_WAKE_N TEGRA_GPIO(O, 5)
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#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
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#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
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#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
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#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
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#define VCC_USBH TEGRA_GPIO(T, 6)
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#define VCC_USBH_V1_0 TEGRA_GPIO(N, 5)
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#define VCC_USBO1 TEGRA_GPIO(T, 5)
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#define VCC_USBO1_V1_0 TEGRA_GPIO(N, 4)
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int arch_misc_init(void)
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{
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if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
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NVBOOTTYPE_RECOVERY)
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printf("USB recovery mode\n");
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/* PCB Version Indication: V1.2 and later have GPIO_PV0 wired to GND */
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gpio_request(TEGRA_GPIO(V, 0), "PCB Version Indication");
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gpio_direction_input(TEGRA_GPIO(V, 0));
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if (gpio_get_value(TEGRA_GPIO(V, 0))) {
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/*
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* if using the default device tree for new V1.2 and later HW,
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* use version for older V1.0 and V1.1 HW
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*/
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char *fdt_env = env_get("fdt_module");
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if (fdt_env && !strcmp(FDT_MODULE, fdt_env)) {
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env_set("fdt_module", FDT_MODULE_V1_0);
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printf("patching fdt_module to " FDT_MODULE_V1_0
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" for older V1.0 and V1.1 HW\n");
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#ifndef CONFIG_ENV_IS_NOWHERE
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env_save();
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#endif
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}
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/* activate USB power enable GPIOs */
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gpio_request(VCC_USBH_V1_0, "VCC_USBH");
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gpio_direction_output(VCC_USBH_V1_0, 1);
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gpio_request(VCC_USBO1_V1_0, "VCC_USBO1");
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gpio_direction_output(VCC_USBO1_V1_0, 1);
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} else {
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/* activate USB power enable GPIOs */
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gpio_request(VCC_USBH, "VCC_USBH");
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gpio_direction_output(VCC_USBH, 1);
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gpio_request(VCC_USBO1, "VCC_USBO1");
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gpio_direction_output(VCC_USBO1, 1);
|
||||
}
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return 0;
|
||||
}
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int checkboard(void)
|
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{
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puts("Model: Toradex Apalis TK1 2GB\n");
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||||
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return 0;
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||||
}
|
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|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
return ft_common_board_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_clear_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(apalis_tk1_gpio_inits,
|
||||
ARRAY_SIZE(apalis_tk1_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(apalis_tk1_pingrps,
|
||||
ARRAY_SIZE(apalis_tk1_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
|
||||
ARRAY_SIZE(apalis_tk1_drvgrps));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI_TEGRA
|
||||
/* TODO: Convert to driver model */
|
||||
static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (sd > 6)
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||||
return -EINVAL;
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||||
|
||||
err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
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||||
if (err) {
|
||||
pr_err("failed to update SD control register: %d", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* TODO: Convert to driver model */
|
||||
static int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
|
||||
{
|
||||
int err;
|
||||
u8 ctrl_reg = AS3722_LDO_CONTROL0;
|
||||
|
||||
if (ldo > 11)
|
||||
return -EINVAL;
|
||||
|
||||
if (ldo > 7) {
|
||||
ctrl_reg = AS3722_LDO_CONTROL1;
|
||||
ldo -= 8;
|
||||
}
|
||||
|
||||
err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo);
|
||||
if (err) {
|
||||
pr_err("failed to update LDO control register: %d", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_pcie_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_PMIC,
|
||||
DM_GET_DRIVER(pmic_as3722), &dev);
|
||||
if (ret) {
|
||||
pr_err("failed to find AS3722 PMIC: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = as3722_sd_enable(dev, 4);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to enable SD4: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = as3722_sd_set_voltage(dev, 4, 0x24);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to set SD4 voltage: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N");
|
||||
gpio_request(LAN_RESET_N, "LAN_RESET_N");
|
||||
gpio_request(LAN_WAKE_N, "LAN_WAKE_N");
|
||||
|
||||
#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
|
||||
gpio_request(PEX_PERST_N, "PEX_PERST_N");
|
||||
gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
|
||||
#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
|
||||
{
|
||||
int index = tegra_pcie_port_index_of_port(port);
|
||||
|
||||
if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_PMIC,
|
||||
DM_GET_DRIVER(pmic_as3722),
|
||||
&dev);
|
||||
if (ret) {
|
||||
debug("%s: Failed to find PMIC\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Reset I210 Gigabit Ethernet Controller */
|
||||
gpio_direction_output(LAN_RESET_N, 0);
|
||||
|
||||
/*
|
||||
* Make sure we don't get any back feeding from DEV_OFF_N resp.
|
||||
* LAN_WAKE_N
|
||||
*/
|
||||
gpio_direction_output(LAN_DEV_OFF_N, 0);
|
||||
gpio_direction_output(LAN_WAKE_N, 0);
|
||||
|
||||
/* Make sure LDO9 and LDO10 are initially enabled @ 0V */
|
||||
ret = as3722_ldo_enable(dev, 9);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to enable LDO9: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
ret = as3722_ldo_enable(dev, 10);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to enable LDO10: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
ret = as3722_ldo_set_voltage(dev, 9, 0x80);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to set LDO9 voltage: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
ret = as3722_ldo_set_voltage(dev, 10, 0x80);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to set LDO10 voltage: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Make sure controller gets enabled by disabling DEV_OFF_N */
|
||||
gpio_set_value(LAN_DEV_OFF_N, 1);
|
||||
|
||||
/*
|
||||
* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype
|
||||
* V1.0A and sample V1.0B and newer modules
|
||||
*/
|
||||
ret = as3722_ldo_set_voltage(dev, 9, 0xff);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to set LDO9 voltage: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
ret = as3722_ldo_set_voltage(dev, 10, 0xff);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to set LDO10 voltage: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Must be asserted for 100 ms after power and clocks are stable
|
||||
*/
|
||||
mdelay(100);
|
||||
|
||||
gpio_set_value(LAN_RESET_N, 1);
|
||||
} else if (index == 0) { /* Apalis PCIe */
|
||||
#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
|
||||
/*
|
||||
* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis
|
||||
* Evaluation Board
|
||||
*/
|
||||
gpio_direction_output(PEX_PERST_N, 0);
|
||||
gpio_direction_output(RESET_MOCI_CTRL, 0);
|
||||
|
||||
/*
|
||||
* Must be asserted for 100 ms after power and clocks are stable
|
||||
*/
|
||||
mdelay(100);
|
||||
|
||||
gpio_set_value(PEX_PERST_N, 1);
|
||||
/*
|
||||
* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed
|
||||
* Until 900 us After PEX_PERST# De-assertion
|
||||
*/
|
||||
mdelay(1);
|
||||
gpio_set_value(RESET_MOCI_CTRL, 1);
|
||||
#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_PCI_TEGRA */
|
||||
|
||||
/*
|
||||
* Enable/start PWM CPU fan
|
||||
*/
|
||||
void start_cpu_fan(void)
|
||||
{
|
||||
gpio_request(FAN_EN, "FAN_EN");
|
||||
gpio_direction_output(FAN_EN, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Backlight off before OS handover
|
||||
*/
|
||||
void board_preboot_os(void)
|
||||
{
|
||||
gpio_request(TEGRA_GPIO(BB, 5), "BL_ON");
|
||||
gpio_direction_output(TEGRA_GPIO(BB, 5), 0);
|
||||
}
|
||||
@@ -0,0 +1,139 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2012-2016 Toradex, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include "as3722_init.h"
|
||||
|
||||
/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
|
||||
|
||||
void tegra_i2c_ll_write_addr(uint addr, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(addr, ®->cmd_addr0);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void tegra_i2c_ll_write_data(uint data, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(data, ®->cmd_data1);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void pmic_enable_cpu_vdd(void)
|
||||
{
|
||||
debug("%s entry\n", __func__);
|
||||
|
||||
#ifdef AS3722_SD1VOLTAGE_DATA
|
||||
/* Set up VDD_CORE, for boards where OTP is incorrect*/
|
||||
debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
|
||||
/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Make sure all non-fused regulators are down.
|
||||
* That way we're in known state after software reboot from linux
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
|
||||
/*
|
||||
* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.0V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
|
||||
/*
|
||||
* Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.0V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
|
||||
/*
|
||||
* Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.2V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
|
||||
/*
|
||||
* Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set it to value closest to 3.3V, then enable the regulator
|
||||
*
|
||||
* NOTE: We do this early because doing it later seems to hose the CPU
|
||||
* power rail/partition startup. Need to debug.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
|
||||
/*
|
||||
* Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set it to bypass 3.3V straight thru, then enable the regulator
|
||||
*
|
||||
* NOTE: We do this early because doing it later seems to hose the CPU
|
||||
* power rail/partition startup. Need to debug.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
}
|
||||
@@ -0,0 +1,40 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2012-2016 Toradex, Inc.
|
||||
*/
|
||||
|
||||
/* AS3722-PMIC-specific early init regs */
|
||||
|
||||
#define AS3722_I2C_ADDR 0x80
|
||||
|
||||
#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
|
||||
#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
|
||||
#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
|
||||
#define AS3722_SDCONTROL_REG 0x4D
|
||||
|
||||
#define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
|
||||
#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
|
||||
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
|
||||
#define AS3722_LDCONTROL_REG 0x4E
|
||||
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
|
||||
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
|
||||
|
||||
#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
|
||||
#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
|
||||
|
||||
#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
|
||||
#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO1CONTROL_DATA (0x0200 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO1VOLTAGE_DATA (0x7F00 | AS3722_LDO1VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
|
||||
|
||||
#define I2C_SEND_2_BYTES 0x0A02
|
||||
|
||||
void pmic_enable_cpu_vdd(void);
|
||||
@@ -0,0 +1,285 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2016-2019, Toradex, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_APALIS_TK1_H_
|
||||
#define _PINMUX_CONFIG_APALIS_TK1_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config apalis_tk1_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 1, IN),
|
||||
GPIO_INIT(B, 1, IN),
|
||||
GPIO_INIT(C, 0, OUT0),
|
||||
GPIO_INIT(I, 5, IN),
|
||||
GPIO_INIT(I, 6, IN),
|
||||
GPIO_INIT(J, 0, IN),
|
||||
GPIO_INIT(J, 2, IN),
|
||||
GPIO_INIT(K, 2, IN),
|
||||
GPIO_INIT(K, 7, IN),
|
||||
GPIO_INIT(N, 2, OUT1),
|
||||
GPIO_INIT(N, 7, IN),
|
||||
GPIO_INIT(O, 5, IN),
|
||||
GPIO_INIT(Q, 0, OUT0), /* Shift_CTRL_OE[0] */
|
||||
GPIO_INIT(Q, 1, OUT0), /* Shift_CTRL_OE[1] */
|
||||
GPIO_INIT(Q, 2, OUT0), /* Shift_CTRL_OE[2] */
|
||||
GPIO_INIT(Q, 4, OUT0), /* Shift_CTRL_OE[4] */
|
||||
GPIO_INIT(Q, 5, OUT1), /* Shift_CTRL_Dir_Out[0] */
|
||||
GPIO_INIT(Q, 6, OUT1), /* Shift_CTRL_Dir_Out[1] */
|
||||
GPIO_INIT(Q, 7, OUT1), /* Shift_CTRL_Dir_Out[2] */
|
||||
GPIO_INIT(R, 0, OUT0), /* Shift_CTRL_Dir_In[0] */
|
||||
GPIO_INIT(R, 1, OUT0), /* Shift_CTRL_Dir_In[1] */
|
||||
GPIO_INIT(R, 2, OUT0), /* Shift_CTRL_OE[3] */
|
||||
GPIO_INIT(S, 3, OUT0), /* Shift_CTRL_Dir_In[2] */
|
||||
GPIO_INIT(U, 4, OUT0), /* RESET_MOCI_CTRL */
|
||||
GPIO_INIT(V, 0, IN),
|
||||
GPIO_INIT(W, 3, IN),
|
||||
GPIO_INIT(W, 5, IN),
|
||||
GPIO_INIT(BB, 0, IN),
|
||||
GPIO_INIT(BB, 3, OUT0),
|
||||
GPIO_INIT(BB, 4, IN),
|
||||
GPIO_INIT(BB, 5, OUT1),
|
||||
GPIO_INIT(BB, 6, OUT0),
|
||||
GPIO_INIT(CC, 5, IN),
|
||||
GPIO_INIT(DD, 3, IN),
|
||||
GPIO_INIT(EE, 3, IN),
|
||||
GPIO_INIT(EE, 5, IN),
|
||||
GPIO_INIT(FF, 1, IN),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config apalis_tk1_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, rcv_sel */
|
||||
PINCFG(CLK_32K_OUT_PA0, SOC, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_CTS_N_PA1, GMI, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_FS_PA2, HDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PA3, HDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PA4, HDA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PA5, HDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB0, UARTD, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB1, RSVD2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RTS_N_PC0, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG3, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG4, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH0, PWM0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH2, PWM2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH3, PWM3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH7, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI5, RSVD2, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PI6, RSVD1, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ0, RSVD1, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PJ2, RSVD1, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK2, RSVD1, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK7, RSVD2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PN4, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN1_PN5, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(HDMI_INT_PN7, RSVD1, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA4_PO5, ULPI, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DIN_PP1, I2S2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL0_PQ0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL1_PQ1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL2_PQ2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL4_PQ4, KBC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL5_PQ5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL6_PQ6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL7_PQ7, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW0_PR0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW1_PR1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW2_PR2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW4_PR4, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW7_PR7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW9_PS1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW10_PS2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW11_PS3, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW15_PS7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW17_PT1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SCL_PT5, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SDA_PT6, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU1, UARTA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU2, UARTA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU3, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU6, PWM3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CD_N_PV2, RSVD3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(GPIO_W2_AUD_PW2, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_W3_AUD_PW3, SPI6, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_OUT_PW5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PX1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X4_AUD_PX4, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X5_AUD_PX5, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X6_AUD_PX6, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X7_AUD_PX7, SPI2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB0, VGP6, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PBB3, VGP3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB4, VGP4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB5, VGP5, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_REQ_PCC5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_RST_N_PDD1, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_WAKE_N_PDD3, RSVD2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_RST_N_PDD5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
/*
|
||||
* Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka not
|
||||
* tristated and input driver enabled as well as it features some magic
|
||||
* properties even though the external loopback is disabled and the internal
|
||||
* loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
|
||||
* being set to 0xfffd according to the TRM!
|
||||
*/
|
||||
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_LB_IN_PEE5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DP_HPD_PFF0, DP, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN2_PFF1, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PFF2, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(OWR, RSVD2, NORMAL, TRISTATE, OUTPUT, DEFAULT, NORMAL),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config apalis_tk1_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_APALIS_TK1_H */
|
||||
@@ -0,0 +1,55 @@
|
||||
if TARGET_APALIS_IMX6
|
||||
|
||||
config SYS_BOARD
|
||||
default "apalis_imx6"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "apalis_imx6"
|
||||
|
||||
config SYS_CPU
|
||||
default "armv7"
|
||||
|
||||
config SYS_SOC
|
||||
default "mx6"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_HAVE_MMC
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_DEV
|
||||
default "0"
|
||||
|
||||
config TDX_CFG_BLOCK_PART
|
||||
default "1"
|
||||
|
||||
# Toradex config block in eMMC, at the end of 1st "boot sector"
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "-512"
|
||||
|
||||
config TDX_CMD_IMX_MFGR
|
||||
bool "Enable factory testing commands for Toradex iMX 6 modules"
|
||||
help
|
||||
This adds the commands
|
||||
pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
|
||||
If executed on already fused modules it doesn't change any fuse setting.
|
||||
default y
|
||||
|
||||
config TDX_APALIS_IMX6_V1_0
|
||||
bool "Apalis iMX6 V1.0 HW"
|
||||
help
|
||||
Apalis iMX6 V1.0 HW has a different pinout for the UART.
|
||||
The UARTs must be used in DCE mode, RTS/CTS are swapped and
|
||||
thus unusable on standard carrier boards.
|
||||
This option configures DCE mode unconditionally. Whithout this
|
||||
option the config block stating V1.0 HW selects DCE mode,
|
||||
otherwise the UARTs are configuered in DTE mode.
|
||||
default n
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,9 @@
|
||||
Apalis iMX6
|
||||
M: Max Krummenacher <max.krummenacher@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
W: https://www.toradex.com/community
|
||||
S: Maintained
|
||||
F: board/toradex/apalis_imx6/
|
||||
F: include/configs/apalis_imx6.h
|
||||
F: configs/apalis_imx6_defconfig
|
||||
F: arch/arm/dts/imx6-apalis.dts
|
||||
@@ -0,0 +1,5 @@
|
||||
# Copyright (c) 2012-2014 Toradex, Inc.
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-y := apalis_imx6.o do_fuse.o
|
||||
obj-$(CONFIG_TDX_CMD_IMX_MFGR) += pf0100.o
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,97 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2014-2016, Toradex AG
|
||||
*/
|
||||
|
||||
/*
|
||||
* Helpers for i.MX OTP fusing during module production
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#include <console.h>
|
||||
#include <fuse.h>
|
||||
|
||||
static int mfgr_fuse(void)
|
||||
{
|
||||
unsigned val, val6;
|
||||
|
||||
fuse_sense(0, 5, &val);
|
||||
printf("Fuse 0, 5: %8x\n", val);
|
||||
fuse_sense(0, 6, &val6);
|
||||
printf("Fuse 0, 6: %8x\n", val6);
|
||||
fuse_sense(4, 3, &val);
|
||||
printf("Fuse 4, 3: %8x\n", val);
|
||||
fuse_sense(4, 2, &val);
|
||||
printf("Fuse 4, 2: %8x\n", val);
|
||||
if (val6 & 0x10) {
|
||||
puts("BT_FUSE_SEL already fused, will do nothing\n");
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
/* boot cfg */
|
||||
fuse_prog(0, 5, 0x00005062);
|
||||
/* BT_FUSE_SEL */
|
||||
fuse_prog(0, 6, 0x00000010);
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
int ret;
|
||||
puts("Fusing...\n");
|
||||
ret = mfgr_fuse();
|
||||
if (ret == CMD_RET_SUCCESS)
|
||||
puts("done.\n");
|
||||
else
|
||||
puts("failed.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
unsigned val;
|
||||
int ret;
|
||||
int confirmed = argc >= 1 && !strcmp(argv[1], "-y");
|
||||
|
||||
/* can be used in scripts for command availability check */
|
||||
if (argc >= 1 && !strcmp(argv[1], "-n"))
|
||||
return CMD_RET_SUCCESS;
|
||||
|
||||
/* boot cfg */
|
||||
fuse_sense(0, 5, &val);
|
||||
printf("Fuse 0, 5: %8x\n", val);
|
||||
if (val & 0x10) {
|
||||
puts("Fast boot mode already fused, no need to fuse\n");
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
if (!confirmed) {
|
||||
puts("Warning: Programming fuses is an irreversible operation!\n"
|
||||
" Updating to fast boot mode prevents easy\n"
|
||||
" downgrading to previous BSP versions.\n"
|
||||
"\nReally perform this fuse programming? <y/N>\n");
|
||||
if (!confirm_yesno())
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
puts("Fusing fast boot mode...\n");
|
||||
ret = fuse_prog(0, 5, 0x00005072);
|
||||
if (ret == CMD_RET_SUCCESS)
|
||||
puts("done.\n");
|
||||
else
|
||||
puts("failed.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
mfgr_fuse, 1, 0, do_mfgr_fuse,
|
||||
"OTP fusing during module production",
|
||||
""
|
||||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
updt_fuse, 2, 0, do_updt_fuse,
|
||||
"OTP fusing during module update",
|
||||
"updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
|
||||
);
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
@@ -0,0 +1,282 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2014-2019, Toradex AG
|
||||
*/
|
||||
|
||||
/*
|
||||
* Helpers for Freescale PMIC PF0100
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
|
||||
#include "pf0100_otp.inc"
|
||||
#include "pf0100.h"
|
||||
|
||||
/* define for PMIC register dump */
|
||||
/*#define DEBUG */
|
||||
|
||||
#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n"
|
||||
|
||||
/* use Apalis GPIO1 to switch on VPGM, ON: 1 */
|
||||
static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
|
||||
MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 4)
|
||||
};
|
||||
|
||||
unsigned pmic_init(void)
|
||||
{
|
||||
int rc;
|
||||
struct udevice *dev = NULL;
|
||||
unsigned programmed = 0;
|
||||
uchar bus = 1;
|
||||
uchar devid, revid, val;
|
||||
|
||||
puts("PMIC: ");
|
||||
rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
|
||||
if (rc) {
|
||||
printf("failed to get device for PMIC at address 0x%x\n",
|
||||
PFUZE100_I2C_ADDR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* check for errors in PMIC fuses */
|
||||
if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) {
|
||||
puts("i2c pmic INTSTAT3 register read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_BIT_OTP_ECCI) {
|
||||
puts("\n" WARNBAR);
|
||||
puts("WARNING: ecc errors found in pmic fuse banks\n");
|
||||
puts(WARNBAR);
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) {
|
||||
puts("i2c pmic ECC_SE1 register read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_BITS_ECC_SE1) {
|
||||
puts(WARNBAR);
|
||||
puts("WARNING: ecc has made bit corrections in banks 1 to 5\n");
|
||||
puts(WARNBAR);
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) {
|
||||
puts("i2c pmic ECC_SE2 register read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_BITS_ECC_SE2) {
|
||||
puts(WARNBAR);
|
||||
puts("WARNING: ecc has made bit corrections in banks 6 to 10\n"
|
||||
);
|
||||
puts(WARNBAR);
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) {
|
||||
puts("i2c pmic ECC_DE register read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_BITS_ECC_DE1) {
|
||||
puts(WARNBAR);
|
||||
puts("ERROR: banks 1 to 5 have uncorrectable bits\n");
|
||||
puts(WARNBAR);
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) {
|
||||
puts("i2c pmic ECC_DE register read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_BITS_ECC_DE2) {
|
||||
puts(WARNBAR);
|
||||
puts("ERROR: banks 6 to 10 have uncorrectable bits\n");
|
||||
puts(WARNBAR);
|
||||
}
|
||||
|
||||
/* get device ident */
|
||||
if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) {
|
||||
puts("i2c pmic devid read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) {
|
||||
puts("i2c pmic revid read failed\n");
|
||||
return 0;
|
||||
}
|
||||
printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid);
|
||||
|
||||
/* get device programmed state */
|
||||
val = PFUZE100_PAGE_REGISTER_PAGE1;
|
||||
if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
|
||||
puts("i2c write failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) {
|
||||
puts("i2c fuse_por read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_FUSE_POR_M)
|
||||
programmed++;
|
||||
|
||||
if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) {
|
||||
puts("i2c fuse_por read failed\n");
|
||||
return programmed;
|
||||
}
|
||||
if (val & PFUZE100_FUSE_POR_M)
|
||||
programmed++;
|
||||
|
||||
if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) {
|
||||
puts("i2c fuse_por read failed\n");
|
||||
return programmed;
|
||||
}
|
||||
if (val & PFUZE100_FUSE_POR_M)
|
||||
programmed++;
|
||||
|
||||
switch (programmed) {
|
||||
case 0:
|
||||
puts("not programmed\n");
|
||||
break;
|
||||
case 3:
|
||||
puts("programmed\n");
|
||||
break;
|
||||
default:
|
||||
puts("undefined programming state\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* The following is needed during production */
|
||||
if (programmed != 3) {
|
||||
/* set VGEN1 to 1.2V */
|
||||
val = PFUZE100_VGEN1_VAL;
|
||||
if (dm_i2c_write(dev, PFUZE100_VGEN1CTL, &val, 1)) {
|
||||
puts("i2c write failed\n");
|
||||
return programmed;
|
||||
}
|
||||
|
||||
/* set SWBST to 5.0V */
|
||||
val = PFUZE100_SWBST_VAL;
|
||||
if (dm_i2c_write(dev, PFUZE100_SWBSTCTL, &val, 1))
|
||||
puts("i2c write failed\n");
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
{
|
||||
unsigned int i, j;
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
printf("\t%x", i);
|
||||
for (j = 0; j < 0x80; ) {
|
||||
printf("\n%2x", j);
|
||||
for (i = 0; i < 16; i++) {
|
||||
dm_i2c_read(dev, j + i, &val, 1);
|
||||
printf("\t%2x", val);
|
||||
}
|
||||
j += 0x10;
|
||||
}
|
||||
printf("\nEXT Page 1");
|
||||
|
||||
val = PFUZE100_PAGE_REGISTER_PAGE1;
|
||||
if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
|
||||
puts("i2c write failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (j = 0x80; j < 0x100; ) {
|
||||
printf("\n%2x", j);
|
||||
for (i = 0; i < 16; i++) {
|
||||
dm_i2c_read(dev, j + i, &val, 1);
|
||||
printf("\t%2x", val);
|
||||
}
|
||||
j += 0x10;
|
||||
}
|
||||
printf("\nEXT Page 2");
|
||||
|
||||
val = PFUZE100_PAGE_REGISTER_PAGE2;
|
||||
if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
|
||||
puts("i2c write failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (j = 0x80; j < 0x100; ) {
|
||||
printf("\n%2x", j);
|
||||
for (i = 0; i < 16; i++) {
|
||||
dm_i2c_read(dev, j + i, &val, 1);
|
||||
printf("\t%2x", val);
|
||||
}
|
||||
j += 0x10;
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
#endif /* DEBUG */
|
||||
|
||||
return programmed;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
static int pf0100_prog(void)
|
||||
{
|
||||
int rc;
|
||||
struct udevice *dev = NULL;
|
||||
unsigned char bus = 1;
|
||||
unsigned char val;
|
||||
unsigned int i;
|
||||
|
||||
if (pmic_init() == 3) {
|
||||
puts("PMIC already programmed, exiting\n");
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
/* set up gpio to manipulate vprog, initially off */
|
||||
imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
|
||||
ARRAY_SIZE(pmic_prog_pads));
|
||||
gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
|
||||
|
||||
rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
|
||||
if (rc) {
|
||||
printf("failed to get device for PMIC at address 0x%x\n",
|
||||
PFUZE100_I2C_ADDR);
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
|
||||
switch (pmic_otp_prog[i].cmd) {
|
||||
case pmic_i2c:
|
||||
val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
|
||||
if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) {
|
||||
printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
|
||||
pmic_otp_prog[i].reg, val);
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
break;
|
||||
case pmic_delay:
|
||||
udelay(pmic_otp_prog[i].value * 1000);
|
||||
break;
|
||||
case pmic_vpgm:
|
||||
gpio_direction_output(PMIC_PROG_VOLTAGE,
|
||||
pmic_otp_prog[i].value);
|
||||
break;
|
||||
case pmic_pwr:
|
||||
/* TODO */
|
||||
break;
|
||||
}
|
||||
}
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
int ret;
|
||||
puts("Programming PMIC OTP...");
|
||||
ret = pf0100_prog();
|
||||
if (ret == CMD_RET_SUCCESS)
|
||||
puts("done.\n");
|
||||
else
|
||||
puts("failed.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
pf0100_otp_prog, 1, 0, do_pf0100_prog,
|
||||
"Program the OTP fuses on the PMIC PF0100",
|
||||
""
|
||||
);
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
@@ -0,0 +1,107 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2014-2019, Toradex AG
|
||||
*/
|
||||
|
||||
/*
|
||||
* Helpers for Freescale PMIC PF0100
|
||||
*/
|
||||
|
||||
#ifndef PF0100_H_
|
||||
#define PF0100_H_
|
||||
|
||||
/* bit definitions */
|
||||
#define PFUZE100_BIT_0 (0x01 << 0)
|
||||
#define PFUZE100_BIT_1 (0x01 << 1)
|
||||
#define PFUZE100_BIT_2 (0x01 << 2)
|
||||
#define PFUZE100_BIT_3 (0x01 << 3)
|
||||
#define PFUZE100_BIT_4 (0x01 << 4)
|
||||
#define PFUZE100_BIT_5 (0x01 << 5)
|
||||
#define PFUZE100_BIT_6 (0x01 << 6)
|
||||
#define PFUZE100_BIT_7 (0x01 << 7)
|
||||
|
||||
/* 7-bit I2C bus slave address */
|
||||
#define PFUZE100_I2C_ADDR (0x08)
|
||||
/* Register Addresses */
|
||||
#define PFUZE100_DEVICEID (0x0)
|
||||
#define PFUZE100_REVID (0x3)
|
||||
#define PFUZE100_INTSTAT3 (0xe)
|
||||
#define PFUZE100_BIT_OTP_ECCI PFUZE100_BIT_7
|
||||
#define PFUZE100_SW1AMODE (0x23)
|
||||
#define PFUZE100_SW1ACON 36
|
||||
#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */
|
||||
#define PFUZE100_SW1ACON_SPEED_M (0x3<<6)
|
||||
#define PFUZE100_SW1CCON 49
|
||||
#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */
|
||||
#define PFUZE100_SW1CCON_SPEED_M (0x3<<6)
|
||||
#define PFUZE100_SW1AVOL 32
|
||||
#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0)
|
||||
#define PFUZE100_SW1CVOL 46
|
||||
#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0)
|
||||
#define PFUZE100_VGEN1CTL (0x6c)
|
||||
#define PFUZE100_VGEN1_VAL (0x30 + 0x08) /* Always ON, 1.2V */
|
||||
#define PFUZE100_SWBSTCTL (0x66)
|
||||
/* Always ON, Auto Switching Mode, 5.0V */
|
||||
#define PFUZE100_SWBST_VAL (0x40 + 0x08 + 0x00)
|
||||
|
||||
/* chooses the extended page (registers 0x80..0xff) */
|
||||
#define PFUZE100_PAGE_REGISTER 0x7f
|
||||
#define PFUZE100_PAGE_REGISTER_PAGE_M (0x1f << 0)
|
||||
#define PFUZE100_PAGE_REGISTER_PAGE1 (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
|
||||
#define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
|
||||
|
||||
/* extended page 1 */
|
||||
#define PFUZE100_OTP_ECC_SE1 0x8a
|
||||
#define PFUZE100_BIT_ECC1_SE PFUZE100_BIT_0
|
||||
#define PFUZE100_BIT_ECC2_SE PFUZE100_BIT_1
|
||||
#define PFUZE100_BIT_ECC3_SE PFUZE100_BIT_2
|
||||
#define PFUZE100_BIT_ECC4_SE PFUZE100_BIT_3
|
||||
#define PFUZE100_BIT_ECC5_SE PFUZE100_BIT_4
|
||||
#define PFUZE100_BITS_ECC_SE1 ((PFUZE100_BIT_ECC1_SE) | \
|
||||
(PFUZE100_BIT_ECC2_SE) | \
|
||||
(PFUZE100_BIT_ECC3_SE) | \
|
||||
(PFUZE100_BIT_ECC4_SE) | \
|
||||
(PFUZE100_BIT_ECC5_SE))
|
||||
#define PFUZE100_OTP_ECC_SE2 0x8b
|
||||
#define PFUZE100_BIT_ECC6_SE PFUZE100_BIT_0
|
||||
#define PFUZE100_BIT_ECC7_SE PFUZE100_BIT_1
|
||||
#define PFUZE100_BIT_ECC8_SE PFUZE100_BIT_2
|
||||
#define PFUZE100_BIT_ECC9_SE PFUZE100_BIT_3
|
||||
#define PFUZE100_BIT_ECC10_SE PFUZE100_BIT_4
|
||||
#define PFUZE100_BITS_ECC_SE2 ((PFUZE100_BIT_ECC6_SE) | \
|
||||
(PFUZE100_BIT_ECC7_SE) | \
|
||||
(PFUZE100_BIT_ECC8_SE) | \
|
||||
(PFUZE100_BIT_ECC9_SE) | \
|
||||
(PFUZE100_BIT_ECC10_SE))
|
||||
#define PFUZE100_OTP_ECC_DE1 0x8c
|
||||
#define PFUZE100_BIT_ECC1_DE PFUZE100_BIT_0
|
||||
#define PFUZE100_BIT_ECC2_DE PFUZE100_BIT_1
|
||||
#define PFUZE100_BIT_ECC3_DE PFUZE100_BIT_2
|
||||
#define PFUZE100_BIT_ECC4_DE PFUZE100_BIT_3
|
||||
#define PFUZE100_BIT_ECC5_DE PFUZE100_BIT_4
|
||||
#define PFUZE100_BITS_ECC_DE1 ((PFUZE100_BIT_ECC1_DE) | \
|
||||
(PFUZE100_BIT_ECC2_DE) | \
|
||||
(PFUZE100_BIT_ECC3_DE) | \
|
||||
(PFUZE100_BIT_ECC4_DE) | \
|
||||
(PFUZE100_BIT_ECC5_DE))
|
||||
#define PFUZE100_OTP_ECC_DE2 0x8d
|
||||
#define PFUZE100_BIT_ECC6_DE PFUZE100_BIT_0
|
||||
#define PFUZE100_BIT_ECC7_DE PFUZE100_BIT_1
|
||||
#define PFUZE100_BIT_ECC8_DE PFUZE100_BIT_2
|
||||
#define PFUZE100_BIT_ECC9_DE PFUZE100_BIT_3
|
||||
#define PFUZE100_BIT_ECC10_DE PFUZE100_BIT_4
|
||||
#define PFUZE100_BITS_ECC_DE2 ((PFUZE100_BIT_ECC6_DE) | \
|
||||
(PFUZE100_BIT_ECC7_DE) | \
|
||||
(PFUZE100_BIT_ECC8_DE) | \
|
||||
(PFUZE100_BIT_ECC9_DE) | \
|
||||
(PFUZE100_BIT_ECC10_DE))
|
||||
#define PFUZE100_FUSE_POR1 0xe4
|
||||
#define PFUZE100_FUSE_POR2 0xe5
|
||||
#define PFUZE100_FUSE_POR3 0xe6
|
||||
#define PFUZE100_FUSE_POR_M (0x1 << 1)
|
||||
|
||||
/* output some informational messages, return the number FUSE_POR=1 */
|
||||
/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
|
||||
unsigned pmic_init(void);
|
||||
|
||||
#endif /* PF0100_H_ */
|
||||
@@ -0,0 +1,190 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2014-2016, Toradex AG
|
||||
*/
|
||||
|
||||
// Register Output for PF0100 programmer
|
||||
// Customer: Toradex AG
|
||||
// Program: Apalis iMX6
|
||||
// Sample marking:
|
||||
// Date: 12.02.2014
|
||||
// Time: 17:16:41
|
||||
// Generated from Spreadsheet Revision: P1.8
|
||||
|
||||
/* sed commands to get from programmer script to struct */
|
||||
/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc
|
||||
sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
|
||||
sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
|
||||
|
||||
enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
|
||||
struct pmic_otp_prog_t{
|
||||
unsigned char cmd;
|
||||
unsigned char reg;
|
||||
unsigned short value;
|
||||
};
|
||||
|
||||
struct pmic_otp_prog_t pmic_otp_prog[] = {
|
||||
{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
|
||||
{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
|
||||
{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
|
||||
{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
|
||||
{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
|
||||
{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
|
||||
{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
|
||||
{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
|
||||
{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
|
||||
{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
|
||||
{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
|
||||
{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
|
||||
{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
|
||||
{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
|
||||
{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
|
||||
{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
|
||||
{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
|
||||
{pmic_i2c, 0xBD, 0x1F}, // Auto gen from Row123
|
||||
{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
|
||||
{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
|
||||
{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
|
||||
{pmic_i2c, 0xC9, 0x08}, // Auto gen from Row135
|
||||
{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
|
||||
{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
|
||||
{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
|
||||
{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
|
||||
{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
|
||||
{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
|
||||
{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
|
||||
{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
|
||||
{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
|
||||
{pmic_i2c, 0xE0, 0x07}, // Auto gen from Row158
|
||||
|
||||
#if 0 /* TBB mode */
|
||||
{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
|
||||
{pmic_delay, 0, 10},
|
||||
#else
|
||||
// Write OTP
|
||||
{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
|
||||
{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
|
||||
{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
|
||||
{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
|
||||
{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
|
||||
{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
|
||||
{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
|
||||
{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
|
||||
//VPGM:DOWN:n
|
||||
//VPGM:UP:n
|
||||
{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
|
||||
//-----------------------------------------------------------------------------------
|
||||
// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 1
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 2
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 3
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 4
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 5
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 6
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 7
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 8
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 9
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 10
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
|
||||
{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
|
||||
{pmic_i2c, 0xD0, 0x00}, // Clear
|
||||
{pmic_i2c, 0xD1, 0x00}, // Clear
|
||||
{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
|
||||
{pmic_delay, 0, 500},
|
||||
{pmic_pwr, 0, 1},
|
||||
#endif
|
||||
};
|
||||
@@ -0,0 +1,39 @@
|
||||
if TARGET_APALIS_T30
|
||||
|
||||
config SYS_BOARD
|
||||
default "apalis_t30"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "apalis_t30"
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_HAVE_MMC
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_DEV
|
||||
default "0"
|
||||
|
||||
config TDX_CFG_BLOCK_PART
|
||||
default "1"
|
||||
|
||||
# Toradex config block in eMMC, at the end of 1st "boot sector"
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "-512"
|
||||
|
||||
config APALIS_T30_PCIE_EVALBOARD_INIT
|
||||
bool "Apalis Evaluation Board PCIe Initialisation"
|
||||
help
|
||||
Bring up the Apalis type specific 4 lane PCIe port as well as the
|
||||
Apalis PCIe port with the PCIe switch as found on the Apalis
|
||||
Evaluation board. Note that by default both those ports are also left
|
||||
disabled in the device tree which needs changing as well for this to
|
||||
actually work.
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,7 @@
|
||||
Apalis T30
|
||||
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
||||
S: Maintained
|
||||
F: board/toradex/apalis_t30/
|
||||
F: include/configs/apalis_t30.h
|
||||
F: configs/apalis_t30_defconfig
|
||||
F: arch/arm/dts/tegra30-apalis.dtb
|
||||
@@ -0,0 +1,4 @@
|
||||
# Copyright (c) 2014 Marcel Ziswiler
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-y += apalis_t30.o
|
||||
@@ -0,0 +1,175 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2014-2018
|
||||
* Marcel Ziswiler <marcel@ziswiler.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/gp_padctrl.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch-tegra/ap.h>
|
||||
#include <asm/arch-tegra/tegra.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm.h>
|
||||
#include <i2c.h>
|
||||
#include <pci_tegra.h>
|
||||
#include "../common/tdx-common.h"
|
||||
|
||||
#include "pinmux-config-apalis_t30.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define PMU_I2C_ADDRESS 0x2D
|
||||
#define MAX_I2C_RETRY 3
|
||||
|
||||
#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
|
||||
#define PEX_PERST_N TEGRA_GPIO(S, 7) /* Apalis GPIO7 */
|
||||
#define RESET_MOCI_CTRL TEGRA_GPIO(I, 4)
|
||||
|
||||
static int pci_reset_status;
|
||||
#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
|
||||
NVBOOTTYPE_RECOVERY)
|
||||
printf("USB recovery mode\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("Model: Toradex Apalis T30 %dGB\n",
|
||||
(gd->ram_size == 0x40000000) ? 1 : 2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
return ft_common_board_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_config_pingrp_table(tegra3_pinmux_common,
|
||||
ARRAY_SIZE(tegra3_pinmux_common));
|
||||
|
||||
pinmux_config_pingrp_table(unused_pins_lowpower,
|
||||
ARRAY_SIZE(unused_pins_lowpower));
|
||||
|
||||
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
|
||||
pinmux_config_drvgrp_table(apalis_t30_padctrl,
|
||||
ARRAY_SIZE(apalis_t30_padctrl));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI_TEGRA
|
||||
int tegra_pcie_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
u8 addr, data[1];
|
||||
int err;
|
||||
|
||||
err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
|
||||
if (err) {
|
||||
debug("%s: Cannot find PMIC I2C chip\n", __func__);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* TPS659110: VDD2_OP_REG = 1.05V */
|
||||
data[0] = 0x27;
|
||||
addr = 0x25;
|
||||
|
||||
err = dm_i2c_write(dev, addr, data, 1);
|
||||
if (err) {
|
||||
debug("failed to set VDD supply\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/* TPS659110: VDD2_REG 7.5 mV/us, ACTIVE */
|
||||
data[0] = 0x0D;
|
||||
addr = 0x24;
|
||||
|
||||
err = dm_i2c_write(dev, addr, data, 1);
|
||||
if (err) {
|
||||
debug("failed to enable VDD supply\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/* TPS659110: LDO6_REG = 1.1V, ACTIVE */
|
||||
data[0] = 0x0D;
|
||||
addr = 0x35;
|
||||
|
||||
err = dm_i2c_write(dev, addr, data, 1);
|
||||
if (err) {
|
||||
debug("failed to set AVDD supply\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
|
||||
gpio_request(PEX_PERST_N, "PEX_PERST_N");
|
||||
gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
|
||||
#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
|
||||
{
|
||||
int index = tegra_pcie_port_index_of_port(port);
|
||||
|
||||
if (index == 2) { /* I210 Gigabit Ethernet Controller (On-module) */
|
||||
tegra_pcie_port_reset(port);
|
||||
}
|
||||
#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
|
||||
/*
|
||||
* Apalis PCIe aka port 1 and Apalis Type Specific 4 Lane PCIe aka port
|
||||
* 0 share the same RESET_MOCI therefore only assert it once for both
|
||||
* ports to avoid losing the previously brought up port again.
|
||||
*/
|
||||
else if ((index == 1) || (index == 0)) {
|
||||
/* only do it once per init cycle */
|
||||
if (pci_reset_status % 2 == 0) {
|
||||
/*
|
||||
* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on
|
||||
* Apalis Evaluation Board
|
||||
*/
|
||||
gpio_direction_output(PEX_PERST_N, 0);
|
||||
gpio_direction_output(RESET_MOCI_CTRL, 0);
|
||||
|
||||
/*
|
||||
* Must be asserted for 100 ms after power and clocks
|
||||
* are stable
|
||||
*/
|
||||
mdelay(100);
|
||||
|
||||
gpio_set_value(PEX_PERST_N, 1);
|
||||
/*
|
||||
* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not
|
||||
* Guaranteed Until 900 us After PEX_PERST# De-assertion
|
||||
*/
|
||||
mdelay(1);
|
||||
gpio_set_value(RESET_MOCI_CTRL, 1);
|
||||
}
|
||||
pci_reset_status++;
|
||||
}
|
||||
#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
|
||||
}
|
||||
#endif /* CONFIG_PCI_TEGRA */
|
||||
|
||||
/*
|
||||
* Backlight off before OS handover
|
||||
*/
|
||||
void board_preboot_os(void)
|
||||
{
|
||||
gpio_request(TEGRA_GPIO(V, 2), "BKL1_ON");
|
||||
gpio_direction_output(TEGRA_GPIO(V, 2), 0);
|
||||
}
|
||||
@@ -0,0 +1,338 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2014, Marcel Ziswiler
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_APALIS_T30_H_
|
||||
#define _PINMUX_CONFIG_APALIS_T30_H_
|
||||
|
||||
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
|
||||
}
|
||||
|
||||
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static struct pmux_pingrp_config tegra3_pinmux_common[] = {
|
||||
/* SDMMC1 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC3 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC4 pinmux (eMMC) */
|
||||
LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* I2C1 pinmux */
|
||||
I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* I2C2 pinmux */
|
||||
I2C_PINMUX(GEN2_I2C_SCL_PT5, RSVD3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SDA_PT6, RSVD3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
|
||||
|
||||
/* I2C3 pinmux */
|
||||
I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* I2C4 pinmux */
|
||||
I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* Power I2C pinmux */
|
||||
I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
/* UARTA RX, make sure we don't get input form a floating Pin */
|
||||
DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
LV_PINMUX(VI_D0_PT4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D1_PD5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D10_PT2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D11_PT3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(PU1, RSVD1, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(PU2, RSVD1, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(PU3, PWM0, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU6, PWM3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(GMI_AD10_PH2, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(GMI_A17_PB0, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(GMI_A19_PK7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
|
||||
DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* multiplexed VI_D2, VI_D3, VI_D4, VI_D5, VI_D6, VI_D7, VI_D8 and VI_D9
|
||||
*/
|
||||
DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* GPIOs */
|
||||
DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL2_PQ2, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT),
|
||||
/* multiplexed KB_COL0 */
|
||||
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, TRISTATE, OUTPUT),
|
||||
|
||||
DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, RSVD2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
|
||||
DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(GMI_AD12_PH4, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
DEFAULT_PINMUX(GMI_AD14_PH6, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
|
||||
|
||||
DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, INPUT),
|
||||
};
|
||||
|
||||
static struct pmux_pingrp_config unused_pins_lowpower[] = {
|
||||
DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK_PK1, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD0_PG0, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1_PG1, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2_PG2, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3_PG3, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD4_PG4, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD5_PG5, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6_PG6, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7_PG7, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11_PH3, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13_PH5, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS_PI2, NAND, DOWN, TRISTATE, OUTPUT),
|
||||
};
|
||||
|
||||
static struct pmux_drvgrp_config apalis_t30_padctrl[] = {
|
||||
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
|
||||
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
|
||||
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
|
||||
};
|
||||
#endif /* _PINMUX_CONFIG_APALIS_T30_H_ */
|
||||
@@ -0,0 +1,29 @@
|
||||
if TARGET_COLIBRI_IMX6ULL
|
||||
|
||||
config SYS_BOARD
|
||||
default "colibri-imx6ull"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "colibri-imx6ull"
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_HAVE_NAND
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "2048"
|
||||
|
||||
config TDX_CFG_BLOCK_OFFSET2
|
||||
default "133120"
|
||||
|
||||
config TDX_CFG_BLOCK_2ND_ETHADDR
|
||||
default y
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,11 @@
|
||||
Colibri iMX6ULL
|
||||
M: Stefan Agner <stefan.agner@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
W: https://www.toradex.com/community
|
||||
S: Maintained
|
||||
F: arch/arm/dts/imx6ull-colibri.dts
|
||||
F: arch/arm/dts/imx6ull-colibri-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6ull-colibri.dtsi
|
||||
F: board/toradex/colibri-imx6ull/
|
||||
F: configs/colibri-imx6ull_defconfig
|
||||
F: include/configs/colibri-imx6ull.h
|
||||
@@ -0,0 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
# Copyright (C) 2018 Toradex AG
|
||||
|
||||
obj-y := colibri-imx6ull.o
|
||||
@@ -0,0 +1,241 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018-2019 Toradex AG
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch-mx6/clock.h>
|
||||
#include <asm/arch-mx6/imx-regs.h>
|
||||
#include <asm/arch-mx6/mx6ull_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm.h>
|
||||
#include <dm/platform_data/serial_mxc.h>
|
||||
#include <env.h>
|
||||
#include <fdt_support.h>
|
||||
#include <imx_thermal.h>
|
||||
#include <jffs2/load_kernel.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <miiphy.h>
|
||||
#include <mtd_node.h>
|
||||
#include <netdev.h>
|
||||
|
||||
#include "../common/tdx-common.h"
|
||||
#include "../common/tdx-cfg-block.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_DSE_48ohm)
|
||||
|
||||
#define MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR 0x2290040
|
||||
|
||||
#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
|
||||
|
||||
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
static void setup_gpmi_nand(void)
|
||||
{
|
||||
setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
|
||||
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
|
||||
}
|
||||
#endif /* CONFIG_NAND_MXS */
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
static iomux_v3_cfg_t const lcd_pads[] = {
|
||||
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const backlight_pads[] = {
|
||||
/* Backlight On */
|
||||
MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* Backlight PWM<A> (multiplexed pin) */
|
||||
MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define GPIO_BL_ON IMX_GPIO_NR(1, 11)
|
||||
#define GPIO_PWM_A IMX_GPIO_NR(4, 11)
|
||||
|
||||
static int setup_lcd(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
|
||||
|
||||
/* Set BL_ON */
|
||||
gpio_request(GPIO_BL_ON, "BL_ON");
|
||||
gpio_direction_output(GPIO_BL_ON, 1);
|
||||
|
||||
/* Set PWM<A> to full brightness (assuming inversed polarity) */
|
||||
gpio_request(GPIO_PWM_A, "PWM<A>");
|
||||
gpio_direction_output(GPIO_PWM_A, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
int ret;
|
||||
|
||||
/* provide the PHY clock from the i.MX 6 */
|
||||
ret = enable_fec_anatop_clock(1, ENET_50MHZ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */
|
||||
clrsetbits_le32(&iomuxc_regs->gpr[1],
|
||||
IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
|
||||
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
|
||||
|
||||
/* give new Ethernet PHY power save mode circuitry time to settle */
|
||||
mdelay(300);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_FEC_MXC */
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
setup_gpmi_nand();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
setup_lcd();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
/* TODO */
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
|
||||
{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_TDX_CFG_BLOCK
|
||||
/*
|
||||
* If we have a valid config block and it says we are a module with
|
||||
* Wi-Fi/Bluetooth make sure we use the -wifi device tree.
|
||||
*/
|
||||
if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT ||
|
||||
tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT)
|
||||
env_set("variant", "-wifi");
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the
|
||||
* SOC to request for a lower voltage during sleep. This is necessary
|
||||
* because the voltage is changing too slow for the SOC to wake up
|
||||
* properly.
|
||||
*/
|
||||
__raw_writel(0x8080, MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR);
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_USB_SDP
|
||||
if (is_boot_from_usb()) {
|
||||
printf("Serial Downloader recovery mode, using sdp command\n");
|
||||
env_set("bootdelay", "0");
|
||||
env_set("bootcmd", "sdp 0");
|
||||
}
|
||||
#endif /* CONFIG_CMD_USB_SDP */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("Model: Toradex Colibri iMX6ULL\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
|
||||
static struct node_info nodes[] = {
|
||||
{ "fsl,imx6ull-gpmi-nand", MTD_DEV_TYPE_NAND, },
|
||||
{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
|
||||
};
|
||||
|
||||
/* Update partition nodes using info from mtdparts env var */
|
||||
puts(" Updating MTD partitions...\n");
|
||||
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
|
||||
#endif
|
||||
|
||||
return ft_common_board_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct mxc_serial_platdata mxc_serial_plat = {
|
||||
.reg = (struct mxc_uart *)UART1_BASE,
|
||||
.use_dte = 1,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(mxc_serial) = {
|
||||
.name = "serial_mxc",
|
||||
.platdata = &mxc_serial_plat,
|
||||
};
|
||||
@@ -0,0 +1,106 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2018 Toradex AG
|
||||
*
|
||||
* Refer doc/README.imximage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : nand
|
||||
*/
|
||||
|
||||
BOOT_FROM nand
|
||||
|
||||
/*
|
||||
* Secure boot support
|
||||
*/
|
||||
#ifdef CONFIG_IMX_HAB
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
/* Enable all clocks */
|
||||
DATA 4 0x020c4068 0xffffffff
|
||||
DATA 4 0x020c406c 0xffffffff
|
||||
DATA 4 0x020c4070 0xffffffff
|
||||
DATA 4 0x020c4074 0xffffffff
|
||||
DATA 4 0x020c4078 0xffffffff
|
||||
DATA 4 0x020c407c 0xffffffff
|
||||
DATA 4 0x020c4080 0xffffffff
|
||||
|
||||
DATA 4 0x020E04B4 0x000C0000
|
||||
DATA 4 0x020E04AC 0x00000000
|
||||
DATA 4 0x020E027C 0x00000030
|
||||
DATA 4 0x020E0250 0x00000030
|
||||
DATA 4 0x020E024C 0x00000030
|
||||
DATA 4 0x020E0490 0x00000030
|
||||
DATA 4 0x020E0288 0x000C0030
|
||||
DATA 4 0x020E0270 0x00000000
|
||||
DATA 4 0x020E0260 0x00000030
|
||||
DATA 4 0x020E0264 0x00000030
|
||||
DATA 4 0x020E04A0 0x00000030
|
||||
DATA 4 0x020E0494 0x00020000
|
||||
DATA 4 0x020E0280 0x00000030
|
||||
DATA 4 0x020E0284 0x00000030
|
||||
DATA 4 0x020E04B0 0x00020000
|
||||
DATA 4 0x020E0498 0x00000030
|
||||
DATA 4 0x020E04A4 0x00000030
|
||||
DATA 4 0x020E0244 0x00000030
|
||||
DATA 4 0x020E0248 0x00000030
|
||||
DATA 4 0x021B001C 0x00008000
|
||||
DATA 4 0x021B0800 0xA1390003
|
||||
DATA 4 0x021B080C 0x00000004
|
||||
DATA 4 0x021B083C 0x41640158
|
||||
DATA 4 0x021B0848 0x40403237
|
||||
DATA 4 0x021B0850 0x40403C33
|
||||
DATA 4 0x021B081C 0x33333333
|
||||
DATA 4 0x021B0820 0x33333333
|
||||
DATA 4 0x021B082C 0xf3333333
|
||||
DATA 4 0x021B0830 0xf3333333
|
||||
DATA 4 0x021B08C0 0x00944009
|
||||
DATA 4 0x021B08b8 0x00000800
|
||||
DATA 4 0x021B0004 0x0002002D
|
||||
DATA 4 0x021B0008 0x1B333030
|
||||
DATA 4 0x021B000C 0x676B52F3
|
||||
DATA 4 0x021B0010 0xB66D0B63
|
||||
DATA 4 0x021B0014 0x01FF00DB
|
||||
DATA 4 0x021B0018 0x00201740
|
||||
DATA 4 0x021B001C 0x00008000
|
||||
DATA 4 0x021B002C 0x000026D2
|
||||
DATA 4 0x021B0030 0x006B1023
|
||||
DATA 4 0x021B0040 0x0000004F
|
||||
DATA 4 0x021B0000 0x84180000
|
||||
DATA 4 0x021B0890 0x00400000
|
||||
DATA 4 0x021B001C 0x02008032
|
||||
DATA 4 0x021B001C 0x00008033
|
||||
DATA 4 0x021B001C 0x00048031
|
||||
DATA 4 0x021B001C 0x15208030
|
||||
DATA 4 0x021B001C 0x04008040
|
||||
DATA 4 0x021B0020 0x00000800
|
||||
DATA 4 0x021B0818 0x00000227
|
||||
DATA 4 0x021B0004 0x0002552D
|
||||
DATA 4 0x021B0404 0x00011006
|
||||
DATA 4 0x021B001C 0x00000000
|
||||
|
||||
@@ -0,0 +1,30 @@
|
||||
if TARGET_COLIBRI_IMX8X
|
||||
|
||||
config SYS_BOARD
|
||||
default "colibri-imx8x"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "colibri-imx8x"
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_HAVE_MMC
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_DEV
|
||||
default "0"
|
||||
|
||||
config TDX_CFG_BLOCK_PART
|
||||
default "1"
|
||||
|
||||
# Toradex config block in eMMC, at the end of 1st "boot sector"
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "-512"
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,9 @@
|
||||
Colibri iMX8X
|
||||
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
S: Maintained
|
||||
F: arch/arm/dts/fsl-imx8x-colibri.dts
|
||||
F: arch/arm/dts/fsl-imx8x-colibri-u-boot.dtsi
|
||||
F: board/toradex/colibri-imx8x/
|
||||
F: configs/colibri-imx8qxp_defconfig
|
||||
F: include/configs/colibri-imx8x.h
|
||||
@@ -0,0 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright 2019 Toradex
|
||||
#
|
||||
|
||||
obj-y += colibri-imx8x.o
|
||||
@@ -0,0 +1,66 @@
|
||||
U-Boot for the Toradex Colibri iMX8QXP V1.0B Module
|
||||
|
||||
Quick Start
|
||||
===========
|
||||
|
||||
- Build the ARM trusted firmware binary
|
||||
- Get scfw_tcm.bin and ahab-container.img
|
||||
- Build U-Boot
|
||||
- Load U-Boot binary using uuu
|
||||
- Flash U-Boot binary into the eMMC
|
||||
- Boot
|
||||
|
||||
Get and Build the ARM Trusted Firmware
|
||||
======================================
|
||||
|
||||
$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
|
||||
$ cd imx-atf/
|
||||
$ make PLAT=imx8qxp bl31
|
||||
|
||||
Get scfw_tcm.bin and ahab-container.img
|
||||
=======================================
|
||||
|
||||
$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
|
||||
$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-tcm.bin
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
|
||||
$ chmod +x firmware-imx-8.0.bin
|
||||
$ ./firmware-imx-8.0.bin
|
||||
|
||||
Copy the following binaries to the U-Boot folder:
|
||||
|
||||
$ cp imx-atf/build/imx8qxp/release/bl31.bin .
|
||||
$ cp u-boot/u-boot.bin .
|
||||
|
||||
Copy the following firmware to the U-Boot folder:
|
||||
|
||||
$ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
|
||||
|
||||
Build U-Boot
|
||||
============
|
||||
|
||||
$ make colibri-imx8qxp_defconfig
|
||||
$ make u-boot-dtb.imx
|
||||
|
||||
Load the U-Boot Binary Using UUU
|
||||
================================
|
||||
|
||||
Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
|
||||
|
||||
https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
|
||||
|
||||
Put the module into USB recovery aka serial downloader mode, connect USB device
|
||||
to your host and execute uuu:
|
||||
|
||||
sudo ./uuu u-boot/u-boot-dtb.imx
|
||||
|
||||
Flash the U-Boot Binary into the eMMC
|
||||
=====================================
|
||||
|
||||
Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
|
||||
|
||||
load mmc 1:1 $loadaddr u-boot-dtb.imx
|
||||
setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
|
||||
mmc dev 0 1
|
||||
mmc write ${loadaddr} 0x0 ${blkcnt}
|
||||
|
||||
Boot
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 Toradex
|
||||
*
|
||||
* Refer doc/README.imx8image for more details about how-to configure
|
||||
* and create imx8image boot image
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
|
||||
/* Boot from SD, sector size 0x400 */
|
||||
BOOT_FROM EMMC_FASTBOOT 0x400
|
||||
/* SoC type IMX8QX */
|
||||
SOC_TYPE IMX8QX
|
||||
/* Append seco container image */
|
||||
APPEND mx8qx-ahab-container.img
|
||||
/* Create the 2nd container */
|
||||
CONTAINER
|
||||
/* Add scfw image with exec attribute */
|
||||
IMAGE SCU mx8qx-colibri-scfw-tcm.bin
|
||||
/* Add ATF image with exec attribute */
|
||||
IMAGE A35 bl31.bin 0x80000000
|
||||
/* Add U-Boot image with load attribute */
|
||||
DATA A35 u-boot-dtb.bin 0x80020000
|
||||
@@ -0,0 +1,138 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2019 Toradex
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx8-pins.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/sci/sci.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <env.h>
|
||||
#include <errno.h>
|
||||
#include <linux/libfdt.h>
|
||||
|
||||
#include "../common/tdx-cfg-block.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
static iomux_cfg_t uart3_pads[] = {
|
||||
SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
/* Transceiver FORCEOFF# signal, mux to use pull-up */
|
||||
SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
sc_pm_clock_rate_t rate;
|
||||
sc_err_t err = 0;
|
||||
|
||||
/*
|
||||
* This works around that having only UART3 up the baudrate is 1.2M
|
||||
* instead of 115.2k. Set UART0 clock root to 80 MHz
|
||||
*/
|
||||
rate = 80000000;
|
||||
err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
|
||||
if (err != SC_ERR_NONE)
|
||||
return 0;
|
||||
|
||||
/* Set UART3 clock root to 80 MHz and enable it */
|
||||
rate = SC_80MHZ;
|
||||
err = sc_pm_setup_uart(SC_R_UART_3, rate);
|
||||
if (err != SC_ERR_NONE)
|
||||
return 0;
|
||||
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_DM_GPIO)
|
||||
static void board_gpio_init(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
#else
|
||||
static inline void board_gpio_init(void) {}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_FEC_MXC)
|
||||
#include <miiphy.h>
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Model: Toradex Colibri iMX8X\n");
|
||||
|
||||
build_info();
|
||||
print_bootinfo();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
board_gpio_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void detail_board_ddr_info(void)
|
||||
{
|
||||
puts("\nDDR ");
|
||||
}
|
||||
|
||||
/*
|
||||
* Board specific reset that is system reset.
|
||||
*/
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
return ft_common_board_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
/* TODO move to common */
|
||||
env_set("board_name", "Colibri iMX8QXP");
|
||||
env_set("board_rev", "v1.0");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
if TARGET_COLIBRI_IMX6
|
||||
|
||||
config SYS_BOARD
|
||||
default "colibri_imx6"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "colibri_imx6"
|
||||
|
||||
config SYS_CPU
|
||||
default "armv7"
|
||||
|
||||
config SYS_SOC
|
||||
default "mx6"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_HAVE_MMC
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_DEV
|
||||
default "0"
|
||||
|
||||
config TDX_CFG_BLOCK_PART
|
||||
default "1"
|
||||
|
||||
# Toradex config block in eMMC, at the end of 1st "boot sector"
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "-512"
|
||||
|
||||
config TDX_CMD_IMX_MFGR
|
||||
bool "Enable factory testing commands for Toradex iMX 6 modules"
|
||||
help
|
||||
This adds the commands
|
||||
pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
|
||||
If executed on already fused modules it doesn't change any fuse setting.
|
||||
default y
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,9 @@
|
||||
Colibri iMX6
|
||||
M: Max Krummenacher <max.krummenacher@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
W: https://www.toradex.com/community
|
||||
S: Maintained
|
||||
F: board/toradex/colibri_imx6/
|
||||
F: include/configs/colibri_imx6.h
|
||||
F: configs/colibri_imx6_defconfig
|
||||
F: arch/arm/dts/imx6-colibri.dts
|
||||
@@ -0,0 +1,5 @@
|
||||
# Copyright (c) 2012-2014 Toradex, Inc.
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-y := colibri_imx6.o do_fuse.o
|
||||
obj-$(CONFIG_TDX_CMD_IMX_MFGR) += pf0100.o
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,97 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2014-2016, Toradex AG
|
||||
*/
|
||||
|
||||
/*
|
||||
* Helpers for i.MX OTP fusing during module production
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#include <console.h>
|
||||
#include <fuse.h>
|
||||
|
||||
static int mfgr_fuse(void)
|
||||
{
|
||||
unsigned val, val6;
|
||||
|
||||
fuse_sense(0, 5, &val);
|
||||
printf("Fuse 0, 5: %8x\n", val);
|
||||
fuse_sense(0, 6, &val6);
|
||||
printf("Fuse 0, 6: %8x\n", val6);
|
||||
fuse_sense(4, 3, &val);
|
||||
printf("Fuse 4, 3: %8x\n", val);
|
||||
fuse_sense(4, 2, &val);
|
||||
printf("Fuse 4, 2: %8x\n", val);
|
||||
if (val6 & 0x10) {
|
||||
puts("BT_FUSE_SEL already fused, will do nothing\n");
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
/* boot cfg */
|
||||
fuse_prog(0, 5, 0x00005062);
|
||||
/* BT_FUSE_SEL */
|
||||
fuse_prog(0, 6, 0x00000010);
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
int ret;
|
||||
puts("Fusing...\n");
|
||||
ret = mfgr_fuse();
|
||||
if (ret == CMD_RET_SUCCESS)
|
||||
puts("done.\n");
|
||||
else
|
||||
puts("failed.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
unsigned val;
|
||||
int ret;
|
||||
int confirmed = argc >= 1 && !strcmp(argv[1], "-y");
|
||||
|
||||
/* can be used in scripts for command availability check */
|
||||
if (argc >= 1 && !strcmp(argv[1], "-n"))
|
||||
return CMD_RET_SUCCESS;
|
||||
|
||||
/* boot cfg */
|
||||
fuse_sense(0, 5, &val);
|
||||
printf("Fuse 0, 5: %8x\n", val);
|
||||
if (val & 0x10) {
|
||||
puts("Fast boot mode already fused, no need to fuse\n");
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
if (!confirmed) {
|
||||
puts("Warning: Programming fuses is an irreversible operation!\n"
|
||||
" Updating to fast boot mode prevents easy\n"
|
||||
" downgrading to previous BSP versions.\n"
|
||||
"\nReally perform this fuse programming? <y/N>\n");
|
||||
if (!confirm_yesno())
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
puts("Fusing fast boot mode...\n");
|
||||
ret = fuse_prog(0, 5, 0x00005072);
|
||||
if (ret == CMD_RET_SUCCESS)
|
||||
puts("done.\n");
|
||||
else
|
||||
puts("failed.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
mfgr_fuse, 1, 0, do_mfgr_fuse,
|
||||
"OTP fusing during module production",
|
||||
""
|
||||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
updt_fuse, 2, 0, do_updt_fuse,
|
||||
"OTP fusing during module update",
|
||||
"updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
|
||||
);
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
@@ -0,0 +1,267 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2014-2019, Toradex AG
|
||||
*/
|
||||
|
||||
/*
|
||||
* Helpers for Freescale PMIC PF0100
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
|
||||
#include "pf0100_otp.inc"
|
||||
#include "pf0100.h"
|
||||
|
||||
/* define for PMIC register dump */
|
||||
/*#define DEBUG */
|
||||
|
||||
#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n"
|
||||
|
||||
/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */
|
||||
static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
|
||||
MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3)
|
||||
};
|
||||
|
||||
unsigned pmic_init(void)
|
||||
{
|
||||
int rc;
|
||||
struct udevice *dev = NULL;
|
||||
unsigned programmed = 0;
|
||||
uchar bus = 1;
|
||||
uchar devid, revid, val;
|
||||
|
||||
puts("PMIC: ");
|
||||
rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
|
||||
if (rc) {
|
||||
printf("failed to get device for PMIC at address 0x%x\n",
|
||||
PFUZE100_I2C_ADDR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* check for errors in PMIC fuses */
|
||||
if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) {
|
||||
puts("i2c pmic INTSTAT3 register read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_BIT_OTP_ECCI) {
|
||||
puts("\n" WARNBAR);
|
||||
puts("WARNING: ecc errors found in pmic fuse banks\n");
|
||||
puts(WARNBAR);
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) {
|
||||
puts("i2c pmic ECC_SE1 register read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_BITS_ECC_SE1) {
|
||||
puts(WARNBAR);
|
||||
puts("WARNING: ecc has made bit corrections in banks 1 to 5\n");
|
||||
puts(WARNBAR);
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) {
|
||||
puts("i2c pmic ECC_SE2 register read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_BITS_ECC_SE2) {
|
||||
puts(WARNBAR);
|
||||
puts("WARNING: ecc has made bit corrections in banks 6 to 10\n"
|
||||
);
|
||||
puts(WARNBAR);
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) {
|
||||
puts("i2c pmic ECC_DE register read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_BITS_ECC_DE1) {
|
||||
puts(WARNBAR);
|
||||
puts("ERROR: banks 1 to 5 have uncorrectable bits\n");
|
||||
puts(WARNBAR);
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) {
|
||||
puts("i2c pmic ECC_DE register read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_BITS_ECC_DE2) {
|
||||
puts(WARNBAR);
|
||||
puts("ERROR: banks 6 to 10 have uncorrectable bits\n");
|
||||
puts(WARNBAR);
|
||||
}
|
||||
|
||||
/* get device ident */
|
||||
if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) {
|
||||
puts("i2c pmic devid read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) {
|
||||
puts("i2c pmic revid read failed\n");
|
||||
return 0;
|
||||
}
|
||||
printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid);
|
||||
|
||||
/* get device programmed state */
|
||||
val = PFUZE100_PAGE_REGISTER_PAGE1;
|
||||
if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
|
||||
puts("i2c write failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) {
|
||||
puts("i2c fuse_por read failed\n");
|
||||
return 0;
|
||||
}
|
||||
if (val & PFUZE100_FUSE_POR_M)
|
||||
programmed++;
|
||||
|
||||
if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) {
|
||||
puts("i2c fuse_por read failed\n");
|
||||
return programmed;
|
||||
}
|
||||
if (val & PFUZE100_FUSE_POR_M)
|
||||
programmed++;
|
||||
|
||||
if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) {
|
||||
puts("i2c fuse_por read failed\n");
|
||||
return programmed;
|
||||
}
|
||||
if (val & PFUZE100_FUSE_POR_M)
|
||||
programmed++;
|
||||
|
||||
switch (programmed) {
|
||||
case 0:
|
||||
puts("not programmed\n");
|
||||
break;
|
||||
case 3:
|
||||
puts("programmed\n");
|
||||
break;
|
||||
default:
|
||||
puts("undefined programming state\n");
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
{
|
||||
unsigned int i, j;
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
printf("\t%x", i);
|
||||
for (j = 0; j < 0x80; ) {
|
||||
printf("\n%2x", j);
|
||||
for (i = 0; i < 16; i++) {
|
||||
dm_i2c_read(dev, j + i, &val, 1);
|
||||
printf("\t%2x", val);
|
||||
}
|
||||
j += 0x10;
|
||||
}
|
||||
printf("\nEXT Page 1");
|
||||
|
||||
val = PFUZE100_PAGE_REGISTER_PAGE1;
|
||||
if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
|
||||
puts("i2c write failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (j = 0x80; j < 0x100; ) {
|
||||
printf("\n%2x", j);
|
||||
for (i = 0; i < 16; i++) {
|
||||
dm_i2c_read(dev, j + i, &val, 1);
|
||||
printf("\t%2x", val);
|
||||
}
|
||||
j += 0x10;
|
||||
}
|
||||
printf("\nEXT Page 2");
|
||||
|
||||
val = PFUZE100_PAGE_REGISTER_PAGE2;
|
||||
if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
|
||||
puts("i2c write failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (j = 0x80; j < 0x100; ) {
|
||||
printf("\n%2x", j);
|
||||
for (i = 0; i < 16; i++) {
|
||||
dm_i2c_read(dev, j + i, &val, 1);
|
||||
printf("\t%2x", val);
|
||||
}
|
||||
j += 0x10;
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
#endif /* DEBUG */
|
||||
|
||||
return programmed;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
static int pf0100_prog(void)
|
||||
{
|
||||
int rc;
|
||||
struct udevice *dev = NULL;
|
||||
unsigned char bus = 1;
|
||||
unsigned char val;
|
||||
unsigned int i;
|
||||
|
||||
if (pmic_init() == 3) {
|
||||
puts("PMIC already programmed, exiting\n");
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
/* set up gpio to manipulate vprog, initially off */
|
||||
imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
|
||||
ARRAY_SIZE(pmic_prog_pads));
|
||||
gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
|
||||
|
||||
rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
|
||||
if (rc) {
|
||||
printf("failed to get device for PMIC at address 0x%x\n",
|
||||
PFUZE100_I2C_ADDR);
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
|
||||
switch (pmic_otp_prog[i].cmd) {
|
||||
case pmic_i2c:
|
||||
val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
|
||||
if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) {
|
||||
printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
|
||||
pmic_otp_prog[i].reg, val);
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
break;
|
||||
case pmic_delay:
|
||||
udelay(pmic_otp_prog[i].value * 1000);
|
||||
break;
|
||||
case pmic_vpgm:
|
||||
gpio_direction_output(PMIC_PROG_VOLTAGE,
|
||||
pmic_otp_prog[i].value);
|
||||
break;
|
||||
case pmic_pwr:
|
||||
/* TODO */
|
||||
break;
|
||||
}
|
||||
}
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
int ret;
|
||||
puts("Programming PMIC OTP...");
|
||||
ret = pf0100_prog();
|
||||
if (ret == CMD_RET_SUCCESS)
|
||||
puts("done.\n");
|
||||
else
|
||||
puts("failed.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
pf0100_otp_prog, 1, 0, do_pf0100_prog,
|
||||
"Program the OTP fuses on the PMIC PF0100",
|
||||
""
|
||||
);
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
@@ -0,0 +1,107 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2014-2019, Toradex AG
|
||||
*/
|
||||
|
||||
/*
|
||||
* Helpers for Freescale PMIC PF0100
|
||||
*/
|
||||
|
||||
#ifndef PF0100_H_
|
||||
#define PF0100_H_
|
||||
|
||||
/* bit definitions */
|
||||
#define PFUZE100_BIT_0 (0x01 << 0)
|
||||
#define PFUZE100_BIT_1 (0x01 << 1)
|
||||
#define PFUZE100_BIT_2 (0x01 << 2)
|
||||
#define PFUZE100_BIT_3 (0x01 << 3)
|
||||
#define PFUZE100_BIT_4 (0x01 << 4)
|
||||
#define PFUZE100_BIT_5 (0x01 << 5)
|
||||
#define PFUZE100_BIT_6 (0x01 << 6)
|
||||
#define PFUZE100_BIT_7 (0x01 << 7)
|
||||
|
||||
/* 7-bit I2C bus slave address */
|
||||
#define PFUZE100_I2C_ADDR (0x08)
|
||||
/* Register Addresses */
|
||||
#define PFUZE100_DEVICEID (0x0)
|
||||
#define PFUZE100_REVID (0x3)
|
||||
#define PFUZE100_INTSTAT3 (0xe)
|
||||
#define PFUZE100_BIT_OTP_ECCI PFUZE100_BIT_7
|
||||
#define PFUZE100_SW1AMODE (0x23)
|
||||
#define PFUZE100_SW1ACON 36
|
||||
#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */
|
||||
#define PFUZE100_SW1ACON_SPEED_M (0x3<<6)
|
||||
#define PFUZE100_SW1CCON 49
|
||||
#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */
|
||||
#define PFUZE100_SW1CCON_SPEED_M (0x3<<6)
|
||||
#define PFUZE100_SW1AVOL 32
|
||||
#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0)
|
||||
#define PFUZE100_SW1CVOL 46
|
||||
#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0)
|
||||
#define PFUZE100_VGEN1CTL (0x6c)
|
||||
#define PFUZE100_VGEN1_VAL (0x30 + 0x08) /* Always ON, 1.2V */
|
||||
#define PFUZE100_SWBSTCTL (0x66)
|
||||
/* Always ON, Auto Switching Mode, 5.0V */
|
||||
#define PFUZE100_SWBST_VAL (0x40 + 0x08 + 0x00)
|
||||
|
||||
/* chooses the extended page (registers 0x80..0xff) */
|
||||
#define PFUZE100_PAGE_REGISTER 0x7f
|
||||
#define PFUZE100_PAGE_REGISTER_PAGE_M (0x1f << 0)
|
||||
#define PFUZE100_PAGE_REGISTER_PAGE1 (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
|
||||
#define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
|
||||
|
||||
/* extended page 1 */
|
||||
#define PFUZE100_OTP_ECC_SE1 0x8a
|
||||
#define PFUZE100_BIT_ECC1_SE PFUZE100_BIT_0
|
||||
#define PFUZE100_BIT_ECC2_SE PFUZE100_BIT_1
|
||||
#define PFUZE100_BIT_ECC3_SE PFUZE100_BIT_2
|
||||
#define PFUZE100_BIT_ECC4_SE PFUZE100_BIT_3
|
||||
#define PFUZE100_BIT_ECC5_SE PFUZE100_BIT_4
|
||||
#define PFUZE100_BITS_ECC_SE1 ((PFUZE100_BIT_ECC1_SE) | \
|
||||
(PFUZE100_BIT_ECC2_SE) | \
|
||||
(PFUZE100_BIT_ECC3_SE) | \
|
||||
(PFUZE100_BIT_ECC4_SE) | \
|
||||
(PFUZE100_BIT_ECC5_SE))
|
||||
#define PFUZE100_OTP_ECC_SE2 0x8b
|
||||
#define PFUZE100_BIT_ECC6_SE PFUZE100_BIT_0
|
||||
#define PFUZE100_BIT_ECC7_SE PFUZE100_BIT_1
|
||||
#define PFUZE100_BIT_ECC8_SE PFUZE100_BIT_2
|
||||
#define PFUZE100_BIT_ECC9_SE PFUZE100_BIT_3
|
||||
#define PFUZE100_BIT_ECC10_SE PFUZE100_BIT_4
|
||||
#define PFUZE100_BITS_ECC_SE2 ((PFUZE100_BIT_ECC6_SE) | \
|
||||
(PFUZE100_BIT_ECC7_SE) | \
|
||||
(PFUZE100_BIT_ECC8_SE) | \
|
||||
(PFUZE100_BIT_ECC9_SE) | \
|
||||
(PFUZE100_BIT_ECC10_SE))
|
||||
#define PFUZE100_OTP_ECC_DE1 0x8c
|
||||
#define PFUZE100_BIT_ECC1_DE PFUZE100_BIT_0
|
||||
#define PFUZE100_BIT_ECC2_DE PFUZE100_BIT_1
|
||||
#define PFUZE100_BIT_ECC3_DE PFUZE100_BIT_2
|
||||
#define PFUZE100_BIT_ECC4_DE PFUZE100_BIT_3
|
||||
#define PFUZE100_BIT_ECC5_DE PFUZE100_BIT_4
|
||||
#define PFUZE100_BITS_ECC_DE1 ((PFUZE100_BIT_ECC1_DE) | \
|
||||
(PFUZE100_BIT_ECC2_DE) | \
|
||||
(PFUZE100_BIT_ECC3_DE) | \
|
||||
(PFUZE100_BIT_ECC4_DE) | \
|
||||
(PFUZE100_BIT_ECC5_DE))
|
||||
#define PFUZE100_OTP_ECC_DE2 0x8d
|
||||
#define PFUZE100_BIT_ECC6_DE PFUZE100_BIT_0
|
||||
#define PFUZE100_BIT_ECC7_DE PFUZE100_BIT_1
|
||||
#define PFUZE100_BIT_ECC8_DE PFUZE100_BIT_2
|
||||
#define PFUZE100_BIT_ECC9_DE PFUZE100_BIT_3
|
||||
#define PFUZE100_BIT_ECC10_DE PFUZE100_BIT_4
|
||||
#define PFUZE100_BITS_ECC_DE2 ((PFUZE100_BIT_ECC6_DE) | \
|
||||
(PFUZE100_BIT_ECC7_DE) | \
|
||||
(PFUZE100_BIT_ECC8_DE) | \
|
||||
(PFUZE100_BIT_ECC9_DE) | \
|
||||
(PFUZE100_BIT_ECC10_DE))
|
||||
#define PFUZE100_FUSE_POR1 0xe4
|
||||
#define PFUZE100_FUSE_POR2 0xe5
|
||||
#define PFUZE100_FUSE_POR3 0xe6
|
||||
#define PFUZE100_FUSE_POR_M (0x1 << 1)
|
||||
|
||||
/* output some informational messages, return the number FUSE_POR=1 */
|
||||
/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
|
||||
unsigned pmic_init(void);
|
||||
|
||||
#endif /* PF0100_H_ */
|
||||
@@ -0,0 +1,190 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2014-2016, Toradex AG
|
||||
*/
|
||||
|
||||
// Register Output for PF0100 programmer
|
||||
// Customer: Toradex AG
|
||||
// Program: Colibri iMX6 V1.1
|
||||
// Sample marking:
|
||||
// Date: 01.05.2017
|
||||
// Time: 16:22:32
|
||||
// Generated from Spreadsheet Revision: P1.8
|
||||
|
||||
/* sed commands to get from programmer script to struct content */
|
||||
/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc
|
||||
sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
|
||||
sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc
|
||||
*/
|
||||
|
||||
enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
|
||||
struct pmic_otp_prog_t{
|
||||
unsigned char cmd;
|
||||
unsigned char reg;
|
||||
unsigned short value;
|
||||
};
|
||||
|
||||
struct pmic_otp_prog_t pmic_otp_prog[] = {
|
||||
{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
|
||||
{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
|
||||
{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
|
||||
{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
|
||||
{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
|
||||
{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
|
||||
{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
|
||||
{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
|
||||
{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
|
||||
{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
|
||||
{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
|
||||
{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
|
||||
{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
|
||||
{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
|
||||
{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
|
||||
{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
|
||||
{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
|
||||
{pmic_i2c, 0xBD, 0x0E}, // Auto gen from Row123
|
||||
{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
|
||||
{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
|
||||
{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
|
||||
{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
|
||||
{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
|
||||
{pmic_i2c, 0xD0, 0x0F}, // Auto gen from Row142
|
||||
{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
|
||||
{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
|
||||
{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
|
||||
{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
|
||||
{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
|
||||
{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
|
||||
{pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158
|
||||
|
||||
#if 0 /* TBB mode */
|
||||
{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
|
||||
{pmic_delay, 0, 10},
|
||||
#else
|
||||
// Write OTP
|
||||
{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
|
||||
{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
|
||||
{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
|
||||
{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
|
||||
{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
|
||||
{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
|
||||
{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
|
||||
{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
|
||||
//VPGM:DOWN:n
|
||||
//VPGM:UP:n
|
||||
{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
|
||||
//-----------------------------------------------------------------------------------
|
||||
// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 1
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 2
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 3
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 4
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 5
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 6
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 7
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 8
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 9
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
// BANK 10
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
|
||||
{pmic_delay, 0, 10}, // Allow time for bank programming to complete
|
||||
{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
|
||||
{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
|
||||
//-----------------------------------------------------------------------------------
|
||||
{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
|
||||
{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
|
||||
{pmic_i2c, 0xD0, 0x00}, // Clear
|
||||
{pmic_i2c, 0xD1, 0x00}, // Clear
|
||||
{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
|
||||
{pmic_delay, 0, 500},
|
||||
{pmic_pwr, 0, 1},
|
||||
#endif
|
||||
};
|
||||
@@ -0,0 +1,76 @@
|
||||
if TARGET_COLIBRI_IMX7
|
||||
|
||||
choice
|
||||
prompt "Colibri iMX7S/D variant"
|
||||
|
||||
config TARGET_COLIBRI_IMX7_NAND
|
||||
bool "Support Colibri iMX7 Solo 256MB/Dual 512MB (raw NAND) modules"
|
||||
imply NAND_MXS
|
||||
help
|
||||
Choose this option if you build for a Toradex Colibri iMX7S
|
||||
256MB or Colibri iMX7D 512MB module which do have raw NAND
|
||||
on-module.
|
||||
|
||||
config TARGET_COLIBRI_IMX7_EMMC
|
||||
bool "Support Colibri iMX7 Dual 1GB (eMMC) modules"
|
||||
help
|
||||
Choose this option if you build for a Toradex Colibri iMX7D
|
||||
1GB module which does have eMMC on-module.
|
||||
|
||||
endchoice
|
||||
|
||||
config SYS_BOARD
|
||||
default "colibri_imx7"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "colibri_imx7"
|
||||
|
||||
config COLIBRI_IMX7_EXT_PHYCLK
|
||||
bool "External oscillator for Ethernet PHY clock provided"
|
||||
help
|
||||
Select this if your module provides a external Ethernet PHY
|
||||
clock source.
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_2ND_ETHADDR
|
||||
default y
|
||||
|
||||
if TARGET_COLIBRI_IMX7_NAND
|
||||
|
||||
config TDX_HAVE_NAND
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "2048"
|
||||
|
||||
config TDX_CFG_BLOCK_OFFSET2
|
||||
default "133120"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_COLIBRI_IMX7_EMMC
|
||||
|
||||
config TDX_HAVE_MMC
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_DEV
|
||||
default "0"
|
||||
|
||||
config TDX_CFG_BLOCK_PART
|
||||
default "1"
|
||||
|
||||
# Toradex config block in eMMC, at the end of 1st "boot sector"
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "-512"
|
||||
|
||||
endif
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,12 @@
|
||||
Colibri iMX7
|
||||
M: Stefan Agner <stefan.agner@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
W: https://www.toradex.com/community
|
||||
S: Maintained
|
||||
F: board/toradex/colibri_imx7/
|
||||
F: include/configs/colibri_imx7.h
|
||||
F: configs/colibri_imx7_defconfig
|
||||
F: configs/colibri_imx7_emmc_defconfig
|
||||
F: arch/arm/dts/imx7-colibri.dtsi
|
||||
F: arch/arm/dts/imx7-colibri-emmc.dts
|
||||
F: arch/arm/dts/imx7-colibri-rawnand.dts
|
||||
@@ -0,0 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
# Copyright (C) 2016 Toradex AG
|
||||
|
||||
obj-y := colibri_imx7.o
|
||||
@@ -0,0 +1,424 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Toradex AG
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx7-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dm/platform_data/serial_mxc.h>
|
||||
#include <fdt_support.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <jffs2/load_kernel.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <mmc.h>
|
||||
#include <miiphy.h>
|
||||
#include <mtd_node.h>
|
||||
#include <netdev.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/rn5t567_pmic.h>
|
||||
#include <usb.h>
|
||||
#include <usb/ehci-ci.h>
|
||||
#include "../common/tdx-common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
|
||||
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
|
||||
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
|
||||
|
||||
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
|
||||
|
||||
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
|
||||
PAD_CTL_DSE_3P3V_49OHM)
|
||||
|
||||
#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
|
||||
|
||||
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
|
||||
|
||||
#define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX7
|
||||
static iomux_v3_cfg_t const usb_cdet_pads[] = {
|
||||
MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
|
||||
static iomux_v3_cfg_t const gpmi_pads[] = {
|
||||
MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
|
||||
};
|
||||
|
||||
static void setup_gpmi_nand(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
|
||||
|
||||
/* NAND_USDHC_BUS_CLK is set in rom */
|
||||
set_clk_nand();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
static iomux_v3_cfg_t const lcd_pads[] = {
|
||||
MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const backlight_pads[] = {
|
||||
/* Backlight On */
|
||||
MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* Backlight PWM<A> (multiplexed pin) */
|
||||
MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
|
||||
#define GPIO_PWM_A IMX_GPIO_NR(1, 8)
|
||||
|
||||
static int setup_lcd(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
|
||||
|
||||
/* Set BL_ON */
|
||||
gpio_request(GPIO_BL_ON, "BL_ON");
|
||||
gpio_direction_output(GPIO_BL_ON, 1);
|
||||
|
||||
/* Set PWM<A> to full brightness (assuming inversed polarity) */
|
||||
gpio_request(GPIO_PWM_A, "PWM<A>");
|
||||
gpio_direction_output(GPIO_PWM_A, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Backlight off before OS handover
|
||||
*/
|
||||
void board_preboot_os(void)
|
||||
{
|
||||
gpio_direction_output(GPIO_PWM_A, 1);
|
||||
gpio_direction_output(GPIO_BL_ON, 0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
||||
#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
|
||||
MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
|
||||
#else
|
||||
MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
#endif
|
||||
MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
||||
MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
||||
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_fec();
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, 0,
|
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
||||
if (ret)
|
||||
printf("FEC1 MXC: %s:failed\n", __func__);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
|
||||
/*
|
||||
* Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
|
||||
* and output it on the pin
|
||||
*/
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
|
||||
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
|
||||
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
|
||||
#else
|
||||
/* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
|
||||
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
|
||||
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
|
||||
#endif
|
||||
|
||||
return set_clk_enet(ENET_50MHZ);
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
|
||||
setup_gpmi_nand();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
setup_lcd();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX7
|
||||
imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
|
||||
gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DM_PMIC
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int reg, ver;
|
||||
int ret;
|
||||
|
||||
|
||||
ret = pmic_get("rn5t567@33", &dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
ver = pmic_reg_read(dev, RN5T567_LSIVER);
|
||||
reg = pmic_reg_read(dev, RN5T567_OTPVER);
|
||||
|
||||
printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
|
||||
|
||||
/* set judge and press timer of N_OE to minimal values */
|
||||
pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
|
||||
|
||||
/* configure sleep slot for 3.3V Ethernet */
|
||||
reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
|
||||
reg = (reg & 0xf0) | reg >> 4;
|
||||
pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
|
||||
|
||||
/* disable DCDC2 discharge to avoid backfeeding through VFB2 */
|
||||
pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
|
||||
|
||||
/* configure sleep slot for ARM rail */
|
||||
reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
|
||||
reg = (reg & 0xf0) | reg >> 4;
|
||||
pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
|
||||
|
||||
/* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
|
||||
pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
struct udevice *dev;
|
||||
|
||||
pmic_get("rn5t567@33", &dev);
|
||||
|
||||
/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
|
||||
pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
|
||||
pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
|
||||
|
||||
/*
|
||||
* Re-power factor detection on PMIC side is not instant. 1ms
|
||||
* proved to be enough time until reset takes effect.
|
||||
*/
|
||||
mdelay(1);
|
||||
}
|
||||
#endif
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("Model: Toradex Colibri iMX7%c\n",
|
||||
is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
|
||||
int up;
|
||||
|
||||
up = arch_auxiliary_core_check_up(0);
|
||||
if (up) {
|
||||
int ret;
|
||||
int areas = 1;
|
||||
u64 start[2], size[2];
|
||||
|
||||
/*
|
||||
* Reserve 1MB of memory for M4 (1MiB is also the minimum
|
||||
* alignment for Linux due to MMU section size restrictions).
|
||||
*/
|
||||
start[0] = gd->bd->bi_dram[0].start;
|
||||
size[0] = SZ_256M - SZ_1M;
|
||||
|
||||
/* If needed, create a second entry for memory beyond 256M */
|
||||
if (gd->bd->bi_dram[0].size > SZ_256M) {
|
||||
start[1] = gd->bd->bi_dram[0].start + SZ_256M;
|
||||
size[1] = gd->bd->bi_dram[0].size - SZ_256M;
|
||||
areas = 2;
|
||||
}
|
||||
|
||||
ret = fdt_set_usable_memory(blob, start, size, areas);
|
||||
if (ret) {
|
||||
eprintf("Cannot set usable memory\n");
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
int off;
|
||||
|
||||
off = fdt_node_offset_by_compatible(blob, -1,
|
||||
"fsl,imx7d-rpmsg");
|
||||
if (off > 0)
|
||||
fdt_status_disabled(blob, off);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
|
||||
static const struct node_info nodes[] = {
|
||||
{ "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
|
||||
{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
|
||||
};
|
||||
|
||||
/* Update partition nodes using info from mtdparts env var */
|
||||
puts(" Updating MTD partitions...\n");
|
||||
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
|
||||
#endif
|
||||
|
||||
return ft_common_board_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX7
|
||||
static iomux_v3_cfg_t const usb_otg2_pads[] = {
|
||||
MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
switch (port) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
if (is_cpu_type(MXC_CPU_MX7S))
|
||||
return -ENODEV;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
|
||||
ARRAY_SIZE(usb_otg2_pads));
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
switch (port) {
|
||||
case 0:
|
||||
if (gpio_get_value(USB_CDET_GPIO))
|
||||
return USB_INIT_DEVICE;
|
||||
else
|
||||
return USB_INIT_HOST;
|
||||
case 1:
|
||||
default:
|
||||
return USB_INIT_HOST;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,149 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
* 2015 Toradex AG
|
||||
*
|
||||
* Refer doc/README.imximage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : sd
|
||||
*/
|
||||
|
||||
BOOT_FROM sd
|
||||
|
||||
/*
|
||||
* Secure boot support
|
||||
*/
|
||||
#ifdef CONFIG_IMX_HAB
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
/* IOMUXC_GPR_GPR1 */
|
||||
DATA 4 0x30340004 0x4F400005
|
||||
|
||||
/* DDR3L */
|
||||
/* assuming MEMC_FREQ_RATIO = 2 */
|
||||
/* SRC_DDRC_RCR */
|
||||
DATA 4 0x30391000 0x00000002
|
||||
/* DDRC_MSTR */
|
||||
DATA 4 0x307a0000 0x01040001
|
||||
/* DDRC_DFIUPD0 */
|
||||
DATA 4 0x307a01a0 0x80400003
|
||||
/* DDRC_DFIUPD1 */
|
||||
DATA 4 0x307a01a4 0x00100020
|
||||
/* DDRC_DFIUPD2 */
|
||||
DATA 4 0x307a01a8 0x80100004
|
||||
/* DDRC_RFSHTMG */
|
||||
DATA 4 0x307a0064 0x00400046
|
||||
/* DDRC_MP_PCTRL_0 */
|
||||
DATA 4 0x307a0490 0x00000001
|
||||
/* DDRC_INIT0 */
|
||||
DATA 4 0x307a00d0 0x00020083
|
||||
/* DDRC_INIT1 */
|
||||
DATA 4 0x307a00d4 0x00690000
|
||||
/* DDRC_INIT3 MR0/MR1 */
|
||||
DATA 4 0x307a00dc 0x09300004
|
||||
/* DDRC_INIT4 MR2/MR3 */
|
||||
DATA 4 0x307a00e0 0x04480000
|
||||
/* DDRC_INIT5 */
|
||||
DATA 4 0x307a00e4 0x00100004
|
||||
/* DDRC_RANKCTL */
|
||||
DATA 4 0x307a00f4 0x0000033f
|
||||
/* DDRC_DRAMTMG0 */
|
||||
DATA 4 0x307a0100 0x0910090a
|
||||
/* DDRC_DRAMTMG1 */
|
||||
DATA 4 0x307a0104 0x000d020e
|
||||
/* DDRC_DRAMTMG2 */
|
||||
DATA 4 0x307a0108 0x03040307
|
||||
/* DDRC_DRAMTMG3 */
|
||||
DATA 4 0x307a010c 0x00002006
|
||||
/* DDRC_DRAMTMG4 */
|
||||
DATA 4 0x307a0110 0x04020204
|
||||
/* DDRC_DRAMTMG5 */
|
||||
DATA 4 0x307a0114 0x03030202
|
||||
/* DDRC_DRAMTMG8 */
|
||||
DATA 4 0x307a0120 0x00000803
|
||||
/* DDRC_ZQCTL0 */
|
||||
DATA 4 0x307a0180 0x00800020
|
||||
/* DDRC_ZQCTL1 */
|
||||
DATA 4 0x307a0184 0x02001000
|
||||
/* DDRC_DFITMG0 */
|
||||
DATA 4 0x307a0190 0x02098204
|
||||
/* DDRC_DFITMG1 */
|
||||
DATA 4 0x307a0194 0x00030303
|
||||
/* DDRC_ADDRMAP0 */
|
||||
DATA 4 0x307a0200 0x0000001f
|
||||
/* DDRC_ADDRMAP1 */
|
||||
DATA 4 0x307a0204 0x00080808
|
||||
/* DDRC_ADDRMAP5 */
|
||||
DATA 4 0x307a0214 0x07070707
|
||||
/* DDRC_ADDRMAP6 */
|
||||
DATA 4 0x307a0218 0x07070707
|
||||
/* DDRC_ODTCFG */
|
||||
DATA 4 0x307a0240 0x06000601
|
||||
/* DDRC_ODTMAP */
|
||||
DATA 4 0x307a0244 0x00000001
|
||||
/* SRC_DDRC_RCR */
|
||||
DATA 4 0x30391000 0x00000000
|
||||
/* DDR_PHY_PHY_CON0 */
|
||||
DATA 4 0x30790000 0x17420f40
|
||||
/* DDR_PHY_PHY_CON1 */
|
||||
DATA 4 0x30790004 0x10210100
|
||||
/* DDR_PHY_PHY_CON4 */
|
||||
DATA 4 0x30790010 0x00060807
|
||||
/* DDR_PHY_MDLL_CON0 */
|
||||
DATA 4 0x307900b0 0x1010007e
|
||||
/* DDR_PHY_DRVDS_CON0 */
|
||||
DATA 4 0x3079009c 0x00000d6e
|
||||
/* DDR_PHY_OFFSET_RD_CON0 */
|
||||
DATA 4 0x30790020 0x08080808
|
||||
/* DDR_PHY_OFFSET_WR_CON0 */
|
||||
DATA 4 0x30790030 0x08080808
|
||||
/* DDR_PHY_CMD_SDLL_CON0 */
|
||||
DATA 4 0x30790050 0x01000010
|
||||
DATA 4 0x30790050 0x00000010
|
||||
|
||||
/* DDR_PHY_ZQ_CON0 */
|
||||
DATA 4 0x307900c0 0x0e407304
|
||||
DATA 4 0x307900c0 0x0e447304
|
||||
DATA 4 0x307900c0 0x0e447306
|
||||
/* DDR_PHY_ZQ_CON1 */
|
||||
CHECK_BITS_SET 4 0x307900c4 0x1
|
||||
/* DDR_PHY_ZQ_CON0 */
|
||||
DATA 4 0x307900c0 0x0e447304
|
||||
DATA 4 0x307900c0 0x0e407304
|
||||
|
||||
/* CCM_CCGRn */
|
||||
DATA 4 0x30384130 0x00000000
|
||||
/* IOMUXC_GPR_GPR8 */
|
||||
DATA 4 0x30340020 0x00000178
|
||||
/* CCM_CCGRn */
|
||||
DATA 4 0x30384130 0x00000002
|
||||
/* DDR_PHY_LP_CON0 */
|
||||
DATA 4 0x30790018 0x0000000f
|
||||
|
||||
/* DDRC_STAT */
|
||||
CHECK_BITS_SET 4 0x307a0004 0x1
|
||||
@@ -0,0 +1,23 @@
|
||||
if TARGET_COLIBRI_PXA270
|
||||
|
||||
config SYS_BOARD
|
||||
default "colibri_pxa270"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "colibri_pxa270"
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_HAVE_NOR
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "262144"
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
COLIBRI_PXA270 BOARD
|
||||
M: Marek Vasut <marek.vasut@gmail.com>
|
||||
S: Maintained
|
||||
F: board/toradex/colibri_pxa270/
|
||||
F: include/configs/colibri_pxa270.h
|
||||
F: configs/colibri_pxa270_defconfig
|
||||
@@ -0,0 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Toradex Colibri PXA270 Support
|
||||
#
|
||||
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
|
||||
obj-y := colibri_pxa270.o
|
||||
@@ -0,0 +1,139 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Toradex Colibri PXA270 Support
|
||||
*
|
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
||||
* Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <dm.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/pxa.h>
|
||||
#include <asm/arch/regs-mmc.h>
|
||||
#include <asm/arch/regs-uart.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm/platdata.h>
|
||||
#include <dm/platform_data/serial_pxa.h>
|
||||
#include <netdev.h>
|
||||
#include <serial.h>
|
||||
#include <usb.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include "../common/tdx-common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* We have RAM, disable cache */
|
||||
dcache_disable();
|
||||
icache_disable();
|
||||
|
||||
/* arch number of Toradex Colibri PXA270 */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = 0xa0000100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Model: Toradex Colibri PXA270\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
return ft_common_board_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
pxa2xx_dram_init();
|
||||
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
int board_usb_init(int index, enum usb_init_type init)
|
||||
{
|
||||
writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
|
||||
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
|
||||
UHCHR);
|
||||
|
||||
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
|
||||
|
||||
while (UHCHR & UHCHR_FSBIR)
|
||||
;
|
||||
|
||||
writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
|
||||
writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
|
||||
|
||||
/* Clear any OTG Pin Hold */
|
||||
if (readl(PSSR) & PSSR_OTGPH)
|
||||
writel(readl(PSSR) | PSSR_OTGPH, PSSR);
|
||||
|
||||
writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
|
||||
writel(readl(UHCRHDA) | 0x100, UHCRHDA);
|
||||
|
||||
/* Set port power control mask bits, only 3 ports. */
|
||||
writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
|
||||
|
||||
/* enable port 2 */
|
||||
writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
|
||||
UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_usb_cleanup(int index, enum usb_init_type init)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void usb_board_stop(void)
|
||||
{
|
||||
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
|
||||
udelay(11);
|
||||
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
|
||||
|
||||
writel(readl(UHCCOMS) | 1, UHCCOMS);
|
||||
udelay(10);
|
||||
|
||||
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DRIVER_DM9000
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return dm9000_initialize(bis);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_MMC
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
pxa_mmc_register(0);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct pxa_serial_platdata serial_platdata = {
|
||||
.base = (struct pxa_uart_regs *)FFUART_BASE,
|
||||
.port = FFUART_INDEX,
|
||||
.baudrate = CONFIG_BAUDRATE,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(pxa_serials) = {
|
||||
.name = "serial_pxa",
|
||||
.platdata = &serial_platdata,
|
||||
};
|
||||
@@ -0,0 +1,23 @@
|
||||
if TARGET_COLIBRI_T20
|
||||
|
||||
config SYS_BOARD
|
||||
default "colibri_t20"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "colibri_t20"
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_HAVE_NAND
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "3145728"
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,7 @@
|
||||
COLIBRI_T20
|
||||
M: Lucas Stach <dev@lynxeye.de>
|
||||
S: Maintained
|
||||
F: board/toradex/colibri_t20/
|
||||
F: include/configs/colibri_t20.h
|
||||
F: configs/colibri_t20_defconfig
|
||||
F: arch/arm/dts/tegra20-colibri.dtb
|
||||
@@ -0,0 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2012 Lucas Stach
|
||||
|
||||
obj-y += colibri_t20.o
|
||||
@@ -0,0 +1,162 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2012 Lucas Stach
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/funcmux.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch-tegra/ap.h>
|
||||
#include <asm/arch-tegra/board.h>
|
||||
#include <asm/arch-tegra/tegra.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <i2c.h>
|
||||
#include <nand.h>
|
||||
#include "../common/tdx-common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define PMU_I2C_ADDRESS 0x34
|
||||
#define MAX_I2C_RETRY 3
|
||||
#define PMU_SUPPLYENE 0x14
|
||||
#define PMU_SUPPLYENE_SYSINEN (1<<5)
|
||||
#define PMU_SUPPLYENE_EXITSLREQ (1<<1)
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
/* Disable PMIC sleep mode on low supply voltage */
|
||||
struct udevice *dev;
|
||||
u8 addr, data[1];
|
||||
int err;
|
||||
|
||||
err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
|
||||
if (err) {
|
||||
debug("%s: Cannot find PMIC I2C chip\n", __func__);
|
||||
return err;
|
||||
}
|
||||
|
||||
addr = PMU_SUPPLYENE;
|
||||
|
||||
err = dm_i2c_read(dev, addr, data, 1);
|
||||
if (err) {
|
||||
debug("failed to get PMU_SUPPLYENE\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
data[0] &= ~PMU_SUPPLYENE_SYSINEN;
|
||||
data[0] |= PMU_SUPPLYENE_EXITSLREQ;
|
||||
|
||||
err = dm_i2c_write(dev, addr, data, 1);
|
||||
if (err) {
|
||||
debug("failed to set PMU_SUPPLYENE\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/* make sure SODIMM pin 87 nRESET_OUT is released properly */
|
||||
pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI);
|
||||
|
||||
if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
|
||||
NVBOOTTYPE_RECOVERY)
|
||||
printf("USB recovery mode\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("Model: Toradex Colibri T20 %dMB V%s\n",
|
||||
(gd->ram_size == 0x10000000) ? 256 : 512,
|
||||
(get_nand_dev_by_index(0)->erasesize >> 10 == 512) ?
|
||||
((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
return ft_common_board_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC_SDHCI_TEGRA
|
||||
/*
|
||||
* Routine: pin_mux_mmc
|
||||
* Description: setup the pin muxes/tristate values for the SDMMC(s)
|
||||
*/
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
|
||||
pinmux_tristate_disable(PMUX_PINGRP_GMB);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TEGRA_NAND
|
||||
void pin_mux_nand(void)
|
||||
{
|
||||
funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
|
||||
|
||||
/*
|
||||
* configure pingroup ATC to something unrelated to
|
||||
* avoid ATC overriding KBC
|
||||
*/
|
||||
pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_TEGRA
|
||||
void pin_mux_usb(void)
|
||||
{
|
||||
/* module internal USB bus to connect ethernet chipset */
|
||||
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
|
||||
|
||||
/* ULPI reference clock output */
|
||||
pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
|
||||
pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
|
||||
|
||||
/* PHY reset GPIO */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_UAC);
|
||||
|
||||
/* VBus GPIO */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_DTE);
|
||||
|
||||
/* Reset ASIX using LAN_RESET */
|
||||
gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
|
||||
gpio_direction_output(TEGRA_GPIO(V, 4), 0);
|
||||
pinmux_tristate_disable(PMUX_PINGRP_GPV);
|
||||
udelay(5);
|
||||
gpio_set_value(TEGRA_GPIO(V, 4), 1);
|
||||
|
||||
/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
|
||||
pinmux_tristate_disable(PMUX_PINGRP_SPIG);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_TEGRA20
|
||||
/*
|
||||
* Routine: pin_mux_display
|
||||
* Description: setup the pin muxes/tristate values for the LCD interface)
|
||||
*/
|
||||
void pin_mux_display(void)
|
||||
{
|
||||
/*
|
||||
* Manually untristate BL_ON (PT4 - SODIMM 71) as specified through
|
||||
* device-tree
|
||||
*/
|
||||
pinmux_tristate_disable(PMUX_PINGRP_DTA);
|
||||
|
||||
pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
|
||||
pinmux_tristate_disable(PMUX_PINGRP_SDC);
|
||||
}
|
||||
|
||||
/*
|
||||
* Backlight off before OS handover
|
||||
*/
|
||||
void board_preboot_os(void)
|
||||
{
|
||||
gpio_request(TEGRA_GPIO(T, 4), "BL_ON");
|
||||
gpio_direction_output(TEGRA_GPIO(T, 4), 0);
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,30 @@
|
||||
if TARGET_COLIBRI_T30
|
||||
|
||||
config SYS_BOARD
|
||||
default "colibri_t30"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "colibri_t30"
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_HAVE_MMC
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_DEV
|
||||
default "0"
|
||||
|
||||
config TDX_CFG_BLOCK_PART
|
||||
default "1"
|
||||
|
||||
# Toradex config block in eMMC, at the end of 1st "boot sector"
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "-512"
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,7 @@
|
||||
Colibri T30
|
||||
M: Stefan Agner <stefan.agner@toradex.com>
|
||||
S: Maintained
|
||||
F: board/toradex/colibri_t30/
|
||||
F: include/configs/colibri_t30.h
|
||||
F: configs/colibri_t30_defconfig
|
||||
F: arch/arm/dts/tegra30-colibri.dtb
|
||||
@@ -0,0 +1,4 @@
|
||||
# Copyright (c) 2013-2014 Stefan Agner
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-y += colibri_t30.o
|
||||
@@ -0,0 +1,77 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2014-2016
|
||||
* Stefan Agner <stefan@agner.ch>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/gp_padctrl.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch-tegra/ap.h>
|
||||
#include <asm/arch-tegra/tegra.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <i2c.h>
|
||||
#include "pinmux-config-colibri_t30.h"
|
||||
#include "../common/tdx-common.h"
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
|
||||
NVBOOTTYPE_RECOVERY)
|
||||
printf("USB recovery mode\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Model: Toradex Colibri T30 1GB\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
return ft_common_board_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_config_pingrp_table(tegra3_pinmux_common,
|
||||
ARRAY_SIZE(tegra3_pinmux_common));
|
||||
|
||||
pinmux_config_pingrp_table(unused_pins_lowpower,
|
||||
ARRAY_SIZE(unused_pins_lowpower));
|
||||
|
||||
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
|
||||
pinmux_config_drvgrp_table(colibri_t30_padctrl,
|
||||
ARRAY_SIZE(colibri_t30_padctrl));
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable AX88772B USB to LAN controller
|
||||
*/
|
||||
void pin_mux_usb(void)
|
||||
{
|
||||
/* Reset ASIX using LAN_RESET */
|
||||
gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET");
|
||||
gpio_direction_output(TEGRA_GPIO(DD, 0), 0);
|
||||
udelay(5);
|
||||
gpio_set_value(TEGRA_GPIO(DD, 0), 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Backlight off before OS handover
|
||||
*/
|
||||
void board_preboot_os(void)
|
||||
{
|
||||
gpio_request(TEGRA_GPIO(V, 2), "BL_ON");
|
||||
gpio_direction_output(TEGRA_GPIO(V, 2), 0);
|
||||
}
|
||||
+349
@@ -0,0 +1,349 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2013-2014, Stefan Agner
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_COLIBRI_T30_H_
|
||||
#define _PINMUX_CONFIG_COLIBRI_T30_H_
|
||||
|
||||
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
|
||||
}
|
||||
|
||||
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static struct pmux_pingrp_config tegra3_pinmux_common[] = {
|
||||
/* SDMMC1 disabled */
|
||||
DEFAULT_PINMUX(SDMMC1_CLK_PZ0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_CMD_PZ1, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT3_PY4, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT2_PY5, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT1_PY6, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC1_DAT0_PY7, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC3 pinmux */
|
||||
DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SDMMC4 pinmux (eMMC) */
|
||||
LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* I2C1 pinmux */
|
||||
I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* I2C2 pinmux */
|
||||
DEFAULT_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* I2C3 pinmux, muliplexed with KB_ROW13/KB_ROW14 */
|
||||
I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* I2C4 pinmux */
|
||||
I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* Power I2C pinmux */
|
||||
I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
/* UARTA RX, make sure we don't get input form a floating Pin */
|
||||
DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
|
||||
DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
|
||||
DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
|
||||
DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, INPUT),
|
||||
|
||||
|
||||
/* Multiplexed with KB_ROW10/KB_ROW11/KB_ROW12/KB_ROW15 */
|
||||
DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(PBB3, VGP3, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* KBC keys */
|
||||
DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* SDMMC2 pinmux */
|
||||
DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* LAN_RESET */
|
||||
DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* LAN_VBUS */
|
||||
DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* GPIOs */
|
||||
/* SDMMC1 CD gpio */
|
||||
DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
|
||||
/* SDMMC1 WP gpio */
|
||||
LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* Touch panel GPIO */
|
||||
/* Touch IRQ */
|
||||
DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
|
||||
|
||||
/* Touch RESET */
|
||||
DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* Power rails GPIO */
|
||||
DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
|
||||
|
||||
LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
};
|
||||
|
||||
static struct pmux_pingrp_config unused_pins_lowpower[] = {
|
||||
DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
};
|
||||
|
||||
static struct pmux_drvgrp_config colibri_t30_padctrl[] = {
|
||||
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
|
||||
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
|
||||
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
|
||||
};
|
||||
#endif /* _PINMUX_CONFIG_COLIBRI_T30_H_ */
|
||||
@@ -0,0 +1,26 @@
|
||||
if TARGET_COLIBRI_VF
|
||||
|
||||
config SYS_BOARD
|
||||
default "colibri_vf"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "colibri_vf"
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_HAVE_NAND
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "2048"
|
||||
|
||||
config TDX_CFG_BLOCK_2ND_ETHADDR
|
||||
default y
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,12 @@
|
||||
Colibri VFxx
|
||||
M: Stefan Agner <stefan.agner@toradex.com>
|
||||
W: http://developer.toradex.com/software/linux/linux-software
|
||||
W: https://www.toradex.com/community
|
||||
S: Maintained
|
||||
F: board/toradex/colibri_vf/
|
||||
F: include/configs/colibri_vf.h
|
||||
F: configs/colibri_vf_defconfig
|
||||
F: arch/arm/dts/vf-colibri.dtsi
|
||||
F: arch/arm/dts/vf-colibri-u-boot.dtsi
|
||||
F: arch/arm/dts/vf500-colibri.dts
|
||||
F: arch/arm/dts/vf610-colibri.dts
|
||||
@@ -0,0 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright 2013 Freescale Semiconductor, Inc.
|
||||
|
||||
obj-y := colibri_vf.o
|
||||
obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
|
||||
@@ -0,0 +1,464 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2015-2019 Toradex, Inc.
|
||||
*
|
||||
* Based on vf610twr.c:
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/ddrmc-vf610.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux-vf610.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <env.h>
|
||||
#include <fdt_support.h>
|
||||
#include <fsl_dcu_fb.h>
|
||||
#include <g_dnl.h>
|
||||
#include <jffs2/load_kernel.h>
|
||||
#include <mtd_node.h>
|
||||
#include <usb.h>
|
||||
|
||||
#include "../common/tdx-common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define PTC0_GPIO_45 45
|
||||
|
||||
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
|
||||
{ DDRMC_CR79_CTLUPD_AREF(1), 79 },
|
||||
/* sets manual values for read lvl. (gate) delay of data slice 0/1 */
|
||||
{ DDRMC_CR105_RDLVL_DL_0(28), 105 },
|
||||
{ DDRMC_CR106_RDLVL_GTDL_0(24), 106 },
|
||||
{ DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 },
|
||||
{ DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 },
|
||||
|
||||
/* AXI */
|
||||
{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
|
||||
{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
|
||||
{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
|
||||
DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
|
||||
{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
|
||||
DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
|
||||
{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
|
||||
DDRMC_CR122_AXI0_PRIRLX(100), 122 },
|
||||
{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
|
||||
DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
|
||||
{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
|
||||
{ DDRMC_CR126_PHY_RDLAT(8), 126 },
|
||||
{ DDRMC_CR132_WRLAT_ADJ(5) |
|
||||
DDRMC_CR132_RDLAT_ADJ(6), 132 },
|
||||
{ DDRMC_CR137_PHYCTL_DL(2), 137 },
|
||||
{ DDRMC_CR138_PHY_WRLV_MXDL(256) |
|
||||
DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
|
||||
{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
|
||||
DDRMC_CR139_PHY_WRLV_DLL(3) |
|
||||
DDRMC_CR139_PHY_WRLV_EN(3), 139 },
|
||||
{ DDRMC_CR140_PHY_WRLV_WW(64), 140 },
|
||||
{ DDRMC_CR143_RDLV_GAT_MXDL(1536) |
|
||||
DDRMC_CR143_RDLV_MXDL(128), 143 },
|
||||
{ DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
|
||||
DDRMC_CR144_PHY_RDLV_DLL(3) |
|
||||
DDRMC_CR144_PHY_RDLV_EN(3), 144 },
|
||||
{ DDRMC_CR145_PHY_RDLV_RR(64), 145 },
|
||||
{ DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
|
||||
{ DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
|
||||
{ DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
|
||||
{ DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
|
||||
DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
|
||||
|
||||
{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
|
||||
DDRMC_CR154_PAD_ZQ_MODE(1) |
|
||||
DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
|
||||
DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
|
||||
{ DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 },
|
||||
{ DDRMC_CR158_TWR(6), 158 },
|
||||
{ DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
|
||||
DDRMC_CR161_TODTH_WR(2), 161 },
|
||||
/* end marker */
|
||||
{ 0, -1 }
|
||||
};
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
static const struct ddr3_jedec_timings timings = {
|
||||
.tinit = 5,
|
||||
.trst_pwron = 80000,
|
||||
.cke_inactive = 200000,
|
||||
.wrlat = 5,
|
||||
.caslat_lin = 12,
|
||||
.trc = 21,
|
||||
.trrd = 4,
|
||||
.tccd = 4,
|
||||
.tbst_int_interval = 0,
|
||||
.tfaw = 20,
|
||||
.trp = 6,
|
||||
.twtr = 4,
|
||||
.tras_min = 15,
|
||||
.tmrd = 4,
|
||||
.trtp = 4,
|
||||
.tras_max = 28080,
|
||||
.tmod = 12,
|
||||
.tckesr = 4,
|
||||
.tcke = 3,
|
||||
.trcd_int = 6,
|
||||
.tras_lockout = 0,
|
||||
.tdal = 12,
|
||||
.bstlen = 3,
|
||||
.tdll = 512, /* not applicable since freq. scaling
|
||||
* is not used
|
||||
*/
|
||||
.trp_ab = 6,
|
||||
.tref = 3120,
|
||||
.trfc = 64,
|
||||
.tref_int = 0,
|
||||
.tpdex = 3,
|
||||
.txpdll = 10,
|
||||
.txsnr = 68, /* changed to conform to JEDEC
|
||||
* specifications
|
||||
*/
|
||||
.txsr = 506, /* changed to conform to JEDEC
|
||||
* specifications
|
||||
*/
|
||||
.cksrx = 5,
|
||||
.cksre = 5,
|
||||
.freq_chg_en = 0,
|
||||
.zqcl = 256,
|
||||
.zqinit = 512,
|
||||
.zqcs = 64,
|
||||
.ref_per_zq = 64,
|
||||
.zqcs_rotate = 0,
|
||||
.aprebit = 10,
|
||||
.cmd_age_cnt = 64,
|
||||
.age_cnt = 64,
|
||||
.q_fullness = 7,
|
||||
.odt_rd_mapcs0 = 0,
|
||||
.odt_wr_mapcs0 = 1,
|
||||
.wlmrd = 40,
|
||||
.wldqsen = 25,
|
||||
};
|
||||
|
||||
ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_VYBRID_GPIO
|
||||
static void setup_iomux_gpio(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t gpio_pads[] = {
|
||||
VF610_PAD_PTA17__GPIO_7,
|
||||
VF610_PAD_PTA20__GPIO_10,
|
||||
VF610_PAD_PTA21__GPIO_11,
|
||||
VF610_PAD_PTA30__GPIO_20,
|
||||
VF610_PAD_PTA31__GPIO_21,
|
||||
VF610_PAD_PTB0__GPIO_22,
|
||||
VF610_PAD_PTB1__GPIO_23,
|
||||
VF610_PAD_PTB6__GPIO_28,
|
||||
VF610_PAD_PTB7__GPIO_29,
|
||||
VF610_PAD_PTB8__GPIO_30,
|
||||
VF610_PAD_PTB9__GPIO_31,
|
||||
VF610_PAD_PTB12__GPIO_34,
|
||||
VF610_PAD_PTB13__GPIO_35,
|
||||
VF610_PAD_PTB16__GPIO_38,
|
||||
VF610_PAD_PTB17__GPIO_39,
|
||||
VF610_PAD_PTB18__GPIO_40,
|
||||
VF610_PAD_PTB21__GPIO_43,
|
||||
VF610_PAD_PTB22__GPIO_44,
|
||||
VF610_PAD_PTC0__GPIO_45,
|
||||
VF610_PAD_PTC1__GPIO_46,
|
||||
VF610_PAD_PTC2__GPIO_47,
|
||||
VF610_PAD_PTC3__GPIO_48,
|
||||
VF610_PAD_PTC4__GPIO_49,
|
||||
VF610_PAD_PTC5__GPIO_50,
|
||||
VF610_PAD_PTC6__GPIO_51,
|
||||
VF610_PAD_PTC7__GPIO_52,
|
||||
VF610_PAD_PTC8__GPIO_53,
|
||||
VF610_PAD_PTD31__GPIO_63,
|
||||
VF610_PAD_PTD30__GPIO_64,
|
||||
VF610_PAD_PTD29__GPIO_65,
|
||||
VF610_PAD_PTD28__GPIO_66,
|
||||
VF610_PAD_PTD27__GPIO_67,
|
||||
VF610_PAD_PTD26__GPIO_68,
|
||||
VF610_PAD_PTD25__GPIO_69,
|
||||
VF610_PAD_PTD24__GPIO_70,
|
||||
VF610_PAD_PTD9__GPIO_88,
|
||||
VF610_PAD_PTD10__GPIO_89,
|
||||
VF610_PAD_PTD11__GPIO_90,
|
||||
VF610_PAD_PTD12__GPIO_91,
|
||||
VF610_PAD_PTD13__GPIO_92,
|
||||
VF610_PAD_PTB23__GPIO_93,
|
||||
VF610_PAD_PTB26__GPIO_96,
|
||||
VF610_PAD_PTB28__GPIO_98,
|
||||
VF610_PAD_PTC30__GPIO_103,
|
||||
VF610_PAD_PTA7__GPIO_134,
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_FSL_DCU_FB
|
||||
static void setup_iomux_fsl_dcu(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t dcu0_pads[] = {
|
||||
VF610_PAD_PTE0__DCU0_HSYNC,
|
||||
VF610_PAD_PTE1__DCU0_VSYNC,
|
||||
VF610_PAD_PTE2__DCU0_PCLK,
|
||||
VF610_PAD_PTE4__DCU0_DE,
|
||||
VF610_PAD_PTE5__DCU0_R0,
|
||||
VF610_PAD_PTE6__DCU0_R1,
|
||||
VF610_PAD_PTE7__DCU0_R2,
|
||||
VF610_PAD_PTE8__DCU0_R3,
|
||||
VF610_PAD_PTE9__DCU0_R4,
|
||||
VF610_PAD_PTE10__DCU0_R5,
|
||||
VF610_PAD_PTE11__DCU0_R6,
|
||||
VF610_PAD_PTE12__DCU0_R7,
|
||||
VF610_PAD_PTE13__DCU0_G0,
|
||||
VF610_PAD_PTE14__DCU0_G1,
|
||||
VF610_PAD_PTE15__DCU0_G2,
|
||||
VF610_PAD_PTE16__DCU0_G3,
|
||||
VF610_PAD_PTE17__DCU0_G4,
|
||||
VF610_PAD_PTE18__DCU0_G5,
|
||||
VF610_PAD_PTE19__DCU0_G6,
|
||||
VF610_PAD_PTE20__DCU0_G7,
|
||||
VF610_PAD_PTE21__DCU0_B0,
|
||||
VF610_PAD_PTE22__DCU0_B1,
|
||||
VF610_PAD_PTE23__DCU0_B2,
|
||||
VF610_PAD_PTE24__DCU0_B3,
|
||||
VF610_PAD_PTE25__DCU0_B4,
|
||||
VF610_PAD_PTE26__DCU0_B5,
|
||||
VF610_PAD_PTE27__DCU0_B6,
|
||||
VF610_PAD_PTE28__DCU0_B7,
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
|
||||
}
|
||||
|
||||
static void setup_tcon(void)
|
||||
{
|
||||
setbits_le32(TCON0_BASE_ADDR, (1 << 29));
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline int is_colibri_vf61(void)
|
||||
{
|
||||
struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
|
||||
|
||||
/*
|
||||
* Detect board type by Level 2 Cache: VF50 don't have any
|
||||
* Level 2 Cache.
|
||||
*/
|
||||
return !!mscm->cpxcfg1;
|
||||
}
|
||||
|
||||
static void clock_init(void)
|
||||
{
|
||||
struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
|
||||
struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
|
||||
u32 pfd_clk_sel, ddr_clk_sel;
|
||||
|
||||
clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR0_UART0_CTRL_MASK);
|
||||
#ifdef CONFIG_FSL_DSPI
|
||||
setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
|
||||
#endif
|
||||
clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
|
||||
CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
|
||||
CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
|
||||
CCM_CCGR4_GPC_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR7_SDHC1_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR10_NFC_CTRL_MASK);
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_VF
|
||||
setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
|
||||
setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
|
||||
|
||||
clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
|
||||
ANADIG_PLL3_CTRL_POWERDOWN |
|
||||
ANADIG_PLL3_CTRL_DIV_SELECT,
|
||||
ANADIG_PLL3_CTRL_ENABLE);
|
||||
clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
|
||||
ANADIG_PLL7_CTRL_POWERDOWN |
|
||||
ANADIG_PLL7_CTRL_DIV_SELECT,
|
||||
ANADIG_PLL7_CTRL_ENABLE);
|
||||
#endif
|
||||
|
||||
clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
|
||||
ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
|
||||
ANADIG_PLL5_CTRL_DIV_SELECT);
|
||||
|
||||
if (is_colibri_vf61()) {
|
||||
clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
|
||||
ANADIG_PLL2_CTRL_POWERDOWN,
|
||||
ANADIG_PLL2_CTRL_ENABLE |
|
||||
ANADIG_PLL2_CTRL_DIV_SELECT);
|
||||
}
|
||||
|
||||
clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
|
||||
ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
|
||||
|
||||
clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
|
||||
CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
|
||||
|
||||
/* See "Typical PLL Configuration" */
|
||||
if (is_colibri_vf61()) {
|
||||
pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
|
||||
ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
|
||||
} else {
|
||||
pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
|
||||
ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
|
||||
}
|
||||
|
||||
clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
|
||||
CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
|
||||
CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
|
||||
CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
|
||||
CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
|
||||
ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
|
||||
CCM_CCSR_SYS_CLK_SEL(4));
|
||||
|
||||
clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
|
||||
CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
|
||||
CCM_CACRR_ARM_CLK_DIV(0));
|
||||
clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
|
||||
CCM_CSCMR1_NFC_CLK_SEL(0));
|
||||
clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCDR1_RMII_CLK_EN);
|
||||
clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
|
||||
CCM_CSCDR2_NFC_EN);
|
||||
clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCDR3_NFC_PRE_DIV(3));
|
||||
clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCMR2_RMII_CLK_SEL(2));
|
||||
|
||||
#ifdef CONFIG_VIDEO_FSL_DCU_FB
|
||||
setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
|
||||
setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void mscm_init(void)
|
||||
{
|
||||
struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MSCM_IRSPRC_NUM; i++)
|
||||
writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
clock_init();
|
||||
mscm_init();
|
||||
|
||||
#ifdef CONFIG_VYBRID_GPIO
|
||||
setup_iomux_gpio();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_FSL_DCU_FB
|
||||
setup_tcon();
|
||||
setup_iomux_fsl_dcu();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INIT
|
||||
int board_late_init(void)
|
||||
{
|
||||
struct src *src = (struct src *)SRC_BASE_ADDR;
|
||||
|
||||
if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
|
||||
== SRC_SBMR2_BMOD_SERIAL) {
|
||||
printf("Serial Downloader recovery mode, disable autoboot\n");
|
||||
env_set("bootdelay", "-1");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_BOARD_LATE_INIT */
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
|
||||
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
/*
|
||||
* Enable external 32K Oscillator
|
||||
*
|
||||
* The internal clock experiences significant drift
|
||||
* so we must use the external oscillator in order
|
||||
* to maintain correct time in the hwclock
|
||||
*/
|
||||
setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
if (is_colibri_vf61())
|
||||
puts("Model: Toradex Colibri VF61\n");
|
||||
else
|
||||
puts("Model: Toradex Colibri VF50\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#ifndef CONFIG_DM_VIDEO
|
||||
int ret = 0;
|
||||
#endif
|
||||
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
|
||||
static const struct node_info nodes[] = {
|
||||
{ "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
|
||||
};
|
||||
|
||||
/* Update partition nodes using info from mtdparts env var */
|
||||
puts(" Updating MTD partitions...\n");
|
||||
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
|
||||
#endif
|
||||
#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO)
|
||||
ret = fsl_dcu_fixedfb_setup(blob);
|
||||
if (ret)
|
||||
return ret;
|
||||
#endif
|
||||
|
||||
return ft_common_board_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Backlight off before OS handover
|
||||
*/
|
||||
void board_preboot_os(void)
|
||||
{
|
||||
gpio_request(PTC0_GPIO_45, "BL_ON");
|
||||
gpio_direction_output(PTC0_GPIO_45, 0);
|
||||
}
|
||||
@@ -0,0 +1,38 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2017 Toradex AG
|
||||
*
|
||||
* FSL DCU platform driver
|
||||
*/
|
||||
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <fsl_dcu_fb.h>
|
||||
#include "div64.h"
|
||||
|
||||
unsigned int dcu_set_pixel_clock(unsigned int pixclock)
|
||||
{
|
||||
struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
|
||||
unsigned long long div;
|
||||
|
||||
clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
|
||||
clrsetbits_le32(&ccm->cscdr3,
|
||||
CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
|
||||
CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
|
||||
div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
|
||||
do_div(div, pixclock);
|
||||
|
||||
return div;
|
||||
}
|
||||
|
||||
int platform_dcu_init(struct fb_info *fbinfo,
|
||||
unsigned int xres,
|
||||
unsigned int yres,
|
||||
const char *port,
|
||||
struct fb_videomode *dcu_fb_videomode)
|
||||
{
|
||||
fsl_dcu_init(fbinfo, xres, yres, 32);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2014 Toradex, Inc.
|
||||
*
|
||||
* Refer doc/README.imximage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
#include <asm/mach-imx/imximage.cfg>
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/* Boot Offset 0x400, valid for both SD and NAND boot */
|
||||
BOOT_OFFSET FLASH_OFFSET_STANDARD
|
||||
@@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
# Copyright (c) 2016 Toradex, Inc.
|
||||
|
||||
menuconfig TDX_CFG_BLOCK
|
||||
bool "Enable Toradex config block support"
|
||||
select OF_BOARD_SETUP
|
||||
help
|
||||
The Toradex config block stored production data on the on-module
|
||||
flash device (NAND, NOR or eMMC). The area is normally preserved by
|
||||
software and contains the serial number (out of which the MAC
|
||||
address is generated) and the exact module type.
|
||||
|
||||
# Helper config to determine the correct default location of the cfg block
|
||||
config TDX_HAVE_MMC
|
||||
bool
|
||||
|
||||
config TDX_HAVE_NAND
|
||||
bool
|
||||
|
||||
config TDX_HAVE_NOR
|
||||
bool
|
||||
|
||||
if TDX_CFG_BLOCK
|
||||
|
||||
config TDX_CFG_BLOCK_IS_IN_MMC
|
||||
bool
|
||||
depends on TDX_HAVE_MMC
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_IS_IN_NAND
|
||||
bool
|
||||
depends on TDX_HAVE_NAND
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_IS_IN_NOR
|
||||
bool
|
||||
depends on TDX_HAVE_NOR
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_DEV
|
||||
int "Toradex config block eMMC device ID"
|
||||
depends on TDX_CFG_BLOCK_IS_IN_MMC
|
||||
|
||||
config TDX_CFG_BLOCK_PART
|
||||
int "Toradex config block eMMC partition ID"
|
||||
depends on TDX_CFG_BLOCK_IS_IN_MMC
|
||||
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
int "Toradex config block offset"
|
||||
help
|
||||
Specify the byte offset of the Toradex config block within the flash
|
||||
device the config block is stored on.
|
||||
|
||||
config TDX_CFG_BLOCK_OFFSET2
|
||||
int "Toradex config block offset, second instance"
|
||||
default 0
|
||||
help
|
||||
Specify the byte offset of the 2nd instance of the Toradex config block
|
||||
within the flash device the config block is stored on.
|
||||
Set to 0 on modules which have no 2nd instance.
|
||||
|
||||
config TDX_CFG_BLOCK_2ND_ETHADDR
|
||||
bool "Set the second Ethernet address"
|
||||
help
|
||||
For each serial number two Ethernet addresses are available for dual
|
||||
Ethernet carrier boards. This options enables the code to set the
|
||||
second Ethernet address as environment variable (eth1addr).
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,11 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
# Copyright (c) 2016 Toradex, Inc.
|
||||
|
||||
# Common for all Toradex modules
|
||||
ifeq ($(CONFIG_SPL_BUILD),y)
|
||||
# Necessary to create built-in.o
|
||||
obj- := __dummy__.o
|
||||
else
|
||||
obj-$(CONFIG_TDX_CFG_BLOCK) += tdx-cfg-block.o
|
||||
obj-y += tdx-common.o
|
||||
endif
|
||||
@@ -0,0 +1,639 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2016-2019 Toradex, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "tdx-cfg-block.h"
|
||||
|
||||
#if defined(CONFIG_TARGET_APALIS_IMX6) || \
|
||||
defined(CONFIG_TARGET_APALIS_IMX8) || \
|
||||
defined(CONFIG_TARGET_COLIBRI_IMX6) || \
|
||||
defined(CONFIG_TARGET_COLIBRI_IMX8X)
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#else
|
||||
#define is_cpu_type(cpu) (0)
|
||||
#endif
|
||||
#if defined(CONFIG_CPU_PXA27X)
|
||||
#include <asm/arch-pxa/pxa.h>
|
||||
#else
|
||||
#define cpu_is_pxa27x(cpu) (0)
|
||||
#endif
|
||||
#include <cli.h>
|
||||
#include <console.h>
|
||||
#include <env.h>
|
||||
#include <flash.h>
|
||||
#include <malloc.h>
|
||||
#include <mmc.h>
|
||||
#include <nand.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define TAG_VALID 0xcf01
|
||||
#define TAG_MAC 0x0000
|
||||
#define TAG_HW 0x0008
|
||||
#define TAG_INVALID 0xffff
|
||||
|
||||
#define TAG_FLAG_VALID 0x1
|
||||
|
||||
#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
|
||||
#define TDX_CFG_BLOCK_MAX_SIZE 512
|
||||
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
|
||||
#define TDX_CFG_BLOCK_MAX_SIZE 64
|
||||
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
|
||||
#define TDX_CFG_BLOCK_MAX_SIZE 64
|
||||
#else
|
||||
#error Toradex config block location not set
|
||||
#endif
|
||||
|
||||
struct toradex_tag {
|
||||
u32 len:14;
|
||||
u32 flags:2;
|
||||
u32 id:16;
|
||||
};
|
||||
|
||||
bool valid_cfgblock;
|
||||
struct toradex_hw tdx_hw_tag;
|
||||
struct toradex_eth_addr tdx_eth_addr;
|
||||
u32 tdx_serial;
|
||||
|
||||
const char * const toradex_modules[] = {
|
||||
[0] = "UNKNOWN MODULE",
|
||||
[1] = "Colibri PXA270 312MHz",
|
||||
[2] = "Colibri PXA270 520MHz",
|
||||
[3] = "Colibri PXA320 806MHz",
|
||||
[4] = "Colibri PXA300 208MHz",
|
||||
[5] = "Colibri PXA310 624MHz",
|
||||
[6] = "Colibri PXA320 806MHz IT",
|
||||
[7] = "Colibri PXA300 208MHz XT",
|
||||
[8] = "Colibri PXA270 312MHz",
|
||||
[9] = "Colibri PXA270 520MHz",
|
||||
[10] = "Colibri VF50 128MB", /* not currently on sale */
|
||||
[11] = "Colibri VF61 256MB",
|
||||
[12] = "Colibri VF61 256MB IT",
|
||||
[13] = "Colibri VF50 128MB IT",
|
||||
[14] = "Colibri iMX6 Solo 256MB",
|
||||
[15] = "Colibri iMX6 DualLite 512MB",
|
||||
[16] = "Colibri iMX6 Solo 256MB IT",
|
||||
[17] = "Colibri iMX6 DualLite 512MB IT",
|
||||
[18] = "UNKNOWN MODULE",
|
||||
[19] = "UNKNOWN MODULE",
|
||||
[20] = "Colibri T20 256MB",
|
||||
[21] = "Colibri T20 512MB",
|
||||
[22] = "Colibri T20 512MB IT",
|
||||
[23] = "Colibri T30 1GB",
|
||||
[24] = "Colibri T20 256MB IT",
|
||||
[25] = "Apalis T30 2GB",
|
||||
[26] = "Apalis T30 1GB",
|
||||
[27] = "Apalis iMX6 Quad 1GB",
|
||||
[28] = "Apalis iMX6 Quad 2GB IT",
|
||||
[29] = "Apalis iMX6 Dual 512MB",
|
||||
[30] = "Colibri T30 1GB IT",
|
||||
[31] = "Apalis T30 1GB IT",
|
||||
[32] = "Colibri iMX7 Solo 256MB",
|
||||
[33] = "Colibri iMX7 Dual 512MB",
|
||||
[34] = "Apalis TK1 2GB",
|
||||
[35] = "Apalis iMX6 Dual 1GB IT",
|
||||
[36] = "Colibri iMX6ULL 256MB",
|
||||
[37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT",
|
||||
[38] = "Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT",
|
||||
[39] = "Colibri iMX7 Dual 1GB (eMMC)",
|
||||
[40] = "Colibri iMX6ULL 512MB Wi-Fi / BT IT",
|
||||
[41] = "Colibri iMX7 Dual 512MB EPDC",
|
||||
[42] = "Apalis TK1 4GB",
|
||||
[43] = "Colibri T20 512MB IT SETEK",
|
||||
[44] = "Colibri iMX6ULL 512MB IT",
|
||||
[45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth",
|
||||
[46] = "Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT",
|
||||
[47] = "Apalis iMX8 QuadMax 4GB IT",
|
||||
[48] = "Apalis iMX8 QuadPlus 2GB Wi-Fi / BT",
|
||||
[49] = "Apalis iMX8 QuadPlus 2GB",
|
||||
[50] = "Colibri iMX8 QuadXPlus 2GB IT",
|
||||
[51] = "Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth",
|
||||
[52] = "Colibri iMX8 DualX 1GB",
|
||||
};
|
||||
|
||||
#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
|
||||
static int tdx_cfg_block_mmc_storage(u8 *config_block, int write)
|
||||
{
|
||||
struct mmc *mmc;
|
||||
int dev = CONFIG_TDX_CFG_BLOCK_DEV;
|
||||
int offset = CONFIG_TDX_CFG_BLOCK_OFFSET;
|
||||
uint part = CONFIG_TDX_CFG_BLOCK_PART;
|
||||
uint blk_start;
|
||||
int ret = 0;
|
||||
|
||||
/* Read production parameter config block from eMMC */
|
||||
mmc = find_mmc_device(dev);
|
||||
if (!mmc) {
|
||||
puts("No MMC card found\n");
|
||||
ret = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
if (mmc_init(mmc)) {
|
||||
puts("MMC init failed\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
if (part != mmc_get_blk_desc(mmc)->hwpart) {
|
||||
if (blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part)) {
|
||||
puts("MMC partition switch failed\n");
|
||||
ret = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
if (offset < 0)
|
||||
offset += mmc->capacity;
|
||||
blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
|
||||
|
||||
if (!write) {
|
||||
/* Careful reads a whole block of 512 bytes into config_block */
|
||||
if (blk_dread(mmc_get_blk_desc(mmc), blk_start, 1,
|
||||
(unsigned char *)config_block) != 1) {
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
} else {
|
||||
/* Just writing one 512 byte block */
|
||||
if (blk_dwrite(mmc_get_blk_desc(mmc), blk_start, 1,
|
||||
(unsigned char *)config_block) != 1) {
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
/* Switch back to regular eMMC user partition */
|
||||
blk_select_hwpart_devnum(IF_TYPE_MMC, 0, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_NAND
|
||||
static int read_tdx_cfg_block_from_nand(unsigned char *config_block)
|
||||
{
|
||||
size_t size = TDX_CFG_BLOCK_MAX_SIZE;
|
||||
struct mtd_info *mtd = get_nand_dev_by_index(0);
|
||||
|
||||
if (!mtd)
|
||||
return -ENODEV;
|
||||
|
||||
/* Read production parameter config block from NAND page */
|
||||
return nand_read_skip_bad(mtd, CONFIG_TDX_CFG_BLOCK_OFFSET,
|
||||
&size, NULL, TDX_CFG_BLOCK_MAX_SIZE,
|
||||
config_block);
|
||||
}
|
||||
|
||||
static int write_tdx_cfg_block_to_nand(unsigned char *config_block)
|
||||
{
|
||||
size_t size = TDX_CFG_BLOCK_MAX_SIZE;
|
||||
|
||||
/* Write production parameter config block to NAND page */
|
||||
return nand_write_skip_bad(get_nand_dev_by_index(0),
|
||||
CONFIG_TDX_CFG_BLOCK_OFFSET,
|
||||
&size, NULL, TDX_CFG_BLOCK_MAX_SIZE,
|
||||
config_block, WITH_WR_VERIFY);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_NOR
|
||||
static int read_tdx_cfg_block_from_nor(unsigned char *config_block)
|
||||
{
|
||||
/* Read production parameter config block from NOR flash */
|
||||
memcpy(config_block, (void *)CONFIG_TDX_CFG_BLOCK_OFFSET,
|
||||
TDX_CFG_BLOCK_MAX_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int write_tdx_cfg_block_to_nor(unsigned char *config_block)
|
||||
{
|
||||
/* Write production parameter config block to NOR flash */
|
||||
return flash_write((void *)config_block, CONFIG_TDX_CFG_BLOCK_OFFSET,
|
||||
TDX_CFG_BLOCK_MAX_SIZE);
|
||||
}
|
||||
#endif
|
||||
|
||||
int read_tdx_cfg_block(void)
|
||||
{
|
||||
int ret = 0;
|
||||
u8 *config_block = NULL;
|
||||
struct toradex_tag *tag;
|
||||
size_t size = TDX_CFG_BLOCK_MAX_SIZE;
|
||||
int offset;
|
||||
|
||||
/* Allocate RAM area for config block */
|
||||
config_block = memalign(ARCH_DMA_MINALIGN, size);
|
||||
if (!config_block) {
|
||||
printf("Not enough malloc space available!\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
memset(config_block, 0, size);
|
||||
|
||||
#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
|
||||
ret = tdx_cfg_block_mmc_storage(config_block, 0);
|
||||
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
|
||||
ret = read_tdx_cfg_block_from_nand(config_block);
|
||||
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
|
||||
ret = read_tdx_cfg_block_from_nor(config_block);
|
||||
#else
|
||||
ret = -EINVAL;
|
||||
#endif
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/* Expect a valid tag first */
|
||||
tag = (struct toradex_tag *)config_block;
|
||||
if (tag->flags != TAG_FLAG_VALID || tag->id != TAG_VALID) {
|
||||
valid_cfgblock = false;
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
valid_cfgblock = true;
|
||||
offset = 4;
|
||||
|
||||
while (offset < TDX_CFG_BLOCK_MAX_SIZE) {
|
||||
tag = (struct toradex_tag *)(config_block + offset);
|
||||
offset += 4;
|
||||
if (tag->id == TAG_INVALID)
|
||||
break;
|
||||
|
||||
if (tag->flags == TAG_FLAG_VALID) {
|
||||
switch (tag->id) {
|
||||
case TAG_MAC:
|
||||
memcpy(&tdx_eth_addr, config_block + offset,
|
||||
6);
|
||||
|
||||
/* NIC part of MAC address is serial number */
|
||||
tdx_serial = ntohl(tdx_eth_addr.nic) >> 8;
|
||||
break;
|
||||
case TAG_HW:
|
||||
memcpy(&tdx_hw_tag, config_block + offset, 8);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get to next tag according to current tags length */
|
||||
offset += tag->len * 4;
|
||||
}
|
||||
|
||||
/* Cap product id to avoid issues with a yet unknown one */
|
||||
if (tdx_hw_tag.prodid >= (sizeof(toradex_modules) /
|
||||
sizeof(toradex_modules[0])))
|
||||
tdx_hw_tag.prodid = 0;
|
||||
|
||||
out:
|
||||
free(config_block);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int get_cfgblock_interactive(void)
|
||||
{
|
||||
char message[CONFIG_SYS_CBSIZE];
|
||||
char *soc;
|
||||
char it = 'n';
|
||||
char wb = 'n';
|
||||
int len;
|
||||
|
||||
/* Unknown module by default */
|
||||
tdx_hw_tag.prodid = 0;
|
||||
|
||||
if (cpu_is_pxa27x())
|
||||
sprintf(message, "Is the module the 312 MHz version? [y/N] ");
|
||||
else
|
||||
sprintf(message, "Is the module an IT version? [y/N] ");
|
||||
len = cli_readline(message);
|
||||
it = console_buffer[0];
|
||||
|
||||
#if defined(CONFIG_TARGET_APALIS_IMX8) || \
|
||||
defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \
|
||||
defined(CONFIG_TARGET_COLIBRI_IMX8X)
|
||||
sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] ");
|
||||
len = cli_readline(message);
|
||||
wb = console_buffer[0];
|
||||
#endif
|
||||
|
||||
soc = env_get("soc");
|
||||
if (!strcmp("mx6", soc)) {
|
||||
#ifdef CONFIG_TARGET_APALIS_IMX6
|
||||
if (it == 'y' || it == 'Y') {
|
||||
if (is_cpu_type(MXC_CPU_MX6Q))
|
||||
tdx_hw_tag.prodid = APALIS_IMX6Q_IT;
|
||||
else
|
||||
tdx_hw_tag.prodid = APALIS_IMX6D_IT;
|
||||
} else {
|
||||
if (is_cpu_type(MXC_CPU_MX6Q))
|
||||
tdx_hw_tag.prodid = APALIS_IMX6Q;
|
||||
else
|
||||
tdx_hw_tag.prodid = APALIS_IMX6D;
|
||||
}
|
||||
#elif CONFIG_TARGET_COLIBRI_IMX6
|
||||
if (it == 'y' || it == 'Y') {
|
||||
if (is_cpu_type(MXC_CPU_MX6DL))
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT;
|
||||
else if (is_cpu_type(MXC_CPU_MX6SOLO))
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX6S_IT;
|
||||
} else {
|
||||
if (is_cpu_type(MXC_CPU_MX6DL))
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX6DL;
|
||||
else if (is_cpu_type(MXC_CPU_MX6SOLO))
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX6S;
|
||||
}
|
||||
#elif CONFIG_TARGET_COLIBRI_IMX6ULL
|
||||
if (it == 'y' || it == 'Y') {
|
||||
if (wb == 'y' || wb == 'Y')
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT_IT;
|
||||
else
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
|
||||
} else {
|
||||
if (wb == 'y' || wb == 'Y')
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT;
|
||||
else
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX6ULL;
|
||||
}
|
||||
#endif
|
||||
} else if (!strcmp("imx7d", soc))
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX7D;
|
||||
else if (!strcmp("imx7s", soc))
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX7S;
|
||||
else if (is_cpu_type(MXC_CPU_IMX8QM)) {
|
||||
if (it == 'y' || it == 'Y') {
|
||||
if (wb == 'y' || wb == 'Y')
|
||||
tdx_hw_tag.prodid = APALIS_IMX8QM_WIFI_BT_IT;
|
||||
else
|
||||
tdx_hw_tag.prodid = APALIS_IMX8QM_IT;
|
||||
} else {
|
||||
if (wb == 'y' || wb == 'Y')
|
||||
tdx_hw_tag.prodid = APALIS_IMX8QP_WIFI_BT;
|
||||
else
|
||||
tdx_hw_tag.prodid = APALIS_IMX8QP;
|
||||
}
|
||||
} else if (is_cpu_type(MXC_CPU_IMX8QXP)) {
|
||||
if (it == 'y' || it == 'Y') {
|
||||
if (wb == 'y' || wb == 'Y')
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT;
|
||||
else
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX8QXP_IT;
|
||||
} else {
|
||||
if (wb == 'y' || wb == 'Y')
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX8DX_WIFI_BT;
|
||||
else
|
||||
tdx_hw_tag.prodid = COLIBRI_IMX8DX;
|
||||
}
|
||||
} else if (!strcmp("tegra20", soc)) {
|
||||
if (it == 'y' || it == 'Y')
|
||||
if (gd->ram_size == 0x10000000)
|
||||
tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT;
|
||||
else
|
||||
tdx_hw_tag.prodid = COLIBRI_T20_512MB_IT;
|
||||
else
|
||||
if (gd->ram_size == 0x10000000)
|
||||
tdx_hw_tag.prodid = COLIBRI_T20_256MB;
|
||||
else
|
||||
tdx_hw_tag.prodid = COLIBRI_T20_512MB;
|
||||
} else if (cpu_is_pxa27x()) {
|
||||
if (it == 'y' || it == 'Y')
|
||||
tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ;
|
||||
else
|
||||
tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ;
|
||||
}
|
||||
#ifdef CONFIG_MACH_TYPE
|
||||
else if (!strcmp("tegra30", soc)) {
|
||||
if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) {
|
||||
if (it == 'y' || it == 'Y')
|
||||
tdx_hw_tag.prodid = APALIS_T30_IT;
|
||||
else
|
||||
if (gd->ram_size == 0x40000000)
|
||||
tdx_hw_tag.prodid = APALIS_T30_1GB;
|
||||
else
|
||||
tdx_hw_tag.prodid = APALIS_T30_2GB;
|
||||
} else {
|
||||
if (it == 'y' || it == 'Y')
|
||||
tdx_hw_tag.prodid = COLIBRI_T30_IT;
|
||||
else
|
||||
tdx_hw_tag.prodid = COLIBRI_T30;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_MACH_TYPE */
|
||||
else if (!strcmp("tegra124", soc)) {
|
||||
tdx_hw_tag.prodid = APALIS_TK1_2GB;
|
||||
} else if (!strcmp("vf500", soc)) {
|
||||
if (it == 'y' || it == 'Y')
|
||||
tdx_hw_tag.prodid = COLIBRI_VF50_IT;
|
||||
else
|
||||
tdx_hw_tag.prodid = COLIBRI_VF50;
|
||||
} else if (!strcmp("vf610", soc)) {
|
||||
if (it == 'y' || it == 'Y')
|
||||
tdx_hw_tag.prodid = COLIBRI_VF61_IT;
|
||||
else
|
||||
tdx_hw_tag.prodid = COLIBRI_VF61;
|
||||
}
|
||||
|
||||
if (!tdx_hw_tag.prodid) {
|
||||
printf("Module type not detectable due to unknown SoC\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
while (len < 4) {
|
||||
sprintf(message, "Enter the module version (e.g. V1.1B): V");
|
||||
len = cli_readline(message);
|
||||
}
|
||||
|
||||
tdx_hw_tag.ver_major = console_buffer[0] - '0';
|
||||
tdx_hw_tag.ver_minor = console_buffer[2] - '0';
|
||||
tdx_hw_tag.ver_assembly = console_buffer[3] - 'A';
|
||||
|
||||
if (cpu_is_pxa27x() && tdx_hw_tag.ver_major == 1)
|
||||
tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ -
|
||||
COLIBRI_PXA270_V1_312MHZ);
|
||||
|
||||
while (len < 8) {
|
||||
sprintf(message, "Enter module serial number: ");
|
||||
len = cli_readline(message);
|
||||
}
|
||||
|
||||
tdx_serial = simple_strtoul(console_buffer, NULL, 10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_cfgblock_barcode(char *barcode)
|
||||
{
|
||||
if (strlen(barcode) < 16) {
|
||||
printf("Argument too short, barcode is 16 chars long\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Get hardware information from the first 8 digits */
|
||||
tdx_hw_tag.ver_major = barcode[4] - '0';
|
||||
tdx_hw_tag.ver_minor = barcode[5] - '0';
|
||||
tdx_hw_tag.ver_assembly = barcode[7] - '0';
|
||||
|
||||
barcode[4] = '\0';
|
||||
tdx_hw_tag.prodid = simple_strtoul(barcode, NULL, 10);
|
||||
|
||||
/* Parse second part of the barcode (serial number */
|
||||
barcode += 8;
|
||||
tdx_serial = simple_strtoul(barcode, NULL, 10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
u8 *config_block;
|
||||
struct toradex_tag *tag;
|
||||
size_t size = TDX_CFG_BLOCK_MAX_SIZE;
|
||||
int offset = 0;
|
||||
int ret = CMD_RET_SUCCESS;
|
||||
int err;
|
||||
int force_overwrite = 0;
|
||||
|
||||
/* Allocate RAM area for config block */
|
||||
config_block = memalign(ARCH_DMA_MINALIGN, size);
|
||||
if (!config_block) {
|
||||
printf("Not enough malloc space available!\n");
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
memset(config_block, 0xff, size);
|
||||
|
||||
if (argc >= 3) {
|
||||
if (argv[2][0] == '-' && argv[2][1] == 'y')
|
||||
force_overwrite = 1;
|
||||
}
|
||||
|
||||
read_tdx_cfg_block();
|
||||
if (valid_cfgblock) {
|
||||
#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
|
||||
/*
|
||||
* On NAND devices, recreation is only allowed if the page is
|
||||
* empty (config block invalid...)
|
||||
*/
|
||||
printf("NAND erase block %d need to be erased before creating a Toradex config block\n",
|
||||
CONFIG_TDX_CFG_BLOCK_OFFSET /
|
||||
get_nand_dev_by_index(0)->erasesize);
|
||||
goto out;
|
||||
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
|
||||
/*
|
||||
* On NOR devices, recreation is only allowed if the sector is
|
||||
* empty and write protection is off (config block invalid...)
|
||||
*/
|
||||
printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n",
|
||||
CONFIG_TDX_CFG_BLOCK_OFFSET);
|
||||
goto out;
|
||||
#else
|
||||
if (!force_overwrite) {
|
||||
char message[CONFIG_SYS_CBSIZE];
|
||||
|
||||
sprintf(message,
|
||||
"A valid Toradex config block is present, still recreate? [y/N] ");
|
||||
|
||||
if (!cli_readline(message))
|
||||
goto out;
|
||||
|
||||
if (console_buffer[0] != 'y' &&
|
||||
console_buffer[0] != 'Y')
|
||||
goto out;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Parse new Toradex config block data... */
|
||||
if (argc < 3 || (force_overwrite && argc < 4)) {
|
||||
err = get_cfgblock_interactive();
|
||||
} else {
|
||||
if (force_overwrite)
|
||||
err = get_cfgblock_barcode(argv[3]);
|
||||
else
|
||||
err = get_cfgblock_barcode(argv[2]);
|
||||
}
|
||||
if (err) {
|
||||
ret = CMD_RET_FAILURE;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Convert serial number to MAC address (the storage format) */
|
||||
tdx_eth_addr.oui = htonl(0x00142dUL << 8);
|
||||
tdx_eth_addr.nic = htonl(tdx_serial << 8);
|
||||
|
||||
/* Valid Tag */
|
||||
tag = (struct toradex_tag *)config_block;
|
||||
tag->id = TAG_VALID;
|
||||
tag->flags = TAG_FLAG_VALID;
|
||||
tag->len = 0;
|
||||
offset += 4;
|
||||
|
||||
/* Product Tag */
|
||||
tag = (struct toradex_tag *)(config_block + offset);
|
||||
tag->id = TAG_HW;
|
||||
tag->flags = TAG_FLAG_VALID;
|
||||
tag->len = 2;
|
||||
offset += 4;
|
||||
|
||||
memcpy(config_block + offset, &tdx_hw_tag, 8);
|
||||
offset += 8;
|
||||
|
||||
/* MAC Tag */
|
||||
tag = (struct toradex_tag *)(config_block + offset);
|
||||
tag->id = TAG_MAC;
|
||||
tag->flags = TAG_FLAG_VALID;
|
||||
tag->len = 2;
|
||||
offset += 4;
|
||||
|
||||
memcpy(config_block + offset, &tdx_eth_addr, 6);
|
||||
offset += 6;
|
||||
memset(config_block + offset, 0, 32 - offset);
|
||||
|
||||
#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
|
||||
err = tdx_cfg_block_mmc_storage(config_block, 1);
|
||||
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
|
||||
err = write_tdx_cfg_block_to_nand(config_block);
|
||||
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
|
||||
err = write_tdx_cfg_block_to_nor(config_block);
|
||||
#else
|
||||
err = -EINVAL;
|
||||
#endif
|
||||
if (err) {
|
||||
printf("Failed to write Toradex config block: %d\n", ret);
|
||||
ret = CMD_RET_FAILURE;
|
||||
goto out;
|
||||
}
|
||||
|
||||
printf("Toradex config block successfully written\n");
|
||||
|
||||
out:
|
||||
free(config_block);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int do_cfgblock(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (argc < 2)
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
if (!strcmp(argv[1], "create")) {
|
||||
return do_cfgblock_create(cmdtp, flag, argc, argv);
|
||||
} else if (!strcmp(argv[1], "reload")) {
|
||||
ret = read_tdx_cfg_block();
|
||||
if (ret) {
|
||||
printf("Failed to reload Toradex config block: %d\n",
|
||||
ret);
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
return CMD_RET_USAGE;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(cfgblock, 4, 0, do_cfgblock,
|
||||
"Toradex config block handling commands",
|
||||
"create [-y] [barcode] - (Re-)create Toradex config block\n"
|
||||
"cfgblock reload - Reload Toradex config block from flash"
|
||||
);
|
||||
@@ -0,0 +1,86 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2016 Toradex, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _TDX_CFG_BLOCK_H
|
||||
#define _TDX_CFG_BLOCK_H
|
||||
|
||||
#include "tdx-common.h"
|
||||
|
||||
struct toradex_hw {
|
||||
u16 ver_major;
|
||||
u16 ver_minor;
|
||||
u16 ver_assembly;
|
||||
u16 prodid;
|
||||
};
|
||||
|
||||
struct toradex_eth_addr {
|
||||
u32 oui:24;
|
||||
u32 nic:24;
|
||||
} __attribute__((__packed__));
|
||||
|
||||
enum {
|
||||
COLIBRI_PXA270_V1_312MHZ = 1,
|
||||
COLIBRI_PXA270_V1_520MHZ,
|
||||
COLIBRI_PXA320,
|
||||
COLIBRI_PXA300,
|
||||
COLIBRI_PXA310, /* 5 */
|
||||
COLIBRI_PXA320_IT,
|
||||
COLIBRI_PXA300_XT,
|
||||
COLIBRI_PXA270_312MHZ,
|
||||
COLIBRI_PXA270_520MHZ,
|
||||
COLIBRI_VF50, /* 10 */
|
||||
COLIBRI_VF61, /* not currently on sale */
|
||||
COLIBRI_VF61_IT,
|
||||
COLIBRI_VF50_IT,
|
||||
COLIBRI_IMX6S,
|
||||
COLIBRI_IMX6DL, /* 15 */
|
||||
COLIBRI_IMX6S_IT,
|
||||
COLIBRI_IMX6DL_IT,
|
||||
/* 18 */
|
||||
/* 19 */
|
||||
COLIBRI_T20_256MB = 20,
|
||||
COLIBRI_T20_512MB,
|
||||
COLIBRI_T20_512MB_IT,
|
||||
COLIBRI_T30,
|
||||
COLIBRI_T20_256MB_IT,
|
||||
APALIS_T30_2GB, /* 25 */
|
||||
APALIS_T30_1GB,
|
||||
APALIS_IMX6Q,
|
||||
APALIS_IMX6Q_IT,
|
||||
APALIS_IMX6D,
|
||||
COLIBRI_T30_IT, /* 30 */
|
||||
APALIS_T30_IT,
|
||||
COLIBRI_IMX7S,
|
||||
COLIBRI_IMX7D,
|
||||
APALIS_TK1_2GB,
|
||||
APALIS_IMX6D_IT, /* 35 */
|
||||
COLIBRI_IMX6ULL,
|
||||
APALIS_IMX8QM_WIFI_BT_IT,
|
||||
COLIBRI_IMX8QXP_WIFI_BT_IT,
|
||||
COLIBRI_IMX7D_EMMC,
|
||||
COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */
|
||||
COLIBRI_IMX7D_EPDC,
|
||||
APALIS_TK1_4GB, /* not currently on sale */
|
||||
COLIBRI_T20_512MB_IT_SETEK,
|
||||
COLIBRI_IMX6ULL_IT,
|
||||
COLIBRI_IMX6ULL_WIFI_BT, /* 45 */
|
||||
APALIS_IMX8QXP_WIFI_BT_IT,
|
||||
APALIS_IMX8QM_IT,
|
||||
APALIS_IMX8QP_WIFI_BT,
|
||||
APALIS_IMX8QP,
|
||||
COLIBRI_IMX8QXP_IT, /* 50 */
|
||||
COLIBRI_IMX8DX_WIFI_BT,
|
||||
COLIBRI_IMX8DX,
|
||||
};
|
||||
|
||||
extern const char * const toradex_modules[];
|
||||
extern bool valid_cfgblock;
|
||||
extern struct toradex_hw tdx_hw_tag;
|
||||
extern struct toradex_eth_addr tdx_eth_addr;
|
||||
extern u32 tdx_serial;
|
||||
|
||||
int read_tdx_cfg_block(void);
|
||||
|
||||
#endif /* _TDX_CFG_BLOCK_H */
|
||||
@@ -0,0 +1,169 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2016 Toradex, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <g_dnl.h>
|
||||
#include <linux/libfdt.h>
|
||||
|
||||
#include "tdx-cfg-block.h"
|
||||
#include <asm/setup.h>
|
||||
#include "tdx-common.h"
|
||||
|
||||
#define TORADEX_OUI 0x00142dUL
|
||||
|
||||
#ifdef CONFIG_TDX_CFG_BLOCK
|
||||
static char tdx_serial_str[9];
|
||||
static char tdx_board_rev_str[6];
|
||||
|
||||
#ifdef CONFIG_REVISION_TAG
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
/* Check validity */
|
||||
if (!tdx_hw_tag.ver_major)
|
||||
return 0;
|
||||
|
||||
return ((tdx_hw_tag.ver_major & 0xff) << 8) |
|
||||
((tdx_hw_tag.ver_minor & 0xf) << 4) |
|
||||
((tdx_hw_tag.ver_assembly & 0xf) + 0xa);
|
||||
}
|
||||
#endif /* CONFIG_TDX_CFG_BLOCK */
|
||||
|
||||
#ifdef CONFIG_SERIAL_TAG
|
||||
void get_board_serial(struct tag_serialnr *serialnr)
|
||||
{
|
||||
int array[8];
|
||||
unsigned int serial = tdx_serial;
|
||||
int i;
|
||||
|
||||
serialnr->low = 0;
|
||||
serialnr->high = 0;
|
||||
|
||||
/* Check validity */
|
||||
if (serial) {
|
||||
/*
|
||||
* Convert to Linux serial number format (hexadecimal coded
|
||||
* decimal)
|
||||
*/
|
||||
i = 7;
|
||||
while (serial) {
|
||||
array[i--] = serial % 10;
|
||||
serial /= 10;
|
||||
}
|
||||
while (i >= 0)
|
||||
array[i--] = 0;
|
||||
serial = array[0];
|
||||
for (i = 1; i < 8; i++) {
|
||||
serial *= 16;
|
||||
serial += array[i];
|
||||
}
|
||||
|
||||
serialnr->low = serial;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_SERIAL_TAG */
|
||||
|
||||
int show_board_info(void)
|
||||
{
|
||||
unsigned char ethaddr[6];
|
||||
|
||||
if (read_tdx_cfg_block()) {
|
||||
printf("MISSING TORADEX CONFIG BLOCK\n");
|
||||
tdx_eth_addr.oui = htonl(TORADEX_OUI << 8);
|
||||
tdx_eth_addr.nic = htonl(tdx_serial << 8);
|
||||
checkboard();
|
||||
} else {
|
||||
sprintf(tdx_serial_str, "%08u", tdx_serial);
|
||||
sprintf(tdx_board_rev_str, "V%1d.%1d%c",
|
||||
tdx_hw_tag.ver_major,
|
||||
tdx_hw_tag.ver_minor,
|
||||
(char)tdx_hw_tag.ver_assembly + 'A');
|
||||
|
||||
env_set("serial#", tdx_serial_str);
|
||||
|
||||
printf("Model: Toradex %s %s, Serial# %s\n",
|
||||
toradex_modules[tdx_hw_tag.prodid],
|
||||
tdx_board_rev_str,
|
||||
tdx_serial_str);
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if environment contains a valid MAC address,
|
||||
* set the one from config block if not
|
||||
*/
|
||||
if (!eth_env_get_enetaddr("ethaddr", ethaddr))
|
||||
eth_env_set_enetaddr("ethaddr", (u8 *)&tdx_eth_addr);
|
||||
|
||||
#ifdef CONFIG_TDX_CFG_BLOCK_2ND_ETHADDR
|
||||
if (!eth_env_get_enetaddr("eth1addr", ethaddr)) {
|
||||
/*
|
||||
* Secondary MAC address is allocated from block
|
||||
* 0x100000 higher then the first MAC address
|
||||
*/
|
||||
memcpy(ethaddr, &tdx_eth_addr, 6);
|
||||
ethaddr[3] += 0x10;
|
||||
eth_env_set_enetaddr("eth1addr", ethaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_GADGET_DOWNLOAD
|
||||
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
|
||||
{
|
||||
unsigned short usb_pid;
|
||||
|
||||
usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + tdx_hw_tag.prodid;
|
||||
put_unaligned(usb_pid, &dev->idProduct);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
int ft_common_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
if (tdx_serial) {
|
||||
fdt_setprop(blob, 0, "serial-number", tdx_serial_str,
|
||||
strlen(tdx_serial_str) + 1);
|
||||
}
|
||||
|
||||
if (tdx_hw_tag.ver_major) {
|
||||
char prod_id[5];
|
||||
|
||||
sprintf(prod_id, "%04u", tdx_hw_tag.prodid);
|
||||
fdt_setprop(blob, 0, "toradex,product-id", prod_id, 5);
|
||||
|
||||
fdt_setprop(blob, 0, "toradex,board-rev", tdx_board_rev_str,
|
||||
strlen(tdx_board_rev_str) + 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#else /* CONFIG_TDX_CFG_BLOCK */
|
||||
|
||||
#ifdef CONFIG_REVISION_TAG
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_REVISION_TAG */
|
||||
|
||||
#ifdef CONFIG_SERIAL_TAG
|
||||
u32 get_board_serial(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SERIAL_TAG */
|
||||
|
||||
int ft_common_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_TDX_CFG_BLOCK */
|
||||
@@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2016 Toradex, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _TDX_COMMON_H
|
||||
#define _TDX_COMMON_H
|
||||
|
||||
#define TORADEX_USB_PRODUCT_NUM_OFFSET 0x4000
|
||||
#define TDX_USB_VID 0x1B67
|
||||
|
||||
int ft_common_board_setup(void *blob, bd_t *bd);
|
||||
|
||||
#endif /* _TDX_COMMON_H */
|
||||
Reference in New Issue
Block a user