GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,38 @@
|
||||
if TARGET_APALIS_TK1
|
||||
|
||||
config SYS_BOARD
|
||||
default "apalis-tk1"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "apalis-tk1"
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_HAVE_MMC
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_DEV
|
||||
default "0"
|
||||
|
||||
config TDX_CFG_BLOCK_PART
|
||||
default "1"
|
||||
|
||||
# Toradex config block in eMMC, at the end of 1st "boot sector"
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "-512"
|
||||
|
||||
config APALIS_TK1_PCIE_EVALBOARD_INIT
|
||||
bool "Apalis Evaluation Board PCIe Initialisation"
|
||||
help
|
||||
Bring up the Apalis PCIe port with the PCIe switch as found on the
|
||||
Apalis Evaluation board. Note that by default the PCIe port is also
|
||||
left disabled in the device tree which needs changing as well for this
|
||||
to actually work.
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,7 @@
|
||||
Apalis TK1
|
||||
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
||||
S: Maintained
|
||||
F: board/toradex/apalis-tk1/
|
||||
F: include/configs/apalis-tk1.h
|
||||
F: configs/apalis-tk1_defconfig
|
||||
F: arch/arm/dts/tegra124-apalis.dtb
|
||||
@@ -0,0 +1,5 @@
|
||||
# Copyright (c) 2016 Toradex, Inc.
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
obj-y += as3722_init.o
|
||||
obj-y += apalis-tk1.o
|
||||
@@ -0,0 +1,298 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2016-2018 Toradex, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <asm/arch-tegra/ap.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <env_internal.h>
|
||||
#include <pci_tegra.h>
|
||||
#include <power/as3722.h>
|
||||
#include <power/pmic.h>
|
||||
|
||||
#include "../common/tdx-common.h"
|
||||
#include "pinmux-config-apalis-tk1.h"
|
||||
|
||||
#define LAN_DEV_OFF_N TEGRA_GPIO(O, 6)
|
||||
#define LAN_RESET_N TEGRA_GPIO(S, 2)
|
||||
#define FAN_EN TEGRA_GPIO(DD, 2)
|
||||
#define LAN_WAKE_N TEGRA_GPIO(O, 5)
|
||||
#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
|
||||
#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
|
||||
#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
|
||||
#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
|
||||
#define VCC_USBH TEGRA_GPIO(T, 6)
|
||||
#define VCC_USBH_V1_0 TEGRA_GPIO(N, 5)
|
||||
#define VCC_USBO1 TEGRA_GPIO(T, 5)
|
||||
#define VCC_USBO1_V1_0 TEGRA_GPIO(N, 4)
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
|
||||
NVBOOTTYPE_RECOVERY)
|
||||
printf("USB recovery mode\n");
|
||||
|
||||
/* PCB Version Indication: V1.2 and later have GPIO_PV0 wired to GND */
|
||||
gpio_request(TEGRA_GPIO(V, 0), "PCB Version Indication");
|
||||
gpio_direction_input(TEGRA_GPIO(V, 0));
|
||||
if (gpio_get_value(TEGRA_GPIO(V, 0))) {
|
||||
/*
|
||||
* if using the default device tree for new V1.2 and later HW,
|
||||
* use version for older V1.0 and V1.1 HW
|
||||
*/
|
||||
char *fdt_env = env_get("fdt_module");
|
||||
|
||||
if (fdt_env && !strcmp(FDT_MODULE, fdt_env)) {
|
||||
env_set("fdt_module", FDT_MODULE_V1_0);
|
||||
printf("patching fdt_module to " FDT_MODULE_V1_0
|
||||
" for older V1.0 and V1.1 HW\n");
|
||||
#ifndef CONFIG_ENV_IS_NOWHERE
|
||||
env_save();
|
||||
#endif
|
||||
}
|
||||
|
||||
/* activate USB power enable GPIOs */
|
||||
gpio_request(VCC_USBH_V1_0, "VCC_USBH");
|
||||
gpio_direction_output(VCC_USBH_V1_0, 1);
|
||||
gpio_request(VCC_USBO1_V1_0, "VCC_USBO1");
|
||||
gpio_direction_output(VCC_USBO1_V1_0, 1);
|
||||
} else {
|
||||
/* activate USB power enable GPIOs */
|
||||
gpio_request(VCC_USBH, "VCC_USBH");
|
||||
gpio_direction_output(VCC_USBH, 1);
|
||||
gpio_request(VCC_USBO1, "VCC_USBO1");
|
||||
gpio_direction_output(VCC_USBO1, 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Model: Toradex Apalis TK1 2GB\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
return ft_common_board_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_clear_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(apalis_tk1_gpio_inits,
|
||||
ARRAY_SIZE(apalis_tk1_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(apalis_tk1_pingrps,
|
||||
ARRAY_SIZE(apalis_tk1_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
|
||||
ARRAY_SIZE(apalis_tk1_drvgrps));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI_TEGRA
|
||||
/* TODO: Convert to driver model */
|
||||
static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (sd > 6)
|
||||
return -EINVAL;
|
||||
|
||||
err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
|
||||
if (err) {
|
||||
pr_err("failed to update SD control register: %d", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* TODO: Convert to driver model */
|
||||
static int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
|
||||
{
|
||||
int err;
|
||||
u8 ctrl_reg = AS3722_LDO_CONTROL0;
|
||||
|
||||
if (ldo > 11)
|
||||
return -EINVAL;
|
||||
|
||||
if (ldo > 7) {
|
||||
ctrl_reg = AS3722_LDO_CONTROL1;
|
||||
ldo -= 8;
|
||||
}
|
||||
|
||||
err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo);
|
||||
if (err) {
|
||||
pr_err("failed to update LDO control register: %d", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_pcie_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_PMIC,
|
||||
DM_GET_DRIVER(pmic_as3722), &dev);
|
||||
if (ret) {
|
||||
pr_err("failed to find AS3722 PMIC: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = as3722_sd_enable(dev, 4);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to enable SD4: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = as3722_sd_set_voltage(dev, 4, 0x24);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to set SD4 voltage: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N");
|
||||
gpio_request(LAN_RESET_N, "LAN_RESET_N");
|
||||
gpio_request(LAN_WAKE_N, "LAN_WAKE_N");
|
||||
|
||||
#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
|
||||
gpio_request(PEX_PERST_N, "PEX_PERST_N");
|
||||
gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
|
||||
#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
|
||||
{
|
||||
int index = tegra_pcie_port_index_of_port(port);
|
||||
|
||||
if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_PMIC,
|
||||
DM_GET_DRIVER(pmic_as3722),
|
||||
&dev);
|
||||
if (ret) {
|
||||
debug("%s: Failed to find PMIC\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Reset I210 Gigabit Ethernet Controller */
|
||||
gpio_direction_output(LAN_RESET_N, 0);
|
||||
|
||||
/*
|
||||
* Make sure we don't get any back feeding from DEV_OFF_N resp.
|
||||
* LAN_WAKE_N
|
||||
*/
|
||||
gpio_direction_output(LAN_DEV_OFF_N, 0);
|
||||
gpio_direction_output(LAN_WAKE_N, 0);
|
||||
|
||||
/* Make sure LDO9 and LDO10 are initially enabled @ 0V */
|
||||
ret = as3722_ldo_enable(dev, 9);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to enable LDO9: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
ret = as3722_ldo_enable(dev, 10);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to enable LDO10: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
ret = as3722_ldo_set_voltage(dev, 9, 0x80);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to set LDO9 voltage: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
ret = as3722_ldo_set_voltage(dev, 10, 0x80);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to set LDO10 voltage: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Make sure controller gets enabled by disabling DEV_OFF_N */
|
||||
gpio_set_value(LAN_DEV_OFF_N, 1);
|
||||
|
||||
/*
|
||||
* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype
|
||||
* V1.0A and sample V1.0B and newer modules
|
||||
*/
|
||||
ret = as3722_ldo_set_voltage(dev, 9, 0xff);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to set LDO9 voltage: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
ret = as3722_ldo_set_voltage(dev, 10, 0xff);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to set LDO10 voltage: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Must be asserted for 100 ms after power and clocks are stable
|
||||
*/
|
||||
mdelay(100);
|
||||
|
||||
gpio_set_value(LAN_RESET_N, 1);
|
||||
} else if (index == 0) { /* Apalis PCIe */
|
||||
#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
|
||||
/*
|
||||
* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis
|
||||
* Evaluation Board
|
||||
*/
|
||||
gpio_direction_output(PEX_PERST_N, 0);
|
||||
gpio_direction_output(RESET_MOCI_CTRL, 0);
|
||||
|
||||
/*
|
||||
* Must be asserted for 100 ms after power and clocks are stable
|
||||
*/
|
||||
mdelay(100);
|
||||
|
||||
gpio_set_value(PEX_PERST_N, 1);
|
||||
/*
|
||||
* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed
|
||||
* Until 900 us After PEX_PERST# De-assertion
|
||||
*/
|
||||
mdelay(1);
|
||||
gpio_set_value(RESET_MOCI_CTRL, 1);
|
||||
#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_PCI_TEGRA */
|
||||
|
||||
/*
|
||||
* Enable/start PWM CPU fan
|
||||
*/
|
||||
void start_cpu_fan(void)
|
||||
{
|
||||
gpio_request(FAN_EN, "FAN_EN");
|
||||
gpio_direction_output(FAN_EN, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Backlight off before OS handover
|
||||
*/
|
||||
void board_preboot_os(void)
|
||||
{
|
||||
gpio_request(TEGRA_GPIO(BB, 5), "BL_ON");
|
||||
gpio_direction_output(TEGRA_GPIO(BB, 5), 0);
|
||||
}
|
||||
@@ -0,0 +1,139 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2012-2016 Toradex, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include "as3722_init.h"
|
||||
|
||||
/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
|
||||
|
||||
void tegra_i2c_ll_write_addr(uint addr, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(addr, ®->cmd_addr0);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void tegra_i2c_ll_write_data(uint data, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(data, ®->cmd_data1);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void pmic_enable_cpu_vdd(void)
|
||||
{
|
||||
debug("%s entry\n", __func__);
|
||||
|
||||
#ifdef AS3722_SD1VOLTAGE_DATA
|
||||
/* Set up VDD_CORE, for boards where OTP is incorrect*/
|
||||
debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
|
||||
/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Make sure all non-fused regulators are down.
|
||||
* That way we're in known state after software reboot from linux
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
|
||||
/*
|
||||
* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.0V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
|
||||
/*
|
||||
* Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.0V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
|
||||
/*
|
||||
* Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set VDD to 1.2V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
|
||||
/*
|
||||
* Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set it to value closest to 3.3V, then enable the regulator
|
||||
*
|
||||
* NOTE: We do this early because doing it later seems to hose the CPU
|
||||
* power rail/partition startup. Need to debug.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
|
||||
debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
|
||||
/*
|
||||
* Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
|
||||
* First set it to bypass 3.3V straight thru, then enable the regulator
|
||||
*
|
||||
* NOTE: We do this early because doing it later seems to hose the CPU
|
||||
* power rail/partition startup. Need to debug.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
|
||||
/*
|
||||
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
|
||||
* tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
|
||||
*/
|
||||
udelay(10 * 1000);
|
||||
}
|
||||
@@ -0,0 +1,40 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2012-2016 Toradex, Inc.
|
||||
*/
|
||||
|
||||
/* AS3722-PMIC-specific early init regs */
|
||||
|
||||
#define AS3722_I2C_ADDR 0x80
|
||||
|
||||
#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
|
||||
#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
|
||||
#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
|
||||
#define AS3722_SDCONTROL_REG 0x4D
|
||||
|
||||
#define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
|
||||
#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
|
||||
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
|
||||
#define AS3722_LDCONTROL_REG 0x4E
|
||||
|
||||
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
|
||||
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
|
||||
|
||||
#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
|
||||
#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
|
||||
|
||||
#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
|
||||
#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO1CONTROL_DATA (0x0200 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO1VOLTAGE_DATA (0x7F00 | AS3722_LDO1VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
|
||||
|
||||
#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
|
||||
#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
|
||||
|
||||
#define I2C_SEND_2_BYTES 0x0A02
|
||||
|
||||
void pmic_enable_cpu_vdd(void);
|
||||
@@ -0,0 +1,285 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2016-2019, Toradex, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_APALIS_TK1_H_
|
||||
#define _PINMUX_CONFIG_APALIS_TK1_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config apalis_tk1_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 1, IN),
|
||||
GPIO_INIT(B, 1, IN),
|
||||
GPIO_INIT(C, 0, OUT0),
|
||||
GPIO_INIT(I, 5, IN),
|
||||
GPIO_INIT(I, 6, IN),
|
||||
GPIO_INIT(J, 0, IN),
|
||||
GPIO_INIT(J, 2, IN),
|
||||
GPIO_INIT(K, 2, IN),
|
||||
GPIO_INIT(K, 7, IN),
|
||||
GPIO_INIT(N, 2, OUT1),
|
||||
GPIO_INIT(N, 7, IN),
|
||||
GPIO_INIT(O, 5, IN),
|
||||
GPIO_INIT(Q, 0, OUT0), /* Shift_CTRL_OE[0] */
|
||||
GPIO_INIT(Q, 1, OUT0), /* Shift_CTRL_OE[1] */
|
||||
GPIO_INIT(Q, 2, OUT0), /* Shift_CTRL_OE[2] */
|
||||
GPIO_INIT(Q, 4, OUT0), /* Shift_CTRL_OE[4] */
|
||||
GPIO_INIT(Q, 5, OUT1), /* Shift_CTRL_Dir_Out[0] */
|
||||
GPIO_INIT(Q, 6, OUT1), /* Shift_CTRL_Dir_Out[1] */
|
||||
GPIO_INIT(Q, 7, OUT1), /* Shift_CTRL_Dir_Out[2] */
|
||||
GPIO_INIT(R, 0, OUT0), /* Shift_CTRL_Dir_In[0] */
|
||||
GPIO_INIT(R, 1, OUT0), /* Shift_CTRL_Dir_In[1] */
|
||||
GPIO_INIT(R, 2, OUT0), /* Shift_CTRL_OE[3] */
|
||||
GPIO_INIT(S, 3, OUT0), /* Shift_CTRL_Dir_In[2] */
|
||||
GPIO_INIT(U, 4, OUT0), /* RESET_MOCI_CTRL */
|
||||
GPIO_INIT(V, 0, IN),
|
||||
GPIO_INIT(W, 3, IN),
|
||||
GPIO_INIT(W, 5, IN),
|
||||
GPIO_INIT(BB, 0, IN),
|
||||
GPIO_INIT(BB, 3, OUT0),
|
||||
GPIO_INIT(BB, 4, IN),
|
||||
GPIO_INIT(BB, 5, OUT1),
|
||||
GPIO_INIT(BB, 6, OUT0),
|
||||
GPIO_INIT(CC, 5, IN),
|
||||
GPIO_INIT(DD, 3, IN),
|
||||
GPIO_INIT(EE, 3, IN),
|
||||
GPIO_INIT(EE, 5, IN),
|
||||
GPIO_INIT(FF, 1, IN),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config apalis_tk1_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, rcv_sel */
|
||||
PINCFG(CLK_32K_OUT_PA0, SOC, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_CTS_N_PA1, GMI, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_FS_PA2, HDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PA3, HDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PA4, HDA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PA5, HDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB0, UARTD, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PB1, RSVD2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RTS_N_PC0, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG3, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG4, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH0, PWM0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH2, PWM2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH3, PWM3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PH7, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI5, RSVD2, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PI6, RSVD1, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ0, RSVD1, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PJ2, RSVD1, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK2, RSVD1, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PK7, RSVD2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PN4, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN1_PN5, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(HDMI_INT_PN7, RSVD1, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA4_PO5, ULPI, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DIN_PP1, I2S2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL0_PQ0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL1_PQ1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL2_PQ2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL4_PQ4, KBC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL5_PQ5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL6_PQ6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_COL7_PQ7, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW0_PR0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW1_PR1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW2_PR2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW4_PR4, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW7_PR7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW9_PS1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW10_PS2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW11_PS3, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW15_PS7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(KB_ROW17_PT1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SCL_PT5, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN2_I2C_SDA_PT6, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU1, UARTA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU2, UARTA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU3, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PU6, PWM3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CD_N_PV2, RSVD3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
|
||||
PINCFG(GPIO_W2_AUD_PW2, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_W3_AUD_PW3, SPI6, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_OUT_PW5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PX1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X4_AUD_PX4, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X5_AUD_PX5, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X6_AUD_PX6, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(GPIO_X7_AUD_PX7, SPI2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB0, VGP6, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
|
||||
PINCFG(PBB3, VGP3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB4, VGP4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB5, VGP5, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK2_REQ_PCC5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_RST_N_PDD1, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_WAKE_N_PDD3, RSVD2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_RST_N_PDD5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
/*
|
||||
* Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka not
|
||||
* tristated and input driver enabled as well as it features some magic
|
||||
* properties even though the external loopback is disabled and the internal
|
||||
* loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
|
||||
* being set to 0xfffd according to the TRM!
|
||||
*/
|
||||
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_LB_IN_PEE5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(DP_HPD_PFF0, DP, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN2_PFF1, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PFF2, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(OWR, RSVD2, NORMAL, TRISTATE, OUTPUT, DEFAULT, NORMAL),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config apalis_tk1_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_APALIS_TK1_H */
|
||||
Reference in New Issue
Block a user