GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,40 @@
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.. SPDX-License-Identifier: GPL-2.0+
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ADP-AG101P
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==========
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ADP-AG101P is the SoC with AG101 hardcore CPU.
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AG101P SoC
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----------
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AG101P is the mainline SoC produced by Andes Technology using N1213 CPU core
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with FPU and DDR contoller support.
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AG101P has integrated both AHB and APB bus and many periphals for application
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and product development.
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Configurations
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--------------
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CONFIG_MEM_REMAP:
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Doing memory remap is essential for preparing some non-OS or RTOS
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applications.
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CONFIG_SKIP_LOWLEVEL_INIT:
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If you want to boot this system from SPI ROM and bypass e-bios (the
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other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
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in "include/configs/adp-ag101p.h".
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Build and boot steps
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--------------------
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Build:
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1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
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2. Use `make adp-ag101p_defconfig` in u-boot root to build the image.
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Burn U-Boot to SPI ROM
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----------------------
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This section will be added later.
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@@ -0,0 +1,532 @@
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.. SPDX-License-Identifier: GPL-2.0+
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AX25-AE350
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==========
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AE350 is the mainline SoC produced by Andes Technology using AX25 CPU core
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base on RISC-V architecture.
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AE350 has integrated both AHB and APB bus and many periphals for application
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and product development.
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AX25-AE350 is the SoC with AE350 hardcore CPU.
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AX25 is Andes CPU IP to adopt RISC-V architecture.
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AX25 Features
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-------------
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CPU Core
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- 5-stage in-order execution pipeline
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- Hardware Multiplier
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- radix-2/radix-4/radix-16/radix-256/fast
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- Hardware Divider
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- Optional branch prediction
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- Machine mode and optional user mode
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- Optional performance monitoring
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ISA
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- RV64I base integer instructions
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- RVC for 16-bit compressed instructions
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- RVM for multiplication and division instructions
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Memory subsystem
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- I & D local memory
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- Size: 4KB to 16MB
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- Memory subsyetem soft-error protection
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- Protection scheme: parity-checking or error-checking-and-correction (ECC)
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- Automatic hardware error correction
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Bus
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- Interface Protocol
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- Synchronous AHB (32-bit/64-bit data-width), or
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- Synchronous AXI4 (64-bit data-width)
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Power management
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- Wait for interrupt (WFI) mode
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Debug
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- Configurable number of breakpoints: 2/4/8
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- External Debug Module
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- AHB slave port
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- External JTAG debug transport module
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Platform Level Interrupt Controller (PLIC)
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- AHB slave port
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- Configurable number of interrupts: 1-1023
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- Configurable number of interrupt priorities: 3/7/15/63/127/255
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- Configurable number of targets: 1-16
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- Preempted interrupt priority stack
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Configurations
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--------------
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CONFIG_SKIP_LOWLEVEL_INIT:
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If you want to boot this system from SPI ROM and bypass e-bios (the
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other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
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in "include/configs/ax25-ae350.h".
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Build and boot steps
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--------------------
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Build:
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1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
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2. Use `make ae350_rv[32|64]_defconfig` in u-boot root to build the image for
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32 or 64 bit.
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Verification:
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1. startup
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2. relocation
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3. timer driver
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4. uart driver
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5. mac driver
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6. mmc driver
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7. spi driver
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Steps
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-----
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1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram.
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2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom.
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3. Ping a server by mac driver
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4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver.
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5. Burn this u-boot image to spi rom by spi driver
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6. Re-boot u-boot from spi flash with power off and power on.
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Messages of U-Boot boot on AE350 board
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--------------------------------------
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.. code-block:: none
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U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800)
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DRAM: 1 GiB
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MMC: mmc@f0e00000: 0
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SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
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In: serial@f0300000
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Out: serial@f0300000
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Err: serial@f0300000
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Net:
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Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10
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eth0: mac@e0100000
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RISC-V # version
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U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800)
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riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0
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GNU ld (GNU Binutils) 2.29
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RISC-V # setenv ipaddr 10.0.4.200 ;
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RISC-V # setenv serverip 10.0.4.97 ;
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RISC-V # ping 10.0.4.97 ;
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Using mac@e0100000 device
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host 10.0.4.97 is alive
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RISC-V # mmc rescan
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RISC-V # fatls mmc 0:1
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318907 u-boot-ae350-64.bin
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1252 hello_world_ae350_32.bin
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328787 u-boot-ae350-32.bin
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3 file(s), 0 dir(s)
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RISC-V # sf probe 0:0 50000000 0
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SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
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RISC-V # sf test 0x100000 0x1000
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SPI flash test:
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0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
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1 check: 29 ticks, 137 KiB/s 1.096 Mbps
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2 write: 40 ticks, 100 KiB/s 0.800 Mbps
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3 read: 20 ticks, 200 KiB/s 1.600 Mbps
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Test passed
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0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
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1 check: 29 ticks, 137 KiB/s 1.096 Mbps
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2 write: 40 ticks, 100 KiB/s 0.800 Mbps
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3 read: 20 ticks, 200 KiB/s 1.600 Mbps
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RISC-V # fatload mmc 0:1 0x600000 u-boot-ae350-32.bin
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reading u-boot-ae350-32.bin
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328787 bytes read in 324 ms (990.2 KiB/s)
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RISC-V # sf erase 0x0 0x51000
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SF: 331776 bytes @ 0x0 Erased: OK
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RISC-V # sf write 0x600000 0x0 0x50453
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device 0 offset 0x0, size 0x50453
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SF: 328787 bytes @ 0x0 Written: OK
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RISC-V # crc32 0x600000 0x50453
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crc32 for 00600000 ... 00650452 ==> 692dc44a
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RISC-V # crc32 0x80000000 0x50453
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crc32 for 80000000 ... 80050452 ==> 692dc44a
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RISC-V #
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*** power-off and power-on, this U-Boot is booted from spi flash ***
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U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800)
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DRAM: 1 GiB
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MMC: mmc@f0e00000: 0
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SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
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In: serial@f0300000
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Out: serial@f0300000
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Err: serial@f0300000
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Net:
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Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5
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eth0: mac@e0100000
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RISC-V #
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Boot bbl and riscv-linux via U-Boot on QEMU
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-------------------------------------------
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1. Build riscv-linux
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2. Build bbl and riscv-linux with --with-payload
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3. Prepare ae350.dtb
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4. Creating OS-kernel images
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.. code-block:: none
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./mkimage -A riscv -O linux -T kernel -C none -a 0x0000 -e 0x0000 -d bbl.bin bootmImage-bbl.bin
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Image Name:
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Created: Tue Mar 13 10:06:42 2018
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Image Type: RISC-V Linux Kernel Image (uncompressed)
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Data Size: 17901204 Bytes = 17481.64 KiB = 17.07 MiB
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Load Address: 00000000
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Entry Point: 00000000
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5. Copy bootmImage-bbl.bin and ae350.dtb to qemu sd card image
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6. Message of booting riscv-linux from bbl via u-boot on qemu
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.. code-block:: none
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U-Boot 2018.03-rc4-00031-g2631273 (Mar 13 2018 - 15:02:55 +0800)
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DRAM: 1 GiB
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main-loop: WARNING: I/O thread spun for 1000 iterations
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MMC: mmc@f0e00000: 0
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Loading Environment from SPI Flash... *** Warning - spi_flash_probe_bus_cs() failed, using default environment
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Failed (-22)
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In: serial@f0300000
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Out: serial@f0300000
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Err: serial@f0300000
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Net:
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Warning: mac@e0100000 (eth0) using random MAC address - 02:00:00:00:00:00
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eth0: mac@e0100000
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RISC-V # mmc rescan
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RISC-V # mmc part
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Partition Map for MMC device 0 -- Partition Type: DOS
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Part Start Sector Num Sectors UUID Type
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RISC-V # fatls mmc 0:0
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17901268 bootmImage-bbl.bin
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1954 ae2xx.dtb
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2 file(s), 0 dir(s)
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RISC-V # fatload mmc 0:0 0x00600000 bootmImage-bbl.bin
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17901268 bytes read in 4642 ms (3.7 MiB/s)
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RISC-V # fatload mmc 0:0 0x2000000 ae350.dtb
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1954 bytes read in 1 ms (1.9 MiB/s)
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RISC-V # setenv bootm_size 0x2000000
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RISC-V # setenv fdt_high 0x1f00000
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RISC-V # bootm 0x00600000 - 0x2000000
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## Booting kernel from Legacy Image at 00600000 ...
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Image Name:
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Image Type: RISC-V Linux Kernel Image (uncompressed)
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Data Size: 17901204 Bytes = 17.1 MiB
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Load Address: 00000000
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Entry Point: 00000000
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Verifying Checksum ... OK
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## Flattened Device Tree blob at 02000000
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Booting using the fdt blob at 0x2000000
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Loading Kernel Image ... OK
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Loading Device Tree to 0000000001efc000, end 0000000001eff7a1 ... OK
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[ 0.000000] OF: fdt: Ignoring memory range 0x0 - 0x200000
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[ 0.000000] Linux version 4.14.0-00046-gf3e439f-dirty (rick@atcsqa06) (gcc version 7.1.1 20170509 (GCC)) #1 Tue Jan 9 16:34:25 CST 2018
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[ 0.000000] bootconsole [early0] enabled
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[ 0.000000] Initial ramdisk at: 0xffffffe000016a98 (12267008 bytes)
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[ 0.000000] Zone ranges:
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[ 0.000000] DMA [mem 0x0000000000200000-0x000000007fffffff]
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[ 0.000000] Normal empty
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[ 0.000000] Movable zone start for each node
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[ 0.000000] Early memory node ranges
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[ 0.000000] node 0: [mem 0x0000000000200000-0x000000007fffffff]
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[ 0.000000] Initmem setup node 0 [mem 0x0000000000200000-0x000000007fffffff]
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[ 0.000000] elf_hwcap is 0x112d
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[ 0.000000] random: fast init done
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[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 516615
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[ 0.000000] Kernel command line: console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7
|
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[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
|
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[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
|
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[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
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[ 0.000000] Sorting __ex_table...
|
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[ 0.000000] Memory: 2047832K/2095104K available (1856K kernel code, 204K rwdata, 532K rodata, 12076K init, 756K bss, 47272K reserved, 0K cma-reserved)
|
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[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
|
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[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
|
||||
[ 0.000000] riscv,cpu_intc,0: 64 local interrupts mapped
|
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[ 0.000000] riscv,plic0,e4000000: mapped 31 interrupts to 1/2 handlers
|
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[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns
|
||||
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000)
|
||||
[ 0.000000] pid_max: default: 32768 minimum: 301
|
||||
[ 0.004000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
|
||||
[ 0.004000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
|
||||
[ 0.056000] devtmpfs: initialized
|
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[ 0.060000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
|
||||
[ 0.064000] futex hash table entries: 256 (order: 0, 6144 bytes)
|
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[ 0.068000] NET: Registered protocol family 16
|
||||
[ 0.080000] vgaarb: loaded
|
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[ 0.084000] clocksource: Switched to clocksource riscv_clocksource
|
||||
[ 0.088000] NET: Registered protocol family 2
|
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[ 0.092000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.096000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.096000] TCP: Hash tables configured (established 16384 bind 16384)
|
||||
[ 0.100000] UDP hash table entries: 1024 (order: 3, 32768 bytes)
|
||||
[ 0.100000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
|
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[ 0.104000] NET: Registered protocol family 1
|
||||
[ 0.616000] Unpacking initramfs...
|
||||
[ 1.220000] workingset: timestamp_bits=62 max_order=19 bucket_order=0
|
||||
[ 1.244000] io scheduler noop registered
|
||||
[ 1.244000] io scheduler cfq registered (default)
|
||||
[ 1.244000] io scheduler mq-deadline registered
|
||||
[ 1.248000] io scheduler kyber registered
|
||||
[ 1.360000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 1.368000] console [ttyS0] disabled
|
||||
[ 1.372000] f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 10, base_baud = 1228800) is a 16550A
|
||||
[ 1.392000] console [ttyS0] enabled
|
||||
[ 1.392000] ftmac100: Loading version 0.2 ...
|
||||
[ 1.396000] ftmac100 e0100000.mac eth0: irq 8, mapped at ffffffd002005000
|
||||
[ 1.400000] ftmac100 e0100000.mac eth0: generated random MAC address 6e:ac:c3:92:36:c0
|
||||
[ 1.404000] IR NEC protocol handler initialized
|
||||
[ 1.404000] IR RC5(x/sz) protocol handler initialized
|
||||
[ 1.404000] IR RC6 protocol handler initialized
|
||||
[ 1.404000] IR JVC protocol handler initialized
|
||||
[ 1.408000] IR Sony protocol handler initialized
|
||||
[ 1.408000] IR SANYO protocol handler initialized
|
||||
[ 1.408000] IR Sharp protocol handler initialized
|
||||
[ 1.408000] IR MCE Keyboard/mouse protocol handler initialized
|
||||
[ 1.412000] IR XMP protocol handler initialized
|
||||
[ 1.456000] ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ
|
||||
[ 1.464000] bootconsole [early0] uses init memory and must be disabled even before the real one is ready
|
||||
[ 1.464000] bootconsole [early0] disabled
|
||||
[ 1.508000] Freeing unused kernel memory: 12076K
|
||||
[ 1.512000] This architecture does not have kernel memory protection.
|
||||
[ 1.520000] mmc0: new SD card at address 4567
|
||||
[ 1.524000] mmcblk0: mmc0:4567 QEMU! 20.0 MiB
|
||||
[ 1.844000] mmcblk0:
|
||||
Wed Dec 1 10:00:00 CST 2010
|
||||
/ #
|
||||
|
||||
|
||||
Running U-Boot SPL
|
||||
------------------
|
||||
The U-Boot SPL will boot in M mode and load the FIT image which include
|
||||
OpenSBI and U-Boot proper images. After loading progress, it will jump
|
||||
to OpenSBI first and then U-Boot proper which will run in S mode.
|
||||
|
||||
|
||||
How to build U-Boot SPL
|
||||
-----------------------
|
||||
Before building U-Boot SPL, OpenSBI must be build first. OpenSBI can be
|
||||
cloned and build for AE350 as below:
|
||||
|
||||
git clone https://github.com/riscv/opensbi.git
|
||||
cd opensbi
|
||||
make PLATFORM=andes/ae350
|
||||
|
||||
Copy OpenSBI FW_DYNAMIC image (build\platform\andes\ae350\firmware\fw_dynamic.bin)
|
||||
into U-Boot root directory
|
||||
|
||||
|
||||
How to build U-Boot SPL booting from RAM
|
||||
----------------------------------------
|
||||
With ae350_rv[32|64]_spl_defconfigs:
|
||||
|
||||
U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode
|
||||
and then load FIT image from RAM device on AE350.
|
||||
|
||||
|
||||
How to build U-Boot SPL booting from ROM
|
||||
----------------------------------------
|
||||
With ae350_rv[32|64]_spl_xip_defconfigs:
|
||||
|
||||
U-Boot SPL can be burned into SPI flash and run in flash in machine mode
|
||||
and then load FIT image from SPI flash or MMC device on AE350.
|
||||
|
||||
|
||||
Messages of U-Boot SPL boots Kernel on AE350 board
|
||||
--------------------------------------------------
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
U-Boot SPL 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800)
|
||||
Trying to boot from RAM
|
||||
|
||||
OpenSBI v0.5-1-gdd8ef28 (Nov 14 2019 11:08:39)
|
||||
____ _____ ____ _____
|
||||
/ __ \ / ____| _ \_ _|
|
||||
| | | |_ __ ___ _ __ | (___ | |_) || |
|
||||
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
|
||||
| |__| | |_) | __/ | | |____) | |_) || |_
|
||||
\____/| .__/ \___|_| |_|_____/|____/_____|
|
||||
| |
|
||||
|_|
|
||||
|
||||
Platform Name : Andes AE350
|
||||
Platform HART Features : RV64ACIMSUX
|
||||
Platform Max HARTs : 4
|
||||
Current Hart : 0
|
||||
Firmware Base : 0x0
|
||||
Firmware Size : 84 KB
|
||||
Runtime SBI Version : 0.2
|
||||
|
||||
PMP0: 0x0000000000000000-0x000000000001ffff (A)
|
||||
PMP1: 0x0000000000000000-0x00000001ffffffff (A,R,W,X)
|
||||
|
||||
|
||||
U-Boot 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800)
|
||||
|
||||
DRAM: 1 GiB
|
||||
Flash: 64 MiB
|
||||
MMC: mmc@f0e00000: 0
|
||||
Loading Environment from SPI Flash... SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
|
||||
OK
|
||||
In: serial@f0300000
|
||||
Out: serial@f0300000
|
||||
Err: serial@f0300000
|
||||
Net: no alias for ethernet0
|
||||
|
||||
Warning: mac@e0100000 (eth0) using random MAC address - a2:ae:93:7b:cc:8f
|
||||
eth0: mac@e0100000
|
||||
Hit any key to stop autoboot: 0
|
||||
6455 bytes read in 31 ms (203.1 KiB/s)
|
||||
20421684 bytes read in 8647 ms (2.3 MiB/s)
|
||||
## Booting kernel from Legacy Image at 00600000 ...
|
||||
Image Name:
|
||||
Image Type: RISC-V Linux Kernel Image (uncompressed)
|
||||
Data Size: 20421620 Bytes = 19.5 MiB
|
||||
Load Address: 00200000
|
||||
Entry Point: 00200000
|
||||
Verifying Checksum ... OK
|
||||
## Flattened Device Tree blob at 20000000
|
||||
Booting using the fdt blob at 0x20000000
|
||||
Loading Kernel Image
|
||||
Loading Device Tree to 000000001effb000, end 000000001efff936 ... OK
|
||||
|
||||
Starting kernel ...
|
||||
|
||||
OF: fdt: Ignoring memory range 0x0 - 0x200000
|
||||
Linux version 4.17.0-00253-g49136e10bcb2 (sqa@atcsqa07) (gcc version 7.3.0 (2019-04-06_nds64le-linux-glibc-v5_experimental)) #1 SMP PREEMPT Sat Apr 6 23:41:49 CST 2019
|
||||
bootconsole [early0] enabled
|
||||
Initial ramdisk at: 0x (ptrval) (13665712 bytes)
|
||||
Zone ranges:
|
||||
DMA32 [mem 0x0000000000200000-0x000000003fffffff]
|
||||
Normal empty
|
||||
Movable zone start for each node
|
||||
Early memory node ranges
|
||||
node 0: [mem 0x0000000000200000-0x000000003fffffff]
|
||||
Initmem setup node 0 [mem 0x0000000000200000-0x000000003fffffff]
|
||||
software IO TLB [mem 0x3b1f8000-0x3f1f8000] (64MB) mapped at [ (ptrval)- (ptrval)]
|
||||
elf_platform is rv64i2p0m2p0a2p0c2p0xv5-0p0
|
||||
compatible privileged spec version 1.10
|
||||
percpu: Embedded 16 pages/cpu @ (ptrval) s28184 r8192 d29160 u65536
|
||||
Built 1 zonelists, mobility grouping on. Total pages: 258055
|
||||
Kernel command line: console=ttyS0,38400n8 debug loglevel=7
|
||||
log_buf_len individual max cpu contribution: 4096 bytes
|
||||
log_buf_len total cpu_extra contributions: 12288 bytes
|
||||
log_buf_len min size: 16384 bytes
|
||||
log_buf_len: 32768 bytes
|
||||
early log buf free: 14608(89%)
|
||||
Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
|
||||
Inode-cache hash table entries: 65536 (order: 7, 524288 bytes)
|
||||
Sorting __ex_table...
|
||||
Memory: 944428K/1046528K available (3979K kernel code, 246K rwdata, 1490K rodata, 13523K init, 688K bss, 102100K reserved, 0K cma-reserved)
|
||||
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
|
||||
Preemptible hierarchical RCU implementation.
|
||||
Tasks RCU enabled.
|
||||
NR_IRQS: 72, nr_irqs: 72, preallocated irqs: 0
|
||||
riscv,cpu_intc,0: 64 local interrupts mapped
|
||||
riscv,cpu_intc,1: 64 local interrupts mapped
|
||||
riscv,cpu_intc,2: 64 local interrupts mapped
|
||||
riscv,cpu_intc,3: 64 local interrupts mapped
|
||||
riscv,plic0,e4000000: mapped 71 interrupts to 8/8 handlers
|
||||
clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1bacf917bf, max_idle_ns: 881590412290 ns
|
||||
sched_clock: 64 bits at 60MHz, resolution 16ns, wraps every 4398046511098ns
|
||||
Console: colour dummy device 40x30
|
||||
Calibrating delay loop (skipped), value calculated using timer frequency.. 120.00 BogoMIPS (lpj=600000)
|
||||
pid_max: default: 32768 minimum: 301
|
||||
Mount-cache hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
Hierarchical SRCU implementation.
|
||||
smp: Bringing up secondary CPUs ...
|
||||
CPU0: online
|
||||
CPU2: online
|
||||
CPU3: online
|
||||
smp: Brought up 1 node, 4 CPUs
|
||||
devtmpfs: initialized
|
||||
random: get_random_u32 called from bucket_table_alloc+0x198/0x1d8 with crng_init=0
|
||||
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
|
||||
futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
NET: Registered protocol family 16
|
||||
Advanced Linux Sound Architecture Driver Initialized.
|
||||
clocksource: Switched to clocksource riscv_clocksource
|
||||
NET: Registered protocol family 2
|
||||
tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes)
|
||||
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
|
||||
TCP bind hash table entries: 8192 (order: 5, 131072 bytes)
|
||||
TCP: Hash tables configured (established 8192 bind 8192)
|
||||
UDP hash table entries: 512 (order: 2, 16384 bytes)
|
||||
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
|
||||
NET: Registered protocol family 1
|
||||
RPC: Registered named UNIX socket transport module.
|
||||
RPC: Registered udp transport module.
|
||||
RPC: Registered tcp transport module.
|
||||
RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
Unpacking initramfs...
|
||||
workingset: timestamp_bits=62 max_order=18 bucket_order=0
|
||||
NFS: Registering the id_resolver key type
|
||||
Key type id_resolver registered
|
||||
Key type id_legacy registered
|
||||
nfs4filelayout_init: NFSv4 File Layout Driver Registering...
|
||||
io scheduler noop registered
|
||||
io scheduler cfq registered (default)
|
||||
io scheduler mq-deadline registered
|
||||
io scheduler kyber registered
|
||||
Console: switching to colour frame buffer device 40x30
|
||||
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
console [ttyS0] disabled
|
||||
f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 20, base_baud = 1228800) is a 16550A
|
||||
console [ttyS0] enabled
|
||||
console [ttyS0] enabled
|
||||
bootconsole [early0] disabled
|
||||
bootconsole [early0] disabled
|
||||
loop: module loaded
|
||||
tun: Universal TUN/TAP device driver, 1.6
|
||||
ftmac100: Loading version 0.2 ...
|
||||
ftmac100 e0100000.mac eth0: irq 21, mapped at (ptrval)
|
||||
ftmac100 e0100000.mac eth0: generated random MAC address 4e:fd:bd:f3:04:fc
|
||||
ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ
|
||||
mmc0: new SDHC card at address d555
|
||||
ftssp010 card registered!
|
||||
mmcblk0: mmc0:d555 SD04G 3.79 GiB
|
||||
NET: Registered protocol family 10
|
||||
mmcblk0: p1
|
||||
Segment Routing with IPv6
|
||||
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
|
||||
NET: Registered protocol family 17
|
||||
NET: Registered protocol family 15
|
||||
ALSA device list:
|
||||
#0: ftssp_ac97 controller
|
||||
Freeing unused kernel memory: 13520K
|
||||
This architecture does not have kernel memory protection.
|
||||
Sysinit starting
|
||||
Sat Apr 6 23:33:53 CST 2019
|
||||
nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
|
||||
|
||||
~ #
|
||||
@@ -0,0 +1,10 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Andes Tech
|
||||
==========
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
adp-ag101p
|
||||
ax25-ae350
|
||||
@@ -0,0 +1,192 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
AT91 Evaluation kits
|
||||
====================
|
||||
|
||||
Board mapping & boot media
|
||||
--------------------------
|
||||
|
||||
AT91SAM9260EK, AT91SAM9G20EK & AT91SAM9XEEK
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Memory map::
|
||||
|
||||
0x20000000 - 23FFFFFF SDRAM (64 MB)
|
||||
0xC0000000 - Cxxxxxxx Atmel Dataflash card (J13)
|
||||
0xD0000000 - D07FFFFF Soldered Atmel Dataflash (AT45DB642)
|
||||
|
||||
Environment variables
|
||||
|
||||
U-Boot environment variables can be stored at different places:
|
||||
|
||||
- Dataflash on SPI chip select 1 (default)
|
||||
- Dataflash on SPI chip select 0 (dataflash card)
|
||||
- Nand flash
|
||||
|
||||
You can choose your storage location at config step (here for at91sam9260ek)::
|
||||
|
||||
make at91sam9260ek_nandflash_config - use nand flash
|
||||
make at91sam9260ek_dataflash_cs0_config - use data flash (spi cs0)
|
||||
make at91sam9260ek_dataflash_cs1_config - use data flash (spi cs1)
|
||||
|
||||
|
||||
AT91SAM9261EK, AT91SAM9G10EK
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Memory map::
|
||||
|
||||
0x20000000 - 23FFFFFF SDRAM (64 MB)
|
||||
0xC0000000 - C07FFFFF Soldered Atmel Dataflash (AT45DB642)
|
||||
0xD0000000 - Dxxxxxxx Atmel Dataflash card (J22)
|
||||
|
||||
Environment variables
|
||||
|
||||
U-Boot environment variables can be stored at different places:
|
||||
|
||||
- Dataflash on SPI chip select 0 (default)
|
||||
- Dataflash on SPI chip select 3 (dataflash card)
|
||||
- Nand flash
|
||||
|
||||
You can choose your storage location at config step (here for at91sam9260ek)::
|
||||
|
||||
make at91sam9261ek_nandflash_config - use nand flash
|
||||
make at91sam9261ek_dataflash_cs0_config - use data flash (spi cs0)
|
||||
make at91sam9261ek_dataflash_cs3_config - use data flash (spi cs3)
|
||||
|
||||
|
||||
AT91SAM9263EK
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
Memory map::
|
||||
|
||||
0x20000000 - 23FFFFFF SDRAM (64 MB)
|
||||
0xC0000000 - Cxxxxxxx Atmel Dataflash card (J9)
|
||||
|
||||
Environment variables
|
||||
|
||||
U-Boot environment variables can be stored at different places:
|
||||
|
||||
- Dataflash on SPI chip select 0 (dataflash card)
|
||||
- Nand flash
|
||||
- Nor flash (not populate by default)
|
||||
|
||||
You can choose your storage location at config step (here for at91sam9260ek)::
|
||||
|
||||
make at91sam9263ek_nandflash_config - use nand flash
|
||||
make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0)
|
||||
make at91sam9263ek_norflash_config - use nor flash
|
||||
|
||||
You can choose to boot directly from U-Boot at config step::
|
||||
|
||||
make at91sam9263ek_norflash_boot_config - boot from nor flash
|
||||
|
||||
|
||||
AT91SAM9M10G45EK
|
||||
^^^^^^^^^^^^^^^^
|
||||
|
||||
Memory map::
|
||||
|
||||
0x70000000 - 77FFFFFF SDRAM (128 MB)
|
||||
|
||||
Environment variables
|
||||
|
||||
U-Boot environment variables can be stored at different places:
|
||||
|
||||
- Nand flash
|
||||
|
||||
You can choose your storage location at config step (here for at91sam9m10g45ek)::
|
||||
|
||||
make at91sam9m10g45ek_nandflash_config - use nand flash
|
||||
|
||||
|
||||
AT91SAM9RLEK
|
||||
^^^^^^^^^^^^
|
||||
|
||||
Memory map::
|
||||
|
||||
0x20000000 - 23FFFFFF SDRAM (64 MB)
|
||||
0xC0000000 - C07FFFFF Soldered Atmel Dataflash (AT45DB642)
|
||||
|
||||
Environment variables
|
||||
|
||||
U-Boot environment variables can be stored at different places:
|
||||
|
||||
- Dataflash on SPI chip select 0
|
||||
- Nand flash.
|
||||
|
||||
You can choose your storage location at config step (here for at91sam9rlek)::
|
||||
|
||||
make at91sam9rlek_nandflash_config - use nand flash
|
||||
|
||||
|
||||
AT91SAM9N12EK, AT91SAM9X5EK
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Memory map::
|
||||
|
||||
0x20000000 - 27FFFFFF SDRAM (128 MB)
|
||||
|
||||
Environment variables
|
||||
|
||||
U-Boot environment variables can be stored at different places:
|
||||
|
||||
- Nand flash
|
||||
- SD/MMC card
|
||||
- Serialflash/Dataflash on SPI chip select 0
|
||||
|
||||
You can choose your storage location at config step (here for at91sam9x5ek)::
|
||||
|
||||
make at91sam9x5ek_dataflash_config - use data flash
|
||||
make at91sam9x5ek_mmc_config - use sd/mmc card
|
||||
make at91sam9x5ek_nandflash_config - use nand flash
|
||||
make at91sam9x5ek_spiflash_config - use serial flash
|
||||
|
||||
|
||||
SAMA5D3XEK
|
||||
^^^^^^^^^^
|
||||
|
||||
Memory map::
|
||||
|
||||
0x20000000 - 3FFFFFFF SDRAM (512 MB)
|
||||
|
||||
Environment variables
|
||||
|
||||
U-Boot environment variables can be stored at different places:
|
||||
|
||||
- Nand flash
|
||||
- SD/MMC card
|
||||
- Serialflash on SPI chip select 0
|
||||
|
||||
You can choose your storage location at config step (here for sama5d3xek)::
|
||||
|
||||
make sama5d3xek_mmc_config - use SD/MMC card
|
||||
make sama5d3xek_nandflash_config - use nand flash
|
||||
make sama5d3xek_serialflash_config - use serial flash
|
||||
|
||||
|
||||
NAND partition table
|
||||
--------------------
|
||||
|
||||
All the board support boot from NAND flash will use the following NAND
|
||||
partition table::
|
||||
|
||||
0x00000000 - 0x0003FFFF bootstrap (256 KiB)
|
||||
0x00040000 - 0x000BFFFF u-boot (512 KiB)
|
||||
0x000C0000 - 0x000FFFFF env (256 KiB)
|
||||
0x00100000 - 0x0013FFFF env_redundant (256 KiB)
|
||||
0x00140000 - 0x0017FFFF spare (256 KiB)
|
||||
0x00180000 - 0x001FFFFF dtb (512 KiB)
|
||||
0x00200000 - 0x007FFFFF kernel (6 MiB)
|
||||
0x00800000 - 0xxxxxxxxx rootfs (All left)
|
||||
|
||||
|
||||
Watchdog support
|
||||
----------------
|
||||
|
||||
For security reasons, the at91 watchdog is running at boot time and,
|
||||
if deactivated, cannot be used anymore.
|
||||
If you want to use the watchdog, you will need to keep it running in
|
||||
your code (make sure not to disable it in AT91Bootstrap for instance).
|
||||
|
||||
In the U-Boot configuration, the AT91 watchdog support is enabled using
|
||||
the CONFIG_WDT and CONFIG_WDT_AT91 options.
|
||||
@@ -0,0 +1,9 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Atmel
|
||||
=====
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
at91ek
|
||||
@@ -0,0 +1,42 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
|
||||
|
||||
Coreboot
|
||||
========
|
||||
|
||||
Build Instructions for U-Boot as coreboot payload
|
||||
-------------------------------------------------
|
||||
Building U-Boot as a coreboot payload is just like building U-Boot for targets
|
||||
on other architectures, like below::
|
||||
|
||||
$ make coreboot_defconfig
|
||||
$ make all
|
||||
|
||||
Test with coreboot
|
||||
------------------
|
||||
For testing U-Boot as the coreboot payload, there are things that need be paid
|
||||
attention to. coreboot supports loading an ELF executable and a 32-bit plain
|
||||
binary, as well as other supported payloads. With the default configuration,
|
||||
U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
|
||||
generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
|
||||
provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
|
||||
this capability yet. The command is as follows::
|
||||
|
||||
# in the coreboot root directory
|
||||
$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
|
||||
-f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
|
||||
|
||||
Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address
|
||||
of _x86boot_start (in arch/x86/cpu/start.S).
|
||||
|
||||
If you want to use ELF as the coreboot payload, change U-Boot configuration to
|
||||
use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
|
||||
|
||||
To enable video you must enable these options in coreboot:
|
||||
|
||||
- Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
|
||||
- Keep VESA framebuffer
|
||||
|
||||
At present it seems that for Minnowboard Max, coreboot does not pass through
|
||||
the video information correctly (it always says the resolution is 0x0). This
|
||||
works correctly for link though.
|
||||
@@ -0,0 +1,9 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Coreboot
|
||||
========
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
coreboot
|
||||
@@ -0,0 +1,12 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Emulation
|
||||
=========
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
qemu-arm
|
||||
qemu-mips
|
||||
qemu-riscv
|
||||
qemu-x86
|
||||
@@ -0,0 +1,82 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. Copyright (C) 2017, Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
|
||||
|
||||
QEMU ARM
|
||||
========
|
||||
|
||||
QEMU for ARM supports a special 'virt' machine designed for emulation and
|
||||
virtualization purposes. This document describes how to run U-Boot under it.
|
||||
Both 32-bit ARM and AArch64 are supported.
|
||||
|
||||
The 'virt' platform provides the following as the basic functionality:
|
||||
|
||||
- A freely configurable amount of CPU cores
|
||||
- U-Boot loaded and executing in the emulated flash at address 0x0
|
||||
- A generated device tree blob placed at the start of RAM
|
||||
- A freely configurable amount of RAM, described by the DTB
|
||||
- A PL011 serial port, discoverable via the DTB
|
||||
- An ARMv7/ARMv8 architected timer
|
||||
- PSCI for rebooting the system
|
||||
- A generic ECAM-based PCI host controller, discoverable via the DTB
|
||||
|
||||
Additionally, a number of optional peripherals can be added to the PCI bus.
|
||||
|
||||
Building U-Boot
|
||||
---------------
|
||||
Set the CROSS_COMPILE environment variable as usual, and run:
|
||||
|
||||
- For ARM::
|
||||
|
||||
make qemu_arm_defconfig
|
||||
make
|
||||
|
||||
- For AArch64::
|
||||
|
||||
make qemu_arm64_defconfig
|
||||
make
|
||||
|
||||
Running U-Boot
|
||||
--------------
|
||||
The minimal QEMU command line to get U-Boot up and running is:
|
||||
|
||||
- For ARM::
|
||||
|
||||
qemu-system-arm -machine virt -bios u-boot.bin
|
||||
|
||||
- For AArch64::
|
||||
|
||||
qemu-system-aarch64 -machine virt -cpu cortex-a57 -bios u-boot.bin
|
||||
|
||||
Note that for some odd reason qemu-system-aarch64 needs to be explicitly
|
||||
told to use a 64-bit CPU or it will boot in 32-bit mode.
|
||||
|
||||
Additional persistent U-boot environment support can be added as follows:
|
||||
|
||||
- Create envstore.img using qemu-img::
|
||||
|
||||
qemu-img create -f raw envstore.img 64M
|
||||
|
||||
- Add a pflash drive parameter to the command line::
|
||||
|
||||
-drive if=pflash,format=raw,index=1,file=envstore.img
|
||||
|
||||
Additional peripherals that have been tested to work in both U-Boot and Linux
|
||||
can be enabled with the following command line parameters:
|
||||
|
||||
- To add a Serial ATA disk via an Intel ICH9 AHCI controller, pass e.g.::
|
||||
|
||||
-drive if=none,file=disk.img,id=mydisk -device ich9-ahci,id=ahci -device ide-drive,drive=mydisk,bus=ahci.0
|
||||
|
||||
- To add an Intel E1000 network adapter, pass e.g.::
|
||||
|
||||
-netdev user,id=net0 -device e1000,netdev=net0
|
||||
|
||||
- To add an EHCI-compliant USB host controller, pass e.g.::
|
||||
|
||||
-device usb-ehci,id=ehci
|
||||
|
||||
- To add a NVMe disk, pass e.g.::
|
||||
|
||||
-drive if=none,file=disk.img,id=mydisk -device nvme,drive=mydisk,serial=foo
|
||||
|
||||
These have been tested in QEMU 2.9.0 but should work in at least 2.5.0 as well.
|
||||
@@ -0,0 +1,234 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Vlad Lungu <vlad.lungu@windriver.com>
|
||||
|
||||
QEMU MIPS
|
||||
=========
|
||||
|
||||
Qemu is a full system emulator. See http://www.nongnu.org/qemu/
|
||||
|
||||
Limitations & comments
|
||||
----------------------
|
||||
Supports the "-M mips" configuration of qemu: serial,NE2000,IDE.
|
||||
Supports little and big endian as well as 32 bit and 64 bit.
|
||||
Derived from au1x00 with a lot of things cut out.
|
||||
|
||||
Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with
|
||||
recent qemu versions. When using emulated flash, launch with
|
||||
-pflash <filename> and erase mips_bios.bin.
|
||||
|
||||
|
||||
Notes for the Qemu MIPS port
|
||||
----------------------------
|
||||
|
||||
Example usage
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
Using u-boot.bin as ROM (replaces Qemu monitor):
|
||||
|
||||
32 bit, big endian::
|
||||
|
||||
# make qemu_mips
|
||||
# qemu-system-mips -M mips -bios u-boot.bin -nographic
|
||||
|
||||
32 bit, little endian::
|
||||
|
||||
# make qemu_mipsel
|
||||
# qemu-system-mipsel -M mips -bios u-boot.bin -nographic
|
||||
|
||||
64 bit, big endian::
|
||||
|
||||
# make qemu_mips64
|
||||
# qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
|
||||
|
||||
64 bit, little endian::
|
||||
|
||||
# make qemu_mips64el
|
||||
# qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
|
||||
|
||||
or using u-boot.bin from emulated flash:
|
||||
|
||||
if you use a qemu version after commit 4224
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
create image:
|
||||
# dd of=flash bs=1k count=4k if=/dev/zero
|
||||
# dd of=flash bs=1k conv=notrunc if=u-boot.bin
|
||||
start it (see above):
|
||||
# qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash -nographic
|
||||
|
||||
Download kernel + initrd
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/
|
||||
you can downland::
|
||||
|
||||
#config to build the kernel
|
||||
qemu_mips_defconfig
|
||||
#patch to fix mips interrupt init on 2.6.24.y kernel
|
||||
qemu_mips_kernel.patch
|
||||
initrd.gz
|
||||
vmlinux
|
||||
vmlinux.bin
|
||||
System.map
|
||||
|
||||
Generate uImage
|
||||
^^^^^^^^^^^^^^^
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage
|
||||
|
||||
Copy uImage to Flash
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
# dd if=uImage bs=1k conv=notrunc seek=224 of=flash
|
||||
|
||||
Generate Ide Disk
|
||||
^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
# dd of=ide bs=1k cout=100k if=/dev/zero
|
||||
|
||||
# sfdisk -C 261 -d ide
|
||||
# partition table of ide
|
||||
unit: sectors
|
||||
|
||||
ide1 : start= 63, size= 32067, Id=83
|
||||
ide2 : start= 32130, size= 32130, Id=83
|
||||
ide3 : start= 64260, size= 4128705, Id=83
|
||||
ide4 : start= 0, size= 0, Id= 0
|
||||
|
||||
Copy to ide
|
||||
^^^^^^^^^^^
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
# dd if=uImage bs=512 conv=notrunc seek=63 of=ide
|
||||
|
||||
Generate ext2 on part 2 on Copy uImage and initrd.gz
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
# Attached as loop device ide offset = 32130 * 512
|
||||
# losetup -o 16450560 -f ide
|
||||
# Format as ext2 ( arg2 : nb blocks)
|
||||
# mke2fs /dev/loop0 16065
|
||||
# losetup -d /dev/loop0
|
||||
# Mount and copy uImage and initrd.gz to it
|
||||
# mount -o loop,offset=16450560 -t ext2 ide /mnt
|
||||
# mkdir /mnt/boot
|
||||
# cp {initrd.gz,uImage} /mnt/boot/
|
||||
# Umount it
|
||||
# umount /mnt
|
||||
|
||||
Set Environment
|
||||
^^^^^^^^^^^^^^^
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
setenv rd_start 0x80800000
|
||||
setenv rd_size 2663940
|
||||
setenv kernel BFC38000
|
||||
setenv oad_addr 80500000
|
||||
setenv load_addr2 80F00000
|
||||
setenv kernel_flash BFC38000
|
||||
setenv load_addr_hello 80200000
|
||||
setenv bootargs 'root=/dev/ram0 init=/bin/sh'
|
||||
setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz'
|
||||
setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz'
|
||||
setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2'
|
||||
setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage'
|
||||
setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage'
|
||||
setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
|
||||
setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}'
|
||||
setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}'
|
||||
setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
|
||||
setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}'
|
||||
setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
|
||||
setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}'
|
||||
setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
|
||||
setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin'
|
||||
setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}'
|
||||
setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}'
|
||||
setenv bootcmd 'run boot_tftp_flash'
|
||||
|
||||
Now you can boot from flash, ide, ide+ext2 and tfp::
|
||||
|
||||
# qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
|
||||
|
||||
|
||||
How to debug U-Boot
|
||||
-------------------
|
||||
|
||||
In order to debug U-Boot you need to start qemu with gdb server support (-s)
|
||||
and waiting the connection to start the CPU (-S)
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
|
||||
|
||||
in an other console you start gdb
|
||||
|
||||
Debugging of U-Boot Before Relocation
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Before relocation, the addresses in the ELF file can be used without any problems
|
||||
by connecting to the gdb server localhost:1234
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
# mipsel-unknown-linux-gnu-gdb u-boot
|
||||
GNU gdb 6.6
|
||||
Copyright (C) 2006 Free Software Foundation, Inc.
|
||||
GDB is free software, covered by the GNU General Public License, and you are
|
||||
welcome to change it and/or distribute copies of it under certain conditions.
|
||||
Type "show copying" to see the conditions.
|
||||
There is absolutely no warranty for GDB. Type "show warranty" for details.
|
||||
This GDB was configured as "--host=i486-linux-gnu --target=mipsel-unknown-linux-gnu"...
|
||||
(gdb) target remote localhost:1234
|
||||
Remote debugging using localhost:1234
|
||||
_start () at start.S:64
|
||||
64 RVECENT(reset,0) /* U-Boot entry point */
|
||||
Current language: auto; currently asm
|
||||
(gdb) b board.c:289
|
||||
Breakpoint 1 at 0xbfc00cc8: file board.c, line 289.
|
||||
(gdb) c
|
||||
Continuing.
|
||||
|
||||
Breakpoint 1, board_init_f (bootflag=<value optimized out>) at board.c:290
|
||||
290 relocate_code (addr_sp, id, addr);
|
||||
Current language: auto; currently c
|
||||
(gdb) p/x addr
|
||||
$1 = 0x87fa0000
|
||||
|
||||
Debugging of U-Boot After Relocation
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
For debugging U-Boot after relocation we need to know the address to which
|
||||
U-Boot relocates itself to 0x87fa0000 by default.
|
||||
And replace the symbol table to this offset.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
(gdb) symbol-file
|
||||
Discard symbol table from `/private/u-boot-arm/u-boot'? (y or n) y
|
||||
Error in re-setting breakpoint 1:
|
||||
No symbol table is loaded. Use the "file" command.
|
||||
No symbol file now.
|
||||
(gdb) add-symbol-file u-boot 0x87fa0000
|
||||
add symbol table from file "u-boot" at
|
||||
.text_addr = 0x87fa0000
|
||||
(y or n) y
|
||||
Reading symbols from /private/u-boot-arm/u-boot...done.
|
||||
Breakpoint 1 at 0x87fa0cc8: file board.c, line 289.
|
||||
(gdb) c
|
||||
Continuing.
|
||||
|
||||
Program received signal SIGINT, Interrupt.
|
||||
0xffffffff87fa0de4 in udelay (usec=<value optimized out>) at time.c:78
|
||||
78 while ((tmo - read_c0_count()) < 0x7fffffff)
|
||||
@@ -0,0 +1,107 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
|
||||
|
||||
QEMU RISC-V
|
||||
===========
|
||||
|
||||
QEMU for RISC-V supports a special 'virt' machine designed for emulation and
|
||||
virtualization purposes. This document describes how to run U-Boot under it.
|
||||
Both 32-bit and 64-bit targets are supported, running in either machine or
|
||||
supervisor mode.
|
||||
|
||||
The QEMU virt machine models a generic RISC-V virtual machine with support for
|
||||
the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
|
||||
16550A UART devices in addition to VirtIO and it also uses device-tree to pass
|
||||
configuration information to guest software. It implements RISC-V privileged
|
||||
architecture spec v1.10.
|
||||
|
||||
Building U-Boot
|
||||
---------------
|
||||
Set the CROSS_COMPILE environment variable as usual, and run:
|
||||
|
||||
- For 32-bit RISC-V::
|
||||
|
||||
make qemu-riscv32_defconfig
|
||||
make
|
||||
|
||||
- For 64-bit RISC-V::
|
||||
|
||||
make qemu-riscv64_defconfig
|
||||
make
|
||||
|
||||
This will compile U-Boot for machine mode. To build supervisor mode binaries,
|
||||
use the configurations qemu-riscv32_smode_defconfig and
|
||||
qemu-riscv64_smode_defconfig instead. Note that U-Boot running in supervisor
|
||||
mode requires a supervisor binary interface (SBI), such as RISC-V OpenSBI.
|
||||
|
||||
Running U-Boot
|
||||
--------------
|
||||
The minimal QEMU command line to get U-Boot up and running is:
|
||||
|
||||
- For 32-bit RISC-V::
|
||||
|
||||
qemu-system-riscv32 -nographic -machine virt -kernel u-boot
|
||||
|
||||
- For 64-bit RISC-V::
|
||||
|
||||
qemu-system-riscv64 -nographic -machine virt -kernel u-boot
|
||||
|
||||
The commands above create targets with 128MiB memory by default.
|
||||
A freely configurable amount of RAM can be created via the '-m'
|
||||
parameter. For example, '-m 2G' creates 2GiB memory for the target,
|
||||
and the memory node in the embedded DTB created by QEMU reflects
|
||||
the new setting.
|
||||
|
||||
For instructions on how to run U-Boot in supervisor mode on QEMU
|
||||
with OpenSBI, see the documentation available with OpenSBI:
|
||||
https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
|
||||
|
||||
These have been tested in QEMU 3.0.0.
|
||||
|
||||
Running U-Boot SPL
|
||||
------------------
|
||||
In the default SPL configuration, U-Boot SPL starts in machine mode. U-Boot
|
||||
proper and OpenSBI (FW_DYNAMIC firmware) are bundled as FIT image and made
|
||||
available to U-Boot SPL. Both are then loaded by U-Boot SPL and the location
|
||||
of U-Boot proper is passed to OpenSBI. After initialization, U-Boot proper is
|
||||
started in supervisor mode by OpenSBI.
|
||||
|
||||
OpenSBI must be compiled before compiling U-Boot. Version 0.4 and higher is
|
||||
supported by U-Boot. Clone the OpenSBI repository and run the following command.
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
git clone https://github.com/riscv/opensbi.git
|
||||
cd opensbi
|
||||
make PLATFORM=qemu/virt
|
||||
|
||||
See the OpenSBI documentation for full details:
|
||||
https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
|
||||
|
||||
To make the FW_DYNAMIC binary (build/platform/qemu/virt/firmware/fw_dynamic.bin)
|
||||
available to U-Boot, either copy it into the U-Boot root directory or specify
|
||||
its location with the OPENSBI environment variable. Afterwards, compile U-Boot
|
||||
with the following commands.
|
||||
|
||||
- For 32-bit RISC-V::
|
||||
|
||||
make qemu-riscv32_spl_defconfig
|
||||
make
|
||||
|
||||
- For 64-bit RISC-V::
|
||||
|
||||
make qemu-riscv64_spl_defconfig
|
||||
make
|
||||
|
||||
The minimal QEMU commands to run U-Boot SPL in both 32-bit and 64-bit
|
||||
configurations are:
|
||||
|
||||
- For 32-bit RISC-V::
|
||||
|
||||
qemu-system-riscv32 -nographic -machine virt -kernel spl/u-boot-spl \
|
||||
-device loader,file=u-boot.itb,addr=0x80200000
|
||||
|
||||
- For 64-bit RISC-V::
|
||||
|
||||
qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
|
||||
-device loader,file=u-boot.itb,addr=0x80200000
|
||||
@@ -0,0 +1,118 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
|
||||
|
||||
QEMU x86
|
||||
========
|
||||
|
||||
Build instructions for bare mode
|
||||
--------------------------------
|
||||
|
||||
To build u-boot.rom for QEMU x86 targets, just simply run::
|
||||
|
||||
$ make qemu-x86_defconfig (for 32-bit)
|
||||
$ make qemu-x86_64_defconfig (for 64-bit)
|
||||
$ make all
|
||||
|
||||
Note this default configuration will build a U-Boot for the QEMU x86 i440FX
|
||||
board. To build a U-Boot against QEMU x86 Q35 board, you can change the build
|
||||
configuration during the 'make menuconfig' process like below::
|
||||
|
||||
Device Tree Control --->
|
||||
...
|
||||
(qemu-x86_q35) Default Device Tree for DT control
|
||||
|
||||
Test with QEMU for bare mode
|
||||
----------------------------
|
||||
|
||||
QEMU is a fancy emulator that can enable us to test U-Boot without access to
|
||||
a real x86 board. Please make sure your QEMU version is 2.3.0 or above test
|
||||
U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows::
|
||||
|
||||
$ qemu-system-i386 -nographic -bios path/to/u-boot.rom
|
||||
|
||||
This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
|
||||
also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
|
||||
also supported by U-Boot. To instantiate such a machine, call QEMU with::
|
||||
|
||||
$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35
|
||||
|
||||
Note by default QEMU instantiated boards only have 128 MiB system memory. But
|
||||
it is enough to have U-Boot boot and function correctly. You can increase the
|
||||
system memory by pass '-m' parameter to QEMU if you want more memory::
|
||||
|
||||
$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024
|
||||
|
||||
This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only
|
||||
supports 3 GiB maximum system memory and reserves the last 1 GiB address space
|
||||
for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m'
|
||||
would be 3072.
|
||||
|
||||
QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will
|
||||
show QEMU's VGA console window. Note this will disable QEMU's serial output.
|
||||
If you want to check both consoles, use '-serial stdio'.
|
||||
|
||||
Multicore is also supported by QEMU via '-smp n' where n is the number of cores
|
||||
to instantiate. Note, the maximum supported CPU number in QEMU is 255.
|
||||
|
||||
U-Boot uses 'distro_bootcmd' by default when booting on x86 QEMU. This tries to
|
||||
load a boot script, kernel, and ramdisk from several different interfaces. For
|
||||
the default boot order, see 'qemu-x86.h'. For more information, see
|
||||
'README.distro'. Most Linux distros can be booted by writing a uboot script.
|
||||
For example, Debian (stretch) can be booted by creating a script file named
|
||||
'boot.txt' with the contents::
|
||||
|
||||
setenv bootargs root=/dev/sda1 ro
|
||||
load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} /vmlinuz
|
||||
load ${devtype} ${devnum}:${distro_bootpart} ${ramdisk_addr_r} /initrd.img
|
||||
zboot ${kernel_addr_r} - ${ramdisk_addr_r} ${filesize}
|
||||
|
||||
Then compile and install it with::
|
||||
|
||||
$ apt install u-boot-tools && \
|
||||
mkimage -T script -C none -n "Boot script" -d boot.txt /boot/boot.scr
|
||||
|
||||
The fw_cfg interface in QEMU also provides information about kernel data,
|
||||
initrd, command-line arguments and more. U-Boot supports directly accessing
|
||||
these informtion from fw_cfg interface, which saves the time of loading them
|
||||
from hard disk or network again, through emulated devices. To use it , simply
|
||||
providing them in QEMU command line::
|
||||
|
||||
$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 \
|
||||
-kernel /path/to/bzImage -append 'root=/dev/ram console=ttyS0' \
|
||||
-initrd /path/to/initrd -smp 8
|
||||
|
||||
Note: -initrd and -smp are both optional
|
||||
|
||||
Then start QEMU, in U-Boot command line use the following U-Boot command to
|
||||
setup kernel::
|
||||
|
||||
=> qfw
|
||||
qfw - QEMU firmware interface
|
||||
|
||||
Usage:
|
||||
qfw <command>
|
||||
- list : print firmware(s) currently loaded
|
||||
- cpus : print online cpu number
|
||||
- load <kernel addr> <initrd addr> : load kernel and initrd (if any) and setup for zboot
|
||||
|
||||
=> qfw load
|
||||
loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
|
||||
|
||||
Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
|
||||
'zboot' can be used to boot the kernel::
|
||||
|
||||
=> zboot 01000000 - 04000000 1b1ab50
|
||||
|
||||
To run 64-bit U-Boot, qemu-system-x86_64 should be used instead, e.g.::
|
||||
|
||||
$ qemu-system-x86_64 -nographic -bios path/to/u-boot.rom
|
||||
|
||||
A specific CPU can be specified via the '-cpu' parameter but please make
|
||||
sure the specified CPU supports 64-bit like '-cpu core2duo'. Conversely
|
||||
'-cpu pentium' won't work for obvious reasons that the processor only
|
||||
supports 32-bit.
|
||||
|
||||
Note 64-bit support is very preliminary at this point. Lots of features
|
||||
are missing in the 64-bit world. One notable feature is the VGA console
|
||||
support which is currently missing, so that you must specify '-nographic'
|
||||
to get 64-bit U-Boot up and running.
|
||||
@@ -0,0 +1,453 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
B4860QDS
|
||||
========
|
||||
|
||||
The B4860QDS is a Freescale reference board that hosts the B4860 SoC
|
||||
(and variants).
|
||||
|
||||
B4860 Overview
|
||||
--------------
|
||||
The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
|
||||
StarCore and Power Architecture® cores. It targets the broadband wireless
|
||||
infrastructure and builds upon the proven success of the existing multicore
|
||||
DSPs and Power CPUs. It is designed to bolster the rapidly changing and
|
||||
expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
|
||||
|
||||
The B4860 is a highly-integrated StarCore and Power Architecture processor that
|
||||
contains:
|
||||
|
||||
* Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
|
||||
clusters-each core runs up to 1.2 GHz, with an architecture highly optimized
|
||||
for wireless base station applications
|
||||
* Four dual-thread e6500 Power Architecture processors organized in one
|
||||
cluster-each core runs up to 1.8 GHz
|
||||
* Two DDR3/3L controllers for high-speed, industry-standard memory interface
|
||||
each runs at up to 1866.67 MHz
|
||||
* MAPLE-B3 hardware acceleration-for forward error correction schemes including
|
||||
Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
|
||||
equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
|
||||
FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
|
||||
acceleration
|
||||
* CoreNet fabric that fully supports coherency using MESI protocol between the
|
||||
e6500 cores, SC3900 FVP cores, memories and external interfaces.
|
||||
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
|
||||
non-coherent out of order transactions with prioritization and bandwidth
|
||||
allocation amongst CoreNet endpoints.
|
||||
* Data Path Acceleration Architecture, which includes the following:
|
||||
|
||||
* Frame Manager (FMan), which supports in-line packet parsing and general
|
||||
classification to enable policing and QoS-based packet distribution
|
||||
* Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
|
||||
of queue management, task management, load distribution, flow ordering,
|
||||
buffer management, and allocation tasks from the cores
|
||||
* Security engine (SEC 5.3)-crypto-acceleration for protocols such as
|
||||
IPsec, SSL, and 802.16
|
||||
* RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound
|
||||
and outbound). Supports types 5, 6 (outbound only)
|
||||
|
||||
* Large internal cache memory with snooping and stashing capabilities for
|
||||
bandwidth saving and high utilization of processor elements. The 9856-Kbyte
|
||||
internal memory space includes the following:
|
||||
|
||||
* 32 Kbyte L1 ICache per e6500/SC3900 core
|
||||
* 32 Kbyte L1 DCache per e6500/SC3900 core
|
||||
* 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
|
||||
* 2048 Kbyte unified L2 cache for the e6500 cluster
|
||||
* Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
|
||||
|
||||
* Sixteen 10-GHz SerDes lanes serving:
|
||||
|
||||
* Two Serial RapidIO interfaces
|
||||
* Each supports up to 4 lanes and a total of up to 8 lanes
|
||||
|
||||
* Up to 8-lanes Common Public Radio Interface (CPRI) controller for
|
||||
glue-less antenna connection
|
||||
* Two 10-Gbit Ethernet controllers (10GEC)
|
||||
* Six 1G/2.5-Gbit Ethernet controllers for network communications
|
||||
* PCI Express controller
|
||||
* Debug (Aurora)
|
||||
* Two OCeaN DMAs
|
||||
* Various system peripherals
|
||||
* 182 32-bit timers
|
||||
|
||||
B4860QDS Overview
|
||||
-----------------
|
||||
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
|
||||
ECC, 4 GB of memory in two ranks of 2 GB.
|
||||
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
|
||||
ECC, 2 GB of memory. Single rank.
|
||||
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
|
||||
16x16 switch VSC3316
|
||||
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
|
||||
8x8 switch VSC3308
|
||||
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
|
||||
B4860 UART port is available over USB-to-UART translator USB2SER or over
|
||||
RS232 flat cable.
|
||||
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45
|
||||
copper connectors for Stand-alone mode and to the 1000Base-X over AMC
|
||||
MicroTCA connector ports 0 and 2 for AMC mode.
|
||||
- The B4860 configuration may be loaded from nine bits coded reset configuration
|
||||
reset source. The RCW source is set by appropriate DIP-switches.
|
||||
- 16-bit NOR Flash / PROMJet
|
||||
- QIXIS 8-bit NOR Flash Emulator
|
||||
- 8-bit NAND Flash
|
||||
- 24-bit SPI Flash
|
||||
- Long address I2C EEPROM
|
||||
- Available debug interfaces are:
|
||||
|
||||
- On-board eCWTAP controller with ETH and USB I/F
|
||||
- JTAG/COP 16-pin header for any external TAP controller
|
||||
- External JTAG source over AMC to support B2B configuration
|
||||
- 70-pin Aurora debug connector
|
||||
|
||||
- QIXIS (FPGA) logic:
|
||||
- 2 KB internal memory space including
|
||||
|
||||
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
|
||||
DDRCLK1,2 and RTCCLK.
|
||||
- Two 8T49N222A SerDes ref clock devices support two SerDes port clock
|
||||
frequency - total four refclk, including CPRI clock scheme.
|
||||
|
||||
|
||||
B4420 Personality
|
||||
-----------------
|
||||
|
||||
B4420 is a reduced personality of B4860 with less core/clusters(both SC3900
|
||||
and e6500), less DDR controllers, less serdes lanes, less SGMII interfaces
|
||||
and reduced target frequencies.
|
||||
|
||||
Key differences between B4860 and B4420
|
||||
---------------------------------------
|
||||
|
||||
B4420 has:
|
||||
|
||||
1. Less e6500 cores: 1 cluster with 2 e6500 cores
|
||||
2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster
|
||||
3. Single DDRC
|
||||
4. 2X 4 lane serdes
|
||||
5. 3 SGMII interfaces
|
||||
6. no sRIO
|
||||
7. no 10G
|
||||
|
||||
B4860QDS Default Settings
|
||||
-------------------------
|
||||
|
||||
Switch Settings
|
||||
---------------
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
|
||||
SW2 ON ON ON ON ON ON OFF OFF
|
||||
SW3 OFF OFF OFF ON OFF OFF ON OFF
|
||||
SW5 OFF OFF OFF OFF OFF OFF ON ON
|
||||
|
||||
Note:
|
||||
|
||||
- PCIe slots modes: All the PCIe devices work as Root Complex.
|
||||
- Boot location: NOR flash.
|
||||
|
||||
SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
|
||||
66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
|
||||
|
||||
NAND boot::
|
||||
|
||||
SW1 [1.1] = 0
|
||||
SW2 [1.1] = 1
|
||||
SW3 [1:4] = 0001
|
||||
|
||||
NOR boot::
|
||||
|
||||
SW1 [1.1] = 1
|
||||
SW2 [1.1] = 0
|
||||
SW3 [1:4] = 1000
|
||||
|
||||
B4420QDS Default Settings
|
||||
-------------------------
|
||||
|
||||
Switch Settings
|
||||
---------------
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
|
||||
SW2 ON OFF ON OFF ON ON OFF OFF
|
||||
SW3 OFF OFF OFF ON OFF OFF ON OFF
|
||||
SW5 OFF OFF OFF OFF OFF OFF ON ON
|
||||
|
||||
Note:
|
||||
|
||||
- PCIe slots modes: All the PCIe devices work as Root Complex.
|
||||
- Boot location: NOR flash.
|
||||
|
||||
SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
|
||||
66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
|
||||
|
||||
NAND boot::
|
||||
|
||||
SW1 [1.1] = 0
|
||||
SW2 [1.1] = 1
|
||||
SW3 [1:4] = 0001
|
||||
|
||||
NOR boot::
|
||||
|
||||
SW1 [1.1] = 1
|
||||
SW2 [1.1] = 0
|
||||
SW3 [1:4] = 1000
|
||||
|
||||
Memory map on B4860QDS
|
||||
----------------------
|
||||
The addresses in brackets are physical addresses.
|
||||
|
||||
============= ============= =============== =======
|
||||
Start Address End Address Description Size
|
||||
============= ============= =============== =======
|
||||
0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
|
||||
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
|
||||
0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
|
||||
0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
|
||||
0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
|
||||
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
|
||||
0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
|
||||
0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
|
||||
0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
|
||||
0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
|
||||
0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
|
||||
0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
|
||||
0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
|
||||
0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
|
||||
0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
|
||||
0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
|
||||
0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
|
||||
0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
|
||||
0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
|
||||
0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
|
||||
0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
|
||||
0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
|
||||
0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB
|
||||
0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB
|
||||
============= ============= =============== =======
|
||||
|
||||
Memory map on B4420QDS
|
||||
----------------------
|
||||
The addresses in brackets are physical addresses.
|
||||
|
||||
============= ============= =============== =======
|
||||
Start Address End Address Description Size
|
||||
============= ============= =============== =======
|
||||
0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
|
||||
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
|
||||
0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
|
||||
0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
|
||||
0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
|
||||
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
|
||||
0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
|
||||
0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
|
||||
0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
|
||||
0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
|
||||
0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
|
||||
0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
|
||||
0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
|
||||
0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
|
||||
0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
|
||||
0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
|
||||
0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
|
||||
0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
|
||||
0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
|
||||
0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
|
||||
0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
|
||||
0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
|
||||
0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB
|
||||
============= ============= =============== =======
|
||||
|
||||
NOR Flash memory Map on B4860 and B4420QDS
|
||||
------------------------------------------
|
||||
|
||||
============= ============= ============================== =========
|
||||
Start End Definition Size
|
||||
============= ============= ============================== =========
|
||||
0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
|
||||
0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
|
||||
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
|
||||
0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
|
||||
0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
|
||||
0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
|
||||
0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
|
||||
0xEDF40000 0xEDFFFFFF U-Boot (alternate bank) 768KB
|
||||
0xEDF20000 0xEDF3FFFF U-Boot env (alternate bank) 128KB
|
||||
0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
|
||||
0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
|
||||
0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
|
||||
0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
|
||||
0xEC000000 0xEC01FFFF RCW (current bank) 128KB
|
||||
============= ============= ============================== =========
|
||||
|
||||
Various Software configurations/environment variables/commands
|
||||
--------------------------------------------------------------
|
||||
The below commands apply to both B4860QDS and B4420QDS.
|
||||
|
||||
U-Boot environment variable hwconfig
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The default hwconfig is:
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:dr_mode=host,phy_type=ulpi
|
||||
|
||||
Note: For USB gadget set "dr_mode=peripheral"
|
||||
|
||||
FMAN Ucode versions
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
fsl_fman_ucode_B4860_106_3_6.bin
|
||||
|
||||
Switching to alternate bank
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Commands for switching to alternate bank.
|
||||
|
||||
1. To change from vbank0 to vbank2
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> qixis_reset altbank (it will boot using vbank2)
|
||||
|
||||
2. To change from vbank2 to vbank0
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> qixis reset (it will boot using vbank0)
|
||||
|
||||
To change personality of board
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
For changing personality from B4860 to B4420
|
||||
|
||||
1. Boot from vbank0
|
||||
2. Flash vbank2 with b4420 rcw and U-Boot
|
||||
3. Give following commands to uboot prompt
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> mw.b ffdf0040 0x30;
|
||||
=> mw.b ffdf0010 0x00;
|
||||
=> mw.b ffdf0062 0x02;
|
||||
=> mw.b ffdf0050 0x02;
|
||||
=> mw.b ffdf0010 0x30;
|
||||
=> reset
|
||||
|
||||
Note:
|
||||
|
||||
- Power off cycle will lead to default switch settings.
|
||||
- 0xffdf0000 is the address of the QIXIS FPGA.
|
||||
|
||||
Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
To change from NOR to NAND boot give following command on uboot prompt
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> mw.b ffdf0040 0x30
|
||||
=> mw.b ffdf0010 0x00
|
||||
=> mw.b 0xffdf0050 0x08
|
||||
=> mw.b 0xffdf0060 0x82
|
||||
=> mw.b ffdf0061 0x00
|
||||
=> mw.b ffdf0010 0x30
|
||||
=> reset
|
||||
|
||||
To change from NAND to NOR boot give following command on uboot prompt:
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> mw.b ffdf0040 0x30
|
||||
=> mw.b ffdf0010 0x00
|
||||
=> mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
|
||||
=> mw.b 0xffdf0060 0x12
|
||||
=> mw.b ffdf0061 0x01
|
||||
=> mw.b ffdf0010 0x30
|
||||
=> reset
|
||||
|
||||
Note:
|
||||
|
||||
- Power off cycle will lead to default switch settings.
|
||||
- 0xffdf0000 is the address of the QIXIS FPGA.
|
||||
|
||||
Ethernet interfaces for B4860QDS
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Serdes protocosl tested:
|
||||
* 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
|
||||
* 0x2a, 0xb2 (serdes1, serdes2)
|
||||
|
||||
When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
|
||||
SGMII on SGMII riser card.
|
||||
|
||||
Under U-Boot these network interfaces are recognized as::
|
||||
|
||||
FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
|
||||
|
||||
On Linux the interfaces are renamed as::
|
||||
|
||||
eth2 -> fm1-gb2
|
||||
eth3 -> fm1-gb3
|
||||
eth4 -> fm1-gb4
|
||||
eth5 -> fm1-gb5
|
||||
|
||||
RCW and Ethernet interfaces for B4420QDS
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Serdes protocosl tested:
|
||||
* 0x18, 0x9e (serdes1, serdes2)
|
||||
|
||||
Under U-Boot these network interfaces are recognized as::
|
||||
|
||||
FM1@DTSEC3, FM1@DTSEC4 and e1000#0.
|
||||
|
||||
On Linux the interfaces are renamed as::
|
||||
|
||||
eth2 -> fm1-gb2
|
||||
eth3 -> fm1-gb3
|
||||
|
||||
NAND boot with 2 Stage boot loader
|
||||
----------------------------------
|
||||
PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
|
||||
SPL further initialise DDR using SPD and environment variables and copy
|
||||
U-Boot(768 KB) from flash to DDR.
|
||||
Finally SPL transer control to U-Boot for futher booting.
|
||||
|
||||
SPL has following features:
|
||||
- Executes within 256K
|
||||
- No relocation required
|
||||
|
||||
Run time view of SPL framework during boot:
|
||||
|
||||
+----------------------------------------------+
|
||||
|Area | Address |
|
||||
+----------------------------------------------+
|
||||
|Secure boot | 0xFFFC0000 (32KB) |
|
||||
|headers | |
|
||||
+----------------------------------------------+
|
||||
|GD, BD | 0xFFFC8000 (4KB) |
|
||||
+----------------------------------------------+
|
||||
|ENV | 0xFFFC9000 (8KB) |
|
||||
+----------------------------------------------+
|
||||
|HEAP | 0xFFFCB000 (30KB) |
|
||||
+----------------------------------------------+
|
||||
|STACK | 0xFFFD8000 (22KB) |
|
||||
+----------------------------------------------+
|
||||
|U-Boot SPL | 0xFFFD8000 (160KB) |
|
||||
+----------------------------------------------+
|
||||
|
||||
NAND Flash memory Map on B4860 and B4420QDS
|
||||
-------------------------------------------
|
||||
|
||||
============= ============= ============================= =====
|
||||
Start End Definition Size
|
||||
============= ============= ============================= =====
|
||||
0x000000 0x0FFFFF U-Boot 1MB
|
||||
0x140000 0x15FFFF U-Boot env 128KB
|
||||
0x1A0000 0x1BFFFF FMAN Ucode 128KB
|
||||
============= ============= ============================= =====
|
||||
@@ -0,0 +1,9 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Freescale
|
||||
=========
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
b4860qds
|
||||
@@ -0,0 +1,34 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Simon Glass <sjg@chromium.org>
|
||||
|
||||
Chromebook Link
|
||||
===============
|
||||
|
||||
First, you need the following binary blobs:
|
||||
|
||||
* descriptor.bin - Intel flash descriptor
|
||||
* me.bin - Intel Management Engine
|
||||
* mrc.bin - Memory Reference Code, which sets up SDRAM
|
||||
* video ROM - sets up the display
|
||||
|
||||
You can get these binary blobs by::
|
||||
|
||||
$ git clone http://review.coreboot.org/p/blobs.git
|
||||
$ cd blobs
|
||||
|
||||
Find the following files:
|
||||
|
||||
* ./mainboard/google/link/descriptor.bin
|
||||
* ./mainboard/google/link/me.bin
|
||||
* ./northbridge/intel/sandybridge/systemagent-r6.bin
|
||||
|
||||
The 3rd one should be renamed to mrc.bin.
|
||||
As for the video ROM, you can get it `here`_ and rename it to vga.bin.
|
||||
Make sure all these binary blobs are put in the board directory.
|
||||
|
||||
Now you can build U-Boot and obtain u-boot.rom::
|
||||
|
||||
$ make chromebook_link_defconfig
|
||||
$ make all
|
||||
|
||||
.. _here: http://www.coreboot.org/~stepan/pci8086,0166.rom
|
||||
@@ -0,0 +1,101 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Simon Glass <sjg@chromium.org>
|
||||
|
||||
Chromebook Samus
|
||||
================
|
||||
|
||||
First, you need the following binary blobs:
|
||||
|
||||
* descriptor.bin - Intel flash descriptor
|
||||
* me.bin - Intel Management Engine
|
||||
* mrc.bin - Memory Reference Code, which sets up SDRAM
|
||||
* refcode.elf - Additional Reference code
|
||||
* vga.bin - video ROM, which sets up the display
|
||||
|
||||
If you have a samus you can obtain them from your flash, for example, in
|
||||
developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
|
||||
log in as 'root')::
|
||||
|
||||
cd /tmp
|
||||
flashrom -w samus.bin
|
||||
scp samus.bin username@ip_address:/path/to/somewhere
|
||||
|
||||
If not see the coreboot tree where you can use::
|
||||
|
||||
bash crosfirmware.sh samus
|
||||
|
||||
to get the image. There is also an 'extract_blobs.sh' scripts that you can use
|
||||
on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
|
||||
|
||||
Then 'ifdtool -x samus.bin' on your development machine will produce::
|
||||
|
||||
flashregion_0_flashdescriptor.bin
|
||||
flashregion_1_bios.bin
|
||||
flashregion_2_intel_me.bin
|
||||
|
||||
Rename flashregion_0_flashdescriptor.bin to descriptor.bin
|
||||
Rename flashregion_2_intel_me.bin to me.bin
|
||||
You can ignore flashregion_1_bios.bin - it is not used.
|
||||
|
||||
To get the rest, use 'cbfstool samus.bin print'::
|
||||
|
||||
samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
|
||||
alignment: 64 bytes, architecture: x86
|
||||
|
||||
============================ ======== =========== ======
|
||||
Name Offset Type Size
|
||||
============================ ======== =========== ======
|
||||
cmos_layout.bin 0x700000 cmos_layout 1164
|
||||
pci8086,0406.rom 0x7004c0 optionrom 65536
|
||||
spd.bin 0x710500 (unknown) 4096
|
||||
cpu_microcode_blob.bin 0x711540 microcode 70720
|
||||
fallback/romstage 0x722a00 stage 54210
|
||||
fallback/ramstage 0x72fe00 stage 96382
|
||||
config 0x7476c0 raw 6075
|
||||
fallback/vboot 0x748ec0 stage 15980
|
||||
fallback/refcode 0x74cd80 stage 75578
|
||||
fallback/payload 0x75f500 payload 62878
|
||||
u-boot.dtb 0x76eb00 (unknown) 5318
|
||||
(empty) 0x770000 null 196504
|
||||
mrc.bin 0x79ffc0 (unknown) 222876
|
||||
(empty) 0x7d66c0 null 167320
|
||||
============================ ======== =========== ======
|
||||
|
||||
You can extract what you need::
|
||||
|
||||
cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
|
||||
cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
|
||||
cbfstool samus.bin extract -n mrc.bin -f mrc.bin
|
||||
cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
|
||||
|
||||
Note that the -U flag is only supported by the latest cbfstool. It unpacks
|
||||
and decompresses the stage to produce a coreboot rmodule. This is a simple
|
||||
representation of an ELF file. You need the patch "Support decoding a stage
|
||||
with compression".
|
||||
|
||||
Put all 5 files into board/google/chromebook_samus.
|
||||
|
||||
Now you can build U-Boot and obtain u-boot.rom::
|
||||
|
||||
$ make chromebook_samus_defconfig
|
||||
$ make all
|
||||
|
||||
If you are using em100, then this command will flash write -Boot::
|
||||
|
||||
em100 -s -d filename.rom -c W25Q64CV -r
|
||||
|
||||
Flash map for samus / broadwell:
|
||||
|
||||
:fffff800: SYS_X86_START16
|
||||
:ffff0000: RESET_SEG_START
|
||||
:fffd8000: TPL_TEXT_BASE
|
||||
:fffa0000: X86_MRC_ADDR
|
||||
:fff90000: VGA_BIOS_ADDR
|
||||
:ffed0000: SYS_TEXT_BASE
|
||||
:ffea0000: X86_REFCODE_ADDR
|
||||
:ffe70000: SPL_TEXT_BASE
|
||||
:ffbf8000: CONFIG_ENV_OFFSET (environemnt offset)
|
||||
:ffbe0000: rw-mrc-cache (Memory-reference-code cache)
|
||||
:ffa00000: <spare>
|
||||
:ff801000: intel-me (address set by descriptor.bin)
|
||||
:ff800000: intel-descriptor
|
||||
@@ -0,0 +1,10 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Google
|
||||
======
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
chromebook_link
|
||||
chromebook_samus
|
||||
@@ -0,0 +1,18 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Board-specific doc
|
||||
==================
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
AndesTech/index
|
||||
atmel/index
|
||||
coreboot/index
|
||||
emulation/index
|
||||
freescale/index
|
||||
google/index
|
||||
intel/index
|
||||
renesas/index
|
||||
sifive/index
|
||||
xilinx/index
|
||||
@@ -0,0 +1,29 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
|
||||
|
||||
Bayley Bay CRB
|
||||
==============
|
||||
|
||||
This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
|
||||
Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
|
||||
the time of writing). Put it in the corresponding board directory and rename
|
||||
it to fsp.bin.
|
||||
|
||||
Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
|
||||
board directory as vga.bin.
|
||||
|
||||
You still need two more binary blobs. For Bayley Bay, they can be extracted
|
||||
from the sample SPI image provided in the FSP (SPI.bin at the time of writing)::
|
||||
|
||||
$ ./tools/ifdtool -x BayleyBay/SPI.bin
|
||||
$ cp flashregion_0_flashdescriptor.bin board/intel/bayleybay/descriptor.bin
|
||||
$ cp flashregion_2_intel_me.bin board/intel/bayleybay/me.bin
|
||||
|
||||
Now you can build U-Boot and obtain u-boot.rom::
|
||||
|
||||
$ make bayleybay_defconfig
|
||||
$ make all
|
||||
|
||||
Note that the debug version of the FSP is bigger in size. If this version
|
||||
is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
|
||||
the default value 0xfffc0000.
|
||||
@@ -0,0 +1,30 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
|
||||
|
||||
Cherry Hill CRB
|
||||
===============
|
||||
|
||||
This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
|
||||
put the .fd file to the board directory and rename it to fsp.bin.
|
||||
|
||||
Extract descriptor.bin and me.bin from the original BIOS on the board using
|
||||
ifdtool and put them to the board directory as well.
|
||||
|
||||
Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
|
||||
image for the integrated graphics device. Instead a new binary called Video
|
||||
BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
|
||||
vbt.bin if you want graphics support in U-Boot.
|
||||
|
||||
Now you can build U-Boot and obtain u-boot.rom::
|
||||
|
||||
$ make cherryhill_defconfig
|
||||
$ make all
|
||||
|
||||
An important note for programming u-boot.rom to the on-board SPI flash is that
|
||||
you need make sure the SPI flash's 'quad enable' bit in its status register
|
||||
matches the settings in the descriptor.bin, otherwise the board won't boot.
|
||||
|
||||
For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
|
||||
status register by DediProg in: Config > Modify Status Register > Write Status
|
||||
Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
|
||||
persists in SPI flash part regardless of the u-boot.rom image burned.
|
||||
@@ -0,0 +1,24 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
|
||||
|
||||
Cougar Canyon 2 CRB
|
||||
===================
|
||||
|
||||
This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
|
||||
with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
|
||||
website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
|
||||
time of writing) in the board directory and rename it to fsp.bin.
|
||||
|
||||
Now build U-Boot and obtain u-boot.rom::
|
||||
|
||||
$ make cougarcanyon2_defconfig
|
||||
$ make all
|
||||
|
||||
The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
|
||||
the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
|
||||
and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
|
||||
flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
|
||||
this image to the SPI-0 flash according to the board manual just once and we are
|
||||
all set. For programming U-Boot we just need to program SPI-1 flash. Since the
|
||||
default u-boot.rom image for this board is set to 2MB, it should be programmed
|
||||
to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
|
||||
@@ -0,0 +1,43 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
|
||||
|
||||
Crown Bay CRB
|
||||
=============
|
||||
|
||||
U-Boot support of Intel `Crown Bay`_ board relies on a binary blob called
|
||||
Firmware Support Package (`FSP`_) to perform all the necessary initialization
|
||||
steps as documented in the BIOS Writer Guide, including initialization of the
|
||||
CPU, memory controller, chipset and certain bus interfaces.
|
||||
|
||||
Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
|
||||
install it on your host and locate the FSP binary blob. Note this platform
|
||||
also requires a Chipset Micro Code (CMC) state machine binary to be present in
|
||||
the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
|
||||
in this FSP package too.
|
||||
|
||||
* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
|
||||
* ./Microcode/C0_22211.BIN
|
||||
|
||||
Rename the first one to fsp.bin and second one to cmc.bin and put them in the
|
||||
board directory.
|
||||
|
||||
Note the FSP release version 001 has a bug which could cause random endless
|
||||
loop during the FspInit call. This bug was published by Intel although Intel
|
||||
did not describe any details. We need manually apply the patch to the FSP
|
||||
binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
|
||||
binary, change the following five bytes values from orginally E8 42 FF FF FF
|
||||
to B8 00 80 0B 00.
|
||||
|
||||
As for the video ROM, you need manually extract it from the Intel provided
|
||||
BIOS for Crown Bay `here`_, using the AMI `MMTool`_. Check PCI option
|
||||
ROM ID 8086:4108, extract and save it as vga.bin in the board directory.
|
||||
|
||||
Now you can build U-Boot and obtain u-boot.rom::
|
||||
|
||||
$ make crownbay_defconfig
|
||||
$ make all
|
||||
|
||||
.. _`Crown Bay`: http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
|
||||
.. _`FSP`: http://www.intel.com/fsp
|
||||
.. _`here`: http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html
|
||||
.. _`MMTool`: http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/
|
||||
@@ -0,0 +1,41 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
|
||||
Edison
|
||||
======
|
||||
|
||||
Build Instructions for U-Boot as main bootloader
|
||||
------------------------------------------------
|
||||
|
||||
Simple you can build U-Boot and obtain u-boot.bin::
|
||||
|
||||
$ make edison_defconfig
|
||||
$ make all
|
||||
|
||||
Updating U-Boot on Edison
|
||||
-------------------------
|
||||
|
||||
By default Intel Edison boards are shipped with preinstalled heavily
|
||||
patched U-Boot v2014.04. Though it supports DFU which we may be able to
|
||||
use.
|
||||
|
||||
1. Prepare u-boot.bin as described in chapter above. You still need one
|
||||
more step (if and only if you have original U-Boot), i.e. run the
|
||||
following command::
|
||||
|
||||
$ truncate -s %4096 u-boot.bin
|
||||
|
||||
2. Run your board and interrupt booting to U-Boot console. In the console
|
||||
call::
|
||||
|
||||
=> run do_force_flash_os
|
||||
|
||||
3. Wait for few seconds, it will prepare environment variable and runs
|
||||
DFU. Run DFU command from the host system::
|
||||
|
||||
$ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin
|
||||
|
||||
4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and
|
||||
reset the board::
|
||||
|
||||
=> reset
|
||||
@@ -0,0 +1,22 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
|
||||
|
||||
Galileo
|
||||
=======
|
||||
|
||||
Only one binary blob is needed for Remote Management Unit (RMU) within Intel
|
||||
Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
|
||||
needed by the Quark SoC itself.
|
||||
|
||||
You can get the binary blob from Quark Board Support Package from Intel website:
|
||||
|
||||
* ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
|
||||
|
||||
Rename the file and put it to the board directory by::
|
||||
|
||||
$ cp RMU.bin board/intel/galileo/rmu.bin
|
||||
|
||||
Now you can build U-Boot and obtain u-boot.rom::
|
||||
|
||||
$ make galileo_defconfig
|
||||
$ make all
|
||||
@@ -0,0 +1,16 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Intel
|
||||
=====
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
bayleybay
|
||||
cherryhill
|
||||
cougarcanyon2
|
||||
crownbay
|
||||
edison
|
||||
galileo
|
||||
minnowmax
|
||||
slimbootloader
|
||||
@@ -0,0 +1,70 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Simon Glass <sjg@chromium.org>
|
||||
|
||||
Minnowboard MAX
|
||||
===============
|
||||
|
||||
This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
|
||||
Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
|
||||
the time of writing). Put it in the corresponding board directory and rename
|
||||
it to fsp.bin.
|
||||
|
||||
Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
|
||||
board directory as vga.bin.
|
||||
|
||||
You still need two more binary blobs. For Minnowboard MAX, we can reuse the
|
||||
same ME firmware above, but for flash descriptor, we need get that somewhere
|
||||
else, as the one above does not seem to work, probably because it is not
|
||||
designed for the Minnowboard MAX. Now download the original firmware image
|
||||
for this board from:
|
||||
|
||||
* http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
|
||||
|
||||
Unzip it::
|
||||
|
||||
$ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
|
||||
|
||||
Use ifdtool in the U-Boot tools directory to extract the images from that
|
||||
file, for example::
|
||||
|
||||
$ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
|
||||
|
||||
This will provide the descriptor file - copy this into the correct place::
|
||||
|
||||
$ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
|
||||
|
||||
Now you can build U-Boot and obtain u-boot.rom::
|
||||
|
||||
$ make minnowmax_defconfig
|
||||
$ make all
|
||||
|
||||
Checksums are as follows (but note that newer versions will invalidate this)::
|
||||
|
||||
$ md5sum -b board/intel/minnowmax/*.bin
|
||||
ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin
|
||||
69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
|
||||
894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin
|
||||
a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin
|
||||
|
||||
The ROM image is broken up into these parts:
|
||||
|
||||
====== ================== ============================
|
||||
Offset Description Controlling config
|
||||
====== ================== ============================
|
||||
000000 descriptor.bin Hard-coded to 0 in ifdtool
|
||||
001000 me.bin Set by the descriptor
|
||||
500000 <spare>
|
||||
6ef000 Environment CONFIG_ENV_OFFSET
|
||||
6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE
|
||||
700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
|
||||
7b0000 vga.bin CONFIG_VGA_BIOS_ADDR
|
||||
7c0000 fsp.bin CONFIG_FSP_ADDR
|
||||
7f8000 <spare> (depends on size of fsp.bin)
|
||||
7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
|
||||
====== ================== ============================
|
||||
|
||||
Overall ROM image size is controlled by CONFIG_ROM_SIZE.
|
||||
|
||||
Note that the debug version of the FSP is bigger in size. If this version
|
||||
is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
|
||||
the default value 0xfffc0000.
|
||||
@@ -0,0 +1,196 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. sectionauthor:: Aiden Park <aiden.park@intel.com>
|
||||
|
||||
Slim Bootloader
|
||||
===============
|
||||
|
||||
Introduction
|
||||
------------
|
||||
|
||||
This target is to enable U-Boot_ as a payload of `Slim Bootloader`_ (a.k.a SBL)
|
||||
boot firmware which currently supports QEMU, Apollolake, Whiskeylake,
|
||||
Coffeelake-R platforms.
|
||||
|
||||
The `Slim Bootloader`_ is designed with multi-stages (Stage1A/B, Stage2, Payload)
|
||||
architecture to cover from reset vector to OS booting and it consumes
|
||||
`Intel FSP`_ for silicon initialization.
|
||||
|
||||
* Stage1A: Reset vector, CAR init with FSP-T
|
||||
* Stage1B: Memory init with FSP-M, CAR teardown, Continue execution in memory
|
||||
* Stage2 : Rest of Silicon init with FSP-S, Create HOB, Hand-off to Payload
|
||||
* Payload: Payload init with HOB, Load OS from media, Booting OS
|
||||
|
||||
The Slim Bootloader stages (Stage1A/B, Stage2) focus on chipset, hardware and
|
||||
platform specific initialization, and it provides useful information to a
|
||||
payload in a HOB (Hand-Off Block) which has serial port, memory map, performance
|
||||
data info and so on. This is Slim Bootloader architectural design to make a
|
||||
payload light-weight, platform independent and more generic across different
|
||||
boot solutions or payloads, and to minimize hardware re-initialization in a
|
||||
payload.
|
||||
|
||||
Build Instruction for U-Boot as a Slim Bootloader payload
|
||||
---------------------------------------------------------
|
||||
|
||||
Build U-Boot and obtain u-boot-dtb.bin::
|
||||
|
||||
$ make distclean
|
||||
$ make slimbootloader_defconfig
|
||||
$ make all
|
||||
|
||||
Prepare Slim Bootloader
|
||||
-----------------------
|
||||
|
||||
1. Setup Build Environment for Slim Bootloader.
|
||||
|
||||
Refer to `Getting Started`_ page in `Slim Bootloader`_ document site.
|
||||
|
||||
2. Get source code. Let's simply clone the repo::
|
||||
|
||||
$ git clone https://github.com/slimbootloader/slimbootloader.git
|
||||
|
||||
3. Copy u-boot-dtb.bin to Slim Bootloader.
|
||||
Slim Bootloader looks for a payload from the specific location.
|
||||
Copy the build u-boot-dtb.bin to the expected location::
|
||||
|
||||
$ mkdir -p <Slim Bootloader Dir>/PayloadPkg/PayloadBins/
|
||||
$ cp <U-Boot Dir>/u-boot-dtb.bin <Slim Bootloader Dir>/PayloadPkg/PayloadBins/u-boot-dtb.bin
|
||||
|
||||
Build Instruction for Slim Bootloader for QEMU target
|
||||
-----------------------------------------------------
|
||||
|
||||
Slim Bootloader supports multiple payloads, and a board of Slim Bootloader
|
||||
detects its target payload by PayloadId in board configuration.
|
||||
The PayloadId can be any 4 Bytes value.
|
||||
|
||||
1. Update PayloadId. Let's use 'U-BT' as an example::
|
||||
|
||||
$ vi Platform/QemuBoardPkg/CfgData/CfgDataExt_Brd1.dlt
|
||||
-GEN_CFG_DATA.PayloadId | 'AUTO'
|
||||
+GEN_CFG_DATA.PayloadId | 'U-BT'
|
||||
|
||||
2. Update payload text base. PAYLOAD_EXE_BASE must be the same as U-Boot
|
||||
CONFIG_SYS_TEXT_BASE in board/intel/slimbootloader/Kconfig.
|
||||
PAYLOAD_LOAD_HIGH must be 0::
|
||||
|
||||
$ vi Platform/QemuBoardPkg/BoardConfig.py
|
||||
+ self.PAYLOAD_LOAD_HIGH = 0
|
||||
+ self.PAYLOAD_EXE_BASE = 0x00100000
|
||||
|
||||
3. Build QEMU target. Make sure u-boot-dtb.bin and U-BT PayloadId
|
||||
in build command. The output is Outputs/qemu/SlimBootloader.bin::
|
||||
|
||||
$ python BuildLoader.py build qemu -p "OsLoader.efi:LLDR:Lz4;u-boot-dtb.bin:U-BT:Lzma"
|
||||
|
||||
4. Launch Slim Bootloader on QEMU.
|
||||
You should reach at U-Boot serial console::
|
||||
|
||||
$ qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio -pflash Outputs/qemu/SlimBootloader.bin
|
||||
|
||||
Test Linux booting on QEMU target
|
||||
---------------------------------
|
||||
|
||||
Let's use LeafHill (APL) Yocto image for testing.
|
||||
Download it from http://downloads.yoctoproject.org/releases/yocto/yocto-2.0/machines/leafhill/.
|
||||
|
||||
1. Prepare Yocto hard disk image::
|
||||
|
||||
$ wget http://downloads.yoctoproject.org/releases/yocto/yocto-2.0/machines/leafhill/leafhill-4.0-jethro-2.0.tar.bz2
|
||||
$ tar -xvf leafhill-4.0-jethro-2.0.tar.bz2
|
||||
$ ls -l leafhill-4.0-jethro-2.0/binary/core-image-sato-intel-corei7-64.hddimg
|
||||
|
||||
2. Launch Slim Bootloader on QEMU with disk image::
|
||||
|
||||
$ qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio -pflash Outputs/qemu/SlimBootloader.bin -drive id=mydrive,if=none,file=/path/to/core-image-sato-intel-corei7-64.hddimg,format=raw -device ide-hd,drive=mydrive
|
||||
|
||||
3. Update boot environment values on shell::
|
||||
|
||||
=> setenv bootfile vmlinuz
|
||||
=> setenv bootdev scsi
|
||||
=> boot
|
||||
|
||||
Build Instruction for Slim Bootloader for LeafHill (APL) target
|
||||
---------------------------------------------------------------
|
||||
|
||||
LeafHill is using PCI UART2 device as a serial port.
|
||||
For MEM32 serial port, CONFIG_SYS_NS16550_MEM32 needs to be enabled in U-Boot.
|
||||
|
||||
1. Enable CONFIG_SYS_NS16550_MEM32 in U-Boot::
|
||||
|
||||
$ vi include/configs/slimbootloader.h
|
||||
+#define CONFIG_SYS_NS16550_MEM32
|
||||
#ifdef CONFIG_SYS_NS16550_MEM3
|
||||
|
||||
2. Build U-Boot::
|
||||
|
||||
$ make disclean
|
||||
$ make slimbootloader_defconfig
|
||||
$ make all
|
||||
|
||||
3. Copy u-boot-dtb.bin to Slim Bootloader.
|
||||
Slim Bootloader looks for a payload from the specific location.
|
||||
Copy the build u-boot-dtb.bin to the expected location::
|
||||
|
||||
$ mkdir -p <Slim Bootloader Dir>/PayloadPkg/PayloadBins/
|
||||
$ cp <U-Boot Dir>/u-boot-dtb.bin <Slim Bootloader Dir>/PayloadPkg/PayloadBins/u-boot-dtb.bin
|
||||
|
||||
4. Update PayloadId. Let's use 'U-BT' as an example::
|
||||
|
||||
$ vi Platform/ApollolakeBoardPkg/CfgData/CfgData_Int_LeafHill.dlt
|
||||
-GEN_CFG_DATA.PayloadId | 'AUTO
|
||||
+GEN_CFG_DATA.PayloadId | 'U-BT'
|
||||
|
||||
5. Update payload text base.
|
||||
|
||||
* PAYLOAD_EXE_BASE must be the same as U-Boot CONFIG_SYS_TEXT_BASE
|
||||
in board/intel/slimbootloader/Kconfig.
|
||||
* PAYLOAD_LOAD_HIGH must be 0::
|
||||
|
||||
$ vi Platform/ApollolakeBoardPkg/BoardConfig.py
|
||||
+ self.PAYLOAD_LOAD_HIGH = 0
|
||||
+ self.PAYLOAD_EXE_BASE = 0x00100000
|
||||
|
||||
6. Build APL target. Make sure u-boot-dtb.bin and U-BT PayloadId
|
||||
in build command. The output is Outputs/apl/Stitch_Components.zip::
|
||||
|
||||
$ python BuildLoader.py build apl -p "OsLoader.efi:LLDR:Lz4;u-boot-dtb.bin:U-BT:Lzma"
|
||||
|
||||
7. Stitch IFWI.
|
||||
|
||||
Refer to Apollolake_ page in Slim Bootloader document site::
|
||||
|
||||
$ python Platform/ApollolakeBoardPkg/Script/StitchLoader.py -i <Existing IFWI> -s Outputs/apl/Stitch_Components.zip -o <Output IFWI>
|
||||
|
||||
8. Flash IFWI.
|
||||
|
||||
Use DediProg to flash IFWI. You should reach at U-Boot serial console.
|
||||
|
||||
|
||||
Build Instruction to use ELF U-Boot
|
||||
-----------------------------------
|
||||
|
||||
1. Enable CONFIG_OF_EMBED::
|
||||
|
||||
$ vi configs/slimbootloader_defconfig
|
||||
+CONFIG_OF_EMBED=y
|
||||
|
||||
2. Build U-Boot::
|
||||
|
||||
$ make disclean
|
||||
$ make slimbootloader_defconfig
|
||||
$ make all
|
||||
$ strip u-boot (removing symbol for reduced size)
|
||||
|
||||
3. Do same steps as above
|
||||
|
||||
* Copy u-boot (ELF) to PayloadBins directory
|
||||
* Update PayloadId 'U-BT' as above.
|
||||
* No need to set PAYLOAD_LOAD_HIGH and PAYLOAD_EXE_BASE.
|
||||
* Build Slim Bootloader. Use u-boot instead of u-boot-dtb.bin::
|
||||
|
||||
$ python BuildLoader.py build <qemu or apl> -p "OsLoader.efi:LLDR:Lz4;u-boot:U-BT:Lzma"
|
||||
|
||||
.. _U-Boot: https://gitlab.denx.de/
|
||||
.. _`Slim Bootloader`: https://github.com/slimbootloader/
|
||||
.. _`Intel FSP`: https://github.com/IntelFsp/
|
||||
.. _`Getting Started`: https://slimbootloader.github.io/getting-started/
|
||||
.. _Apollolake: https://slimbootloader.github.io/supported-hardware/apollo-lake-crb.html#stitching
|
||||
@@ -0,0 +1,10 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Renesas
|
||||
=======
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
sh7752evb
|
||||
sh7753evb
|
||||
@@ -0,0 +1,79 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
R0P7752C00000RZ board
|
||||
=====================
|
||||
|
||||
This board specification
|
||||
------------------------
|
||||
|
||||
The R0P7752C00000RZ(board config name:sh7752evb) has the following device:
|
||||
|
||||
- SH7752 (SH-4A)
|
||||
- DDR3-SDRAM 512MB
|
||||
- SPI ROM 8MB
|
||||
- Gigabit Ethernet controllers
|
||||
- eMMC 4GB
|
||||
|
||||
|
||||
Configuration for This board
|
||||
----------------------------
|
||||
|
||||
You can select the configuration as follows:
|
||||
|
||||
- make sh7752evb_config
|
||||
|
||||
|
||||
This board specific command
|
||||
---------------------------
|
||||
|
||||
This board has the following its specific command:
|
||||
|
||||
write_mac:
|
||||
You can write MAC address to SPI ROM.
|
||||
|
||||
Usage 1: Write MAC address
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
write_mac [GETHERC ch0] [GETHERC ch1]
|
||||
|
||||
For example:
|
||||
=> write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
|
||||
|
||||
* We have to input the command as a single line (without carriage return)
|
||||
* We have to reset after input the command.
|
||||
|
||||
Usage 2: Show current data
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
write_mac
|
||||
|
||||
For example:
|
||||
=> write_mac
|
||||
GETHERC ch0 = 74:90:50:00:33:9e
|
||||
GETHERC ch1 = 74:90:50:00:33:9f
|
||||
|
||||
|
||||
Update SPI ROM
|
||||
--------------
|
||||
|
||||
1. Copy u-boot image to RAM area.
|
||||
2. Probe SPI device.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> sf probe 0
|
||||
SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
|
||||
|
||||
3. Erase SPI ROM.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> sf erase 0 80000
|
||||
|
||||
4. Write u-boot image to SPI ROM.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> sf write 0x48000000 0 80000
|
||||
@@ -0,0 +1,79 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
SH7753 EVB board
|
||||
================
|
||||
|
||||
This board specification
|
||||
------------------------
|
||||
|
||||
The SH7753 EVB (board config name:sh7753evb) has the following device:
|
||||
|
||||
- SH7753 (SH-4A)
|
||||
- DDR3-SDRAM 512MB
|
||||
- SPI ROM 8MB
|
||||
- Gigabit Ethernet controllers
|
||||
- eMMC 4GB
|
||||
|
||||
|
||||
Configuration for This board
|
||||
----------------------------
|
||||
|
||||
You can select the configuration as follows:
|
||||
|
||||
- make sh7753evb_config
|
||||
|
||||
|
||||
This board specific command
|
||||
---------------------------
|
||||
|
||||
This board has the following its specific command:
|
||||
|
||||
write_mac:
|
||||
You can write MAC address to SPI ROM.
|
||||
|
||||
Usage 1: Write MAC address
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
write_mac [GETHERC ch0] [GETHERC ch1]
|
||||
|
||||
For example:
|
||||
=> write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
|
||||
|
||||
* We have to input the command as a single line (without carriage return)
|
||||
* We have to reset after input the command.
|
||||
|
||||
Usage 2: Show current data
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
write_mac
|
||||
|
||||
For example:
|
||||
=> write_mac
|
||||
GETHERC ch0 = 74:90:50:00:33:9e
|
||||
GETHERC ch1 = 74:90:50:00:33:9f
|
||||
|
||||
|
||||
Update SPI ROM
|
||||
--------------
|
||||
|
||||
1. Copy u-boot image to RAM area.
|
||||
2. Probe SPI device.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> sf probe 0
|
||||
SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
|
||||
|
||||
3. Erase SPI ROM.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> sf erase 0 80000
|
||||
|
||||
4. Write u-boot image to SPI ROM.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> sf write 0x48000000 0 80000
|
||||
@@ -0,0 +1,365 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
HiFive Unleashed
|
||||
================
|
||||
|
||||
FU540-C000 RISC-V SoC
|
||||
---------------------
|
||||
The FU540-C000 is the world’s first 4+1 64-bit RISC-V SoC from SiFive.
|
||||
|
||||
The HiFive Unleashed development platform is based on FU540-C000 and capable
|
||||
of running Linux.
|
||||
|
||||
Mainline support
|
||||
----------------
|
||||
The support for following drivers are already enabled:
|
||||
|
||||
1. SiFive UART Driver.
|
||||
2. SiFive PRCI Driver for clock.
|
||||
3. Cadence MACB ethernet driver for networking support.
|
||||
4. SiFive SPI Driver.
|
||||
5. MMC SPI Driver for MMC/SD support.
|
||||
|
||||
TODO:
|
||||
|
||||
1. U-Boot expects the serial console device entry to be present under /chosen
|
||||
DT node. Without a serial console U-Boot will panic. Example:
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
chosen {
|
||||
stdout-path = "/soc/serial@10010000:115200";
|
||||
};
|
||||
|
||||
Building
|
||||
--------
|
||||
|
||||
1. Add the RISC-V toolchain to your PATH.
|
||||
2. Setup ARCH & cross compilation enviornment variable:
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
export ARCH=riscv
|
||||
export CROSS_COMPILE=<riscv64 toolchain prefix>
|
||||
|
||||
3. make sifive_fu540_defconfig
|
||||
4. make
|
||||
|
||||
Flashing
|
||||
--------
|
||||
|
||||
The current U-Boot port is supported in S-mode only and loaded from DRAM.
|
||||
|
||||
A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to
|
||||
boot the u-boot.bin in S-mode and provide M-mode runtime services.
|
||||
|
||||
Currently, the u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD
|
||||
firmware. We need to compile OpenSBI with below command:
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<path to u-boot-dtb.bin>
|
||||
|
||||
More detailed description of steps required to build FW_PAYLOAD firmware
|
||||
is beyond the scope of this document. Please refer OpenSBI documenation.
|
||||
(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
|
||||
|
||||
Once the prior stage firmware/bootloader binary is generated, it should be
|
||||
copied to the first partition of the sdcard.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
sudo dd if=<prior_stage_firmware_binary> of=/dev/disk2s1 bs=1024
|
||||
|
||||
Booting
|
||||
-------
|
||||
Once you plugin the sdcard and power up, you should see the U-Boot prompt.
|
||||
|
||||
Sample boot log from HiFive Unleashed board
|
||||
-------------------------------------------
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
|
||||
|
||||
CPU: rv64imafdc
|
||||
Model: SiFive HiFive Unleashed A00
|
||||
DRAM: 8 GiB
|
||||
MMC: spi@10050000:mmc@0: 0
|
||||
In: serial@10010000
|
||||
Out: serial@10010000
|
||||
Err: serial@10010000
|
||||
Net: eth0: ethernet@10090000
|
||||
Hit any key to stop autoboot: 0
|
||||
=> version
|
||||
U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
|
||||
|
||||
riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-00003-ga0787e9) 8.2.0
|
||||
GNU ld (GNU Binutils) 2.31.1
|
||||
=> mmc info
|
||||
Device: spi@10050000:mmc@0
|
||||
Manufacturer ID: 3
|
||||
OEM: 5344
|
||||
Name: SU08G
|
||||
Bus Speed: 20000000
|
||||
Mode: SD Legacy
|
||||
Rd Block Len: 512
|
||||
SD version 2.0
|
||||
High Capacity: Yes
|
||||
Capacity: 7.4 GiB
|
||||
Bus Width: 1-bit
|
||||
Erase Group Size: 512 Bytes
|
||||
=> mmc part
|
||||
|
||||
Partition Map for MMC device 0 -- Partition Type: EFI
|
||||
|
||||
Part Start LBA End LBA Name
|
||||
Attributes
|
||||
Type GUID
|
||||
Partition GUID
|
||||
1 0x00000800 0x000107ff "bootloader"
|
||||
attrs: 0x0000000000000000
|
||||
type: 2e54b353-1271-4842-806f-e436d6af6985
|
||||
guid: 393bbd36-7111-491c-9869-ce24008f6403
|
||||
2 0x00040800 0x00ecdfde ""
|
||||
attrs: 0x0000000000000000
|
||||
type: 0fc63daf-8483-4772-8e79-3d69d8477de4
|
||||
guid: 7fc9a949-5480-48c7-b623-04923080757f
|
||||
|
||||
Now you can configure your networking, tftp server and use tftp boot method to
|
||||
load uImage.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> setenv ipaddr 10.206.7.133
|
||||
=> setenv netmask 255.255.252.0
|
||||
=> setenv serverip 10.206.4.143
|
||||
=> setenv gateway 10.206.4.1
|
||||
=> tftpboot ${kernel_addr_r} /sifive/fu540/Image
|
||||
ethernet@10090000: PHY present at 0
|
||||
ethernet@10090000: Starting autonegotiation...
|
||||
ethernet@10090000: Autonegotiation complete
|
||||
ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
|
||||
Using ethernet@10090000 device
|
||||
TFTP from server 10.206.4.143; our IP address is 10.206.7.133
|
||||
Filename '/sifive/fu540/Image'.
|
||||
Load address: 0x84000000
|
||||
Loading: #################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
##########################################
|
||||
1.2 MiB/s
|
||||
done
|
||||
Bytes transferred = 8867100 (874d1c hex)
|
||||
=> tftpboot ${ramdisk_addr_r} /sifive/fu540/uRamdisk
|
||||
ethernet@10090000: PHY present at 0
|
||||
ethernet@10090000: Starting autonegotiation...
|
||||
ethernet@10090000: Autonegotiation complete
|
||||
ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
|
||||
Using ethernet@10090000 device
|
||||
TFTP from server 10.206.4.143; our IP address is 10.206.7.133
|
||||
Filename '/sifive/fu540/uRamdisk'.
|
||||
Load address: 0x88300000
|
||||
Loading: #################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
##############
|
||||
418.9 KiB/s
|
||||
done
|
||||
Bytes transferred = 2398272 (249840 hex)
|
||||
=> tftpboot ${fdt_addr_r} /sifive/fu540/hifive-unleashed-a00.dtb
|
||||
ethernet@10090000: PHY present at 0
|
||||
ethernet@10090000: Starting autonegotiation...
|
||||
ethernet@10090000: Autonegotiation complete
|
||||
ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x7c00)
|
||||
Using ethernet@10090000 device
|
||||
TFTP from server 10.206.4.143; our IP address is 10.206.7.133
|
||||
Filename '/sifive/fu540/hifive-unleashed-a00.dtb'.
|
||||
Load address: 0x88000000
|
||||
Loading: ##
|
||||
1000 Bytes/s
|
||||
done
|
||||
Bytes transferred = 5614 (15ee hex)
|
||||
=> setenv bootargs "root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi"
|
||||
=> booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
|
||||
## Loading init Ramdisk from Legacy Image at 88300000 ...
|
||||
Image Name: Linux RootFS
|
||||
Image Type: RISC-V Linux RAMDisk Image (uncompressed)
|
||||
Data Size: 2398208 Bytes = 2.3 MiB
|
||||
Load Address: 00000000
|
||||
Entry Point: 00000000
|
||||
Verifying Checksum ... OK
|
||||
## Flattened Device Tree blob at 88000000
|
||||
Booting using the fdt blob at 0x88000000
|
||||
Using Device Tree in place at 0000000088000000, end 00000000880045ed
|
||||
|
||||
Starting kernel ...
|
||||
|
||||
[ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
|
||||
[ 0.000000] Linux version 5.3.0-rc1-00003-g460ac558152f (anup@anup-lab-machine) (gcc version 8.2.0 (Buildroot 2018.11-rc2-00003-ga0787e9)) #6 SMP Mon Jul 22 10:01:01 IST 2019
|
||||
[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
|
||||
[ 0.000000] printk: bootconsole [sbi0] enabled
|
||||
[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (2398208 bytes)
|
||||
[ 0.000000] Zone ranges:
|
||||
[ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000ffffffff]
|
||||
[ 0.000000] Normal [mem 0x0000000100000000-0x000000027fffffff]
|
||||
[ 0.000000] Movable zone start for each node
|
||||
[ 0.000000] Early memory node ranges
|
||||
[ 0.000000] node 0: [mem 0x0000000080200000-0x000000027fffffff]
|
||||
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x000000027fffffff]
|
||||
[ 0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB)
|
||||
[ 0.000000] CPU with hartid=0 is not available
|
||||
[ 0.000000] CPU with hartid=0 is not available
|
||||
[ 0.000000] elf_hwcap is 0x112d
|
||||
[ 0.000000] percpu: Embedded 18 pages/cpu s34584 r8192 d30952 u73728
|
||||
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2067975
|
||||
[ 0.000000] Kernel command line: root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi
|
||||
[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
|
||||
[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
|
||||
[ 0.000000] Sorting __ex_table...
|
||||
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
|
||||
[ 0.000000] Memory: 8182308K/8386560K available (5916K kernel code, 368K rwdata, 1840K rodata, 213K init, 304K bss, 204252K reserved, 0K cma-reserved)
|
||||
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
|
||||
[ 0.000000] rcu: Hierarchical RCU implementation.
|
||||
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
|
||||
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
|
||||
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
|
||||
[ 0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts.
|
||||
[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
|
||||
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
|
||||
[ 0.000006] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
|
||||
[ 0.008559] Console: colour dummy device 80x25
|
||||
[ 0.012989] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000)
|
||||
[ 0.023104] pid_max: default: 32768 minimum: 301
|
||||
[ 0.028273] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
|
||||
[ 0.035765] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
|
||||
[ 0.045307] rcu: Hierarchical SRCU implementation.
|
||||
[ 0.049875] smp: Bringing up secondary CPUs ...
|
||||
[ 0.055729] smp: Brought up 1 node, 4 CPUs
|
||||
[ 0.060599] devtmpfs: initialized
|
||||
[ 0.064819] random: get_random_u32 called from bucket_table_alloc.isra.10+0x4e/0x160 with crng_init=0
|
||||
[ 0.073720] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
|
||||
[ 0.083176] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
|
||||
[ 0.090721] NET: Registered protocol family 16
|
||||
[ 0.106319] vgaarb: loaded
|
||||
[ 0.108670] SCSI subsystem initialized
|
||||
[ 0.112515] usbcore: registered new interface driver usbfs
|
||||
[ 0.117758] usbcore: registered new interface driver hub
|
||||
[ 0.123167] usbcore: registered new device driver usb
|
||||
[ 0.128905] clocksource: Switched to clocksource riscv_clocksource
|
||||
[ 0.141239] NET: Registered protocol family 2
|
||||
[ 0.145506] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
|
||||
[ 0.153754] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
|
||||
[ 0.163466] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear)
|
||||
[ 0.173468] TCP: Hash tables configured (established 65536 bind 65536)
|
||||
[ 0.179739] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
|
||||
[ 0.186627] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
|
||||
[ 0.194117] NET: Registered protocol family 1
|
||||
[ 0.198417] RPC: Registered named UNIX socket transport module.
|
||||
[ 0.203887] RPC: Registered udp transport module.
|
||||
[ 0.208664] RPC: Registered tcp transport module.
|
||||
[ 0.213429] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 0.219944] PCI: CLS 0 bytes, default 64
|
||||
[ 0.224170] Unpacking initramfs...
|
||||
[ 0.262347] Freeing initrd memory: 2336K
|
||||
[ 0.266531] workingset: timestamp_bits=62 max_order=21 bucket_order=0
|
||||
[ 0.280406] NFS: Registering the id_resolver key type
|
||||
[ 0.284798] Key type id_resolver registered
|
||||
[ 0.289048] Key type id_legacy registered
|
||||
[ 0.293114] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
|
||||
[ 0.300262] NET: Registered protocol family 38
|
||||
[ 0.304432] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
|
||||
[ 0.311862] io scheduler mq-deadline registered
|
||||
[ 0.316461] io scheduler kyber registered
|
||||
[ 0.356421] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 0.363004] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 4, base_baud = 0) is a SiFive UART v0
|
||||
[ 0.371468] printk: console [ttySIF0] enabled
|
||||
[ 0.371468] printk: console [ttySIF0] enabled
|
||||
[ 0.380223] printk: bootconsole [sbi0] disabled
|
||||
[ 0.380223] printk: bootconsole [sbi0] disabled
|
||||
[ 0.389589] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 1, base_baud = 0) is a SiFive UART v0
|
||||
[ 0.398680] [drm] radeon kernel modesetting enabled.
|
||||
[ 0.412395] loop: module loaded
|
||||
[ 0.415214] sifive_spi 10040000.spi: mapped; irq=3, cs=1
|
||||
[ 0.420628] sifive_spi 10050000.spi: mapped; irq=5, cs=1
|
||||
[ 0.425897] libphy: Fixed MDIO Bus: probed
|
||||
[ 0.429964] macb 10090000.ethernet: Registered clk switch 'sifive-gemgxl-mgmt'
|
||||
[ 0.436743] macb: GEM doesn't support hardware ptp.
|
||||
[ 0.441621] libphy: MACB_mii_bus: probed
|
||||
[ 0.601316] Microsemi VSC8541 SyncE 10090000.ethernet-ffffffff:00: attached PHY driver [Microsemi VSC8541 SyncE] (mii_bus:phy_addr=10090000.ethernet-ffffffff:00, irq=POLL)
|
||||
[ 0.615857] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 6 (70:b3:d5:92:f2:f3)
|
||||
[ 0.625634] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
|
||||
[ 0.631381] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
|
||||
[ 0.637382] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
|
||||
[ 0.643799] ehci-pci: EHCI PCI platform driver
|
||||
[ 0.648261] ehci-platform: EHCI generic platform driver
|
||||
[ 0.653497] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
|
||||
[ 0.659599] ohci-pci: OHCI PCI platform driver
|
||||
[ 0.664055] ohci-platform: OHCI generic platform driver
|
||||
[ 0.669448] usbcore: registered new interface driver uas
|
||||
[ 0.674575] usbcore: registered new interface driver usb-storage
|
||||
[ 0.680642] mousedev: PS/2 mouse device common for all mice
|
||||
[ 0.709493] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no poweroff, cd polling
|
||||
[ 0.716615] usbcore: registered new interface driver usbhid
|
||||
[ 0.722023] usbhid: USB HID core driver
|
||||
[ 0.726738] NET: Registered protocol family 10
|
||||
[ 0.731359] Segment Routing with IPv6
|
||||
[ 0.734332] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
|
||||
[ 0.740687] NET: Registered protocol family 17
|
||||
[ 0.744660] Key type dns_resolver registered
|
||||
[ 0.806775] mmc0: host does not support reading read-only switch, assuming write-enable
|
||||
[ 0.814020] mmc0: new SDHC card on SPI
|
||||
[ 0.820137] mmcblk0: mmc0:0000 SU08G 7.40 GiB
|
||||
[ 0.850220] mmcblk0: p1 p2
|
||||
[ 3.821524] macb 10090000.ethernet eth0: link up (1000/Full)
|
||||
[ 3.828938] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
|
||||
[ 3.848919] Sending DHCP requests .., OK
|
||||
[ 6.252076] IP-Config: Got DHCP answer from 10.206.4.1, my address is 10.206.7.133
|
||||
[ 6.259624] IP-Config: Complete:
|
||||
[ 6.262831] device=eth0, hwaddr=70:b3:d5:92:f2:f3, ipaddr=10.206.7.133, mask=255.255.252.0, gw=10.206.4.1
|
||||
[ 6.272809] host=dhcp-10-206-7-133, domain=sdcorp.global.sandisk.com, nis-domain=(none)
|
||||
[ 6.281228] bootserver=10.206.126.11, rootserver=10.206.126.11, rootpath=
|
||||
[ 6.281232] nameserver0=10.86.1.1, nameserver1=10.86.2.1
|
||||
[ 6.294179] ntpserver0=10.86.1.1, ntpserver1=10.86.2.1
|
||||
[ 6.301026] Freeing unused kernel memory: 212K
|
||||
[ 6.304683] This architecture does not have kernel memory protection.
|
||||
[ 6.311121] Run /init as init process
|
||||
_ _
|
||||
| ||_|
|
||||
| | _ ____ _ _ _ _
|
||||
| || | _ \| | | |\ \/ /
|
||||
| || | | | | |_| |/ \
|
||||
|_||_|_| |_|\____|\_/\_/
|
||||
|
||||
Busybox Rootfs
|
||||
|
||||
Please press Enter to activate this console.
|
||||
/ #
|
||||
@@ -0,0 +1,9 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
SiFive
|
||||
======
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
fu540
|
||||
@@ -0,0 +1,10 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Xilinx
|
||||
======
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
xilinx
|
||||
zynq
|
||||
@@ -0,0 +1,38 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. (C) Copyright 2019 Xilinx, Inc.
|
||||
|
||||
U-Boot device tree bindings
|
||||
----------------------------
|
||||
|
||||
All the device tree bindings used in U-Boot are specified in Linux
|
||||
kernel. Please refer dt bindings from below specified paths in Linux
|
||||
kernel.
|
||||
|
||||
* ata
|
||||
- Documentation/devicetree/bindings/ata/ahci-ceva.txt
|
||||
* gpio
|
||||
- Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
|
||||
- Documentation/devicetree/bindings/gpio/gpio-zynq.txt
|
||||
* i2c
|
||||
- Documentation/devicetree/bindings/i2c/i2c-xiic.txt
|
||||
- Documentation/devicetree/bindings/i2c/i2c-cadence.txt
|
||||
* mmc
|
||||
- Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
|
||||
* net
|
||||
- Documentation/devicetree/bindings/net/macb.txt
|
||||
- Documentation/devicetree/bindings/net/xilinx_axienet.txt
|
||||
- Documentation/devicetree/bindings/net/xilinx_emaclite.txt
|
||||
* serial
|
||||
- Documentation/devicetree/bindings/serial/cdns,uart.txt
|
||||
- Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt
|
||||
* spi
|
||||
- Documentation/devicetree/bindings/spi/spi-cadence.txt
|
||||
- Documentation/devicetree/bindings/spi/spi-xilinx.txt
|
||||
- Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
|
||||
- Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
|
||||
* usb
|
||||
- Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
|
||||
- Documentation/devicetree/bindings/usb/dwc3.txt
|
||||
- Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
|
||||
* wdt
|
||||
- Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
|
||||
@@ -0,0 +1,95 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
.. (C) Copyright 2013 Xilinx, Inc.
|
||||
|
||||
ZYNQ
|
||||
====
|
||||
|
||||
About this
|
||||
----------
|
||||
|
||||
This document describes the information about Xilinx Zynq U-Boot -
|
||||
like supported boards, ML status and TODO list.
|
||||
|
||||
Zynq boards
|
||||
-----------
|
||||
|
||||
Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
|
||||
differentiation, integration, and flexibility through hardware, software,
|
||||
and I/O programmability.
|
||||
|
||||
* zc702 (single qspi, gem0, mmc) [1]
|
||||
* zc706 (dual parallel qspi, gem0, mmc) [2]
|
||||
* zed (single qspi, gem0, mmc) [3]
|
||||
* microzed (single qspi, gem0, mmc) [4]
|
||||
* zc770
|
||||
- zc770-xm010 (single qspi, gem0, mmc)
|
||||
- zc770-xm011 (8 or 16 bit nand)
|
||||
- zc770-xm012 (nor)
|
||||
- zc770-xm013 (dual parallel qspi, gem1)
|
||||
|
||||
Building
|
||||
--------
|
||||
|
||||
configure and build for zc702 board::
|
||||
|
||||
$ make zynq_zc702_config
|
||||
$ make
|
||||
|
||||
Bootmode
|
||||
--------
|
||||
|
||||
Zynq has a facility to read the bootmode from the slcr bootmode register
|
||||
once user is setting through jumpers on the board - see page no:1546 on [5]
|
||||
|
||||
All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins
|
||||
on [5].
|
||||
|
||||
board_late_init() will read the bootmode values using slcr bootmode register
|
||||
at runtime and assign the modeboot variable to specific bootmode string which
|
||||
is intern used in autoboot.
|
||||
|
||||
SLCR bootmode register Bit[3:0] values
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
#define ZYNQ_BM_NOR 0x02
|
||||
#define ZYNQ_BM_SD 0x05
|
||||
#define ZYNQ_BM_JTAG 0x0
|
||||
|
||||
"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot"
|
||||
bootmode strings at runtime.
|
||||
|
||||
Mainline status
|
||||
---------------
|
||||
|
||||
- Added basic board configurations support.
|
||||
- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
|
||||
- Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013
|
||||
- Added zynq drivers:
|
||||
|
||||
:serial: drivers/serial/serial_zynq.c
|
||||
:net: drivers/net/zynq_gem.c
|
||||
:mmc: drivers/mmc/zynq_sdhci.c
|
||||
:spi: drivers/spi/zynq_spi.c
|
||||
:qspi: drivers/spi/zynq_qspi.c
|
||||
:i2c: drivers/i2c/zynq_i2c.c
|
||||
:nand: drivers/mtd/nand/raw/zynq_nand.c
|
||||
|
||||
- Done proper cleanups on board configurations
|
||||
- Added basic FDT support for zynq boards
|
||||
- d-cache support for zynq_gem.c
|
||||
|
||||
TODO
|
||||
----
|
||||
|
||||
Add FDT support on individual drivers
|
||||
|
||||
* [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
|
||||
* [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
|
||||
* [3] http://zedboard.org/product/zedboard
|
||||
* [4] http://zedboard.org/product/microzed
|
||||
* [5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
|
||||
|
||||
|
||||
.. Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
|
||||
.. Sun Dec 15 14:52:41 IST 2013
|
||||
Reference in New Issue
Block a user