GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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I2C for Atmel platforms
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Required properties :
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- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
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"atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
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"atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c".
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #address-cells = <1>;
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- #size-cells = <0>;
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- clocks: phandles to input clocks.
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Optional properties:
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- clock-frequency: Desired I2C bus frequency in Hz, default value is 100000.
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- Child nodes conforming to i2c bus binding.
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Examples :
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i2c0: i2c@f8028000 {
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compatible = "atmel,sama5d2-i2c";
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reg = <0xf8028000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&twi0_clk>;
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clock-frequency = <100000>;
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};
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Cadence I2C controller Device Tree Bindings
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-------------------------------------------
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Required properties:
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- compatible : Should be "cdns,i2c-r1p10" or "xlnx,zynq-spi-r1p10".
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- reg : Physical base address and size of I2C registers map.
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- interrupts : Property with a value describing the interrupt
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number.
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- interrupt-parent : Must be core interrupt controller
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- clocks : Clock phandles (see clock bindings for details).
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Example:
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i2c0: i2c@e0004000 {
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compatible = "cdns,i2c-r1p10";
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reg = <0xe0004000 0x1000>;
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clocks = <&clkc 38>;
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interrupts = <0 25 4>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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I2C gpio device binding
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=======================
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Driver:
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- drivers/i2c/i2c-gpio.c
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Software i2c device-tree node properties:
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Required:
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* #address-cells = <1>;
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* #size-cells = <0>;
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* compatible = "i2c-gpio";
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* gpios = <sda ...>, <scl ...>;
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Optional:
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* i2c-gpio,delay-us = <5>;
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The resulting transfer speed can be adjusted by setting the delay[us]
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between gpio-toggle operations. Speed [Hz] = 1000000 / 4 * udelay[us],
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It not defined, then default is 5us (~50KHz).
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Example:
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i2c-gpio@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "i2c-gpio";
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gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, /* SDA */
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<&gpd1 1 GPIO_ACTIVE_HIGH>; /* CLK */
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i2c-gpio,delay-us = <5>;
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some_device@5 {
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compatible = "some_device";
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reg = <0x5>;
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...
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};
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};
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Common i2c bus multiplexer/switch properties.
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An i2c bus multiplexer/switch will have several child busses that are
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numbered uniquely in a device dependent manner. The nodes for an i2c bus
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multiplexer/switch will have one child node for each child
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bus.
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Required properties:
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- #address-cells = <1>;
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- #size-cells = <0>;
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Required properties for child nodes:
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- #address-cells = <1>;
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- #size-cells = <0>;
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- reg : The sub-bus number.
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Optional properties for child nodes:
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- Other properties specific to the multiplexer/switch hardware.
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- Child nodes conforming to i2c bus binding
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Example :
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/*
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An NXP pca9548 8 channel I2C multiplexer at address 0x70
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with two NXP pca8574 GPIO expanders attached, one each to
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ports 3 and 4.
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*/
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mux@70 {
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compatible = "nxp,pca9548";
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reg = <0x70>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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gpio1: gpio@38 {
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compatible = "nxp,pca8574";
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reg = <0x38>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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gpio2: gpio@38 {
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compatible = "nxp,pca8574";
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reg = <0x38>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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};
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* I2C controller embedded in STMicroelectronis STM32 platforms
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Required properties :
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- compatible : Must be "st,stm32f7-i2c"
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- reg : Offset and length of the register set for the device
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- resets: Must contain the phandle to the reset controller
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- clocks: Must contain the input clock of the I2C instance
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- A pinctrl state named "default" must be defined to set pins in mode of
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operation for I2C transfer
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- #address-cells = <1>;
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- #size-cells = <0>;
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Optional properties :
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- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
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the default 100 kHz frequency will be used. As only Normal, Fast and Fast+
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modes are implemented, possible values are 100000, 400000 and 1000000.
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Example :
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i2c1: i2c@40005400 {
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compatible = "st,stm32f7-i2c";
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reg = <0x40005400 0x400>;
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resets = <&rcc 181>;
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clocks = <&clk_pclk1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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U-Boot I2C
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----------
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U-Boot's I2C model has the concept of an offset within a chip (I2C target
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device). The offset can be up to 4 bytes long, but is normally 1 byte,
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meaning that offsets from 0 to 255 are supported by the chip. This often
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corresponds to register numbers.
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Apart from the controller-specific I2C bindings, U-Boot supports a special
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property which allows the chip offset length to be selected.
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Optional properties:
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- u-boot,i2c-offset-len - length of chip offset in bytes. If omitted the
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default value of 1 is used.
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- u-boot,i2c-transaction-bytes - the length of single I2C transaction on
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the bus. Some devices require more than single byte transmission
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(e.g. mc34708 mfd). This information is necessary to correctly
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initialize (put into idle state) I2C bus after soft reset.
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- gpios = <sda ...>, <scl ...>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c_xfer>;
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pinctrl-1 = <&i2c_gpio>;
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Pin description for I2C bus software deblocking.
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Example
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-------
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i2c4: i2c@12ca0000 {
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cros-ec@1e {
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reg = <0x1e>;
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compatible = "google,cros-ec";
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i2c-max-frequency = <100000>;
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u-boot,i2c-offset-len = <0>;
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u-boot,i2c-transaction-bytes = <3>;
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ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
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};
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};
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&i2c1 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c1_xfer>;
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pinctrl-1 = <&i2c1_gpio>;
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gpios = <&gpio1 26 GPIO_ACTIVE_LOW>, /* SDA */
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<&gpio1 27 GPIO_ACTIVE_LOW>; /* SCL */
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};
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+42
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NVIDIA Tegra186 BPMP I2C controller
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In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
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devices, such as the I2C controller for the power management I2C bus. Software
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running on other CPUs must perform IPC to the BPMP in order to execute
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transactions on that I2C bus. This binding describes an I2C bus that is
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accessed in such a fashion.
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The BPMP I2C node must be located directly inside the main BPMP node. See
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../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
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This node represents an I2C controller. See ../i2c/i2c.txt for details of the
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core I2C binding.
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Required properties:
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- compatible:
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Array of strings.
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One of:
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- "nvidia,tegra186-bpmp-i2c".
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- #address-cells: Address cells for I2C device address.
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Single-cell integer.
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Must be <1>.
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- #size-cells:
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Single-cell integer.
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Must be <0>.
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- nvidia,bpmp-bus-id:
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Single-cell integer.
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Indicates the I2C bus number this DT node represent, as defined by the
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BPMP firmware.
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Example:
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bpmp {
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...
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i2c {
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compatible = "nvidia,tegra186-bpmp-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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nvidia,bpmp-bus-id = <5>;
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};
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};
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(Placeholder note while we locate the kernel Tegra20 bindings)
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Added in U-Boot:
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Required properties:
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- clocks : Two clocks must be given, each as a phandle to the Tegra's
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CAR node and the clock number as a parameter:
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- the I2C clock to use for the peripheral
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- the pll_p_out3 clock, which can be used for fast operation. This
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does not change and is the same for all I2C nodes.
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Example:
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(TODO: merge with existing example):
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i2c@7000c400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C400 0x100>;
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interrupts = < 116 >;
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/* PERIPH_ID_I2C2, PLL_P_OUT3 */
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clocks = <&tegra_car 54>, <&tegra_car 124>;
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};
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