GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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+46
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Texas Instruments' K3 AM654 DDRSS
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=================================
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K3 based AM654 devices has DDR memory subsystem that comprises
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Synopys DDR controller, Synopsis DDR phy and wrapper logic to
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integrate these blocks into the device. This DDR subsystem
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provides an interface to external SDRAM devices. This DDRSS driver
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adds support for the initialization of the external SDRAM devices by
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configuring the DDRSS registers and using the buitin PHY
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initialization routines.
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DDRSS device node:
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==================
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Required properties:
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--------------------
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- compatible: Shall be: "ti,am654-ddrss"
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- reg-names ss - Map the sub system wrapper logic region
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ctl - Map the controller region
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phy - Map the PHY region
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- reg: Contains the register map per reg-names.
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- power-domains: Should contain a phandle to a PM domain provider node
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and an args specifier containing the DDRSS device id
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value. This property is as per the binding,
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doc/device-tree-bindings/power/ti,sci-pm-domain.txt
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- clocks: Must contain an entry for enabling DDR clock. Should
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be defined as per the appropriate clock bindings consumer
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usage in doc/device-tree-bindings/clock/ti,sci-clk.txt
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Optional Properties:
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--------------------
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- clock-frequency: Frequency at which DDR pll should be locked.
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If not provided, default frequency will be used.
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Example (AM65x):
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================
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memory-controller: memory-controller@298e000 {
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compatible = "ti,am654-ddrss";
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reg = <0x0298e000 0x200>,
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<0x02980000 0x4000>,
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<0x02988000 0x2000>;
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reg-names = "ss", "ctl", "phy";
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clocks = <&k3_clks 20 0>;
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power-domains = <&k3_pds 20>;
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u-boot,dm-spl;
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};
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+58
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ST, stm32 flexible memory controller Drive
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Required properties:
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- compatible : "st,stm32-fmc"
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- reg : fmc controller base address
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- clocks : fmc controller clock
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u-boot,dm-pre-reloc: flag to initialize memory before relocation.
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on-board sdram memory attributes:
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- st,sdram-control : parameters for sdram configuration, in this order:
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number of columns
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number of rows
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memory width
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number of intenal banks in memory
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cas latency
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read burst enable or disable
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read pipe delay
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- st,sdram-timing: timings for sdram, in this order:
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tmrd
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txsr
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tras
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trc
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trp
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trcd
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There is device tree include file at :
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include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
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parameters as MACROS.
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Example:
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fmc: fmc@A0000000 {
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compatible = "st,stm32-fmc";
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reg = <0xA0000000 0x1000>;
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clocks = <&rcc 0 64>;
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u-boot,dm-pre-reloc;
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};
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&fmc {
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pinctrl-0 = <&fmc_pins>;
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pinctrl-names = "default";
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status = "okay";
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/* sdram memory configuration from sdram datasheet */
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bank1: bank@0 {
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st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
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CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
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TRCD_18>;
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};
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/* sdram memory configuration from sdram datasheet */
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bank2: bank@1 {
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st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
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CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
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TRCD_18>;
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};
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}
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+299
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ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
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--------------------
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Required properties:
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--------------------
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- compatible : Should be "st,stm32mp1-ddr"
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- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
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- clocks : controller clocks handle
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- clock-names : associated controller clock names
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the "ddrphyc" clock is used to check the DDR frequency
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at phy level according the expected value in "mem-speed" field
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the next attributes are DDR parameters, they are generated by DDR tools
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included in STM32 Cube tool
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info attributes:
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----------------
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- st,mem-name : name for DDR configuration, simple string for information
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- st,mem-speed : DDR expected speed for the setting in kHz
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- st,mem-size : DDR mem size in byte
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controlleur attributes:
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-----------------------
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- st,ctl-reg : controleur values depending of the DDR type
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(DDR3/LPDDR2/LPDDR3)
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for STM32MP15x: 25 values are requested in this order
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MSTR
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MRCTRL0
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MRCTRL1
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DERATEEN
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DERATEINT
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PWRCTL
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PWRTMG
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HWLPCTL
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RFSHCTL0
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RFSHCTL3
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CRCPARCTL0
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ZQCTL0
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DFITMG0
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DFITMG1
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DFILPCFG0
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DFIUPD0
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DFIUPD1
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DFIUPD2
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DFIPHYMSTR
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ODTMAP
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DBG0
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DBG1
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DBGCMD
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POISONCFG
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PCCFG
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- st,ctl-timing : controleur values depending of frequency and timing parameter
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of DDR
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for STM32MP15x: 12 values are requested in this order
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RFSHTMG
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DRAMTMG0
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DRAMTMG1
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DRAMTMG2
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DRAMTMG3
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DRAMTMG4
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DRAMTMG5
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DRAMTMG6
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DRAMTMG7
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DRAMTMG8
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DRAMTMG14
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ODTCFG
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- st,ctl-map : controleur values depending of address mapping
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for STM32MP15x: 9 values are requested in this order
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ADDRMAP1
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ADDRMAP2
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ADDRMAP3
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ADDRMAP4
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ADDRMAP5
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ADDRMAP6
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ADDRMAP9
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ADDRMAP10
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ADDRMAP11
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- st,ctl-perf : controleur values depending of performance and scheduling
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for STM32MP15x: 17 values are requested in this order
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SCHED
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SCHED1
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PERFHPR1
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PERFLPR1
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PERFWR1
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PCFGR_0
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PCFGW_0
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PCFGQOS0_0
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PCFGQOS1_0
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PCFGWQOS0_0
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PCFGWQOS1_0
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PCFGR_1
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PCFGW_1
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PCFGQOS0_1
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PCFGQOS1_1
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PCFGWQOS0_1
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PCFGWQOS1_1
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phyc attributes:
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----------------
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- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
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for STM32MP15x: 11 values are requested in this order
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PGCR
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ACIOCR
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DXCCR
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DSGCR
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DCR
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ODTCR
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ZQ0CR1
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DX0GCR
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DX1GCR
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DX2GCR
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DX3GCR
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- st,phy-timing : phy values depending of frequency and timing parameter of DDR
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for STM32MP15x: 10 values are requested in this order
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PTR0
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PTR1
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PTR2
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DTPR0
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DTPR1
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DTPR2
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MR0
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MR1
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MR2
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MR3
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- st,phy-cal : phy cal depending of calibration or tuning of DDR
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for STM32MP15x: 12 values are requested in this order
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DX0DLLCR
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DX0DQTR
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DX0DQSTR
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DX1DLLCR
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DX1DQTR
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DX1DQSTR
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DX2DLLCR
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DX2DQTR
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DX2DQSTR
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DX3DLLCR
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DX3DQTR
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DX3DQSTR
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Example:
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/ {
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soc {
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u-boot,dm-spl;
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ddr: ddr@0x5A003000{
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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compatible = "st,stm32mp1-ddr";
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reg = <0x5A003000 0x550
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0x5A004000 0x234>;
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clocks = <&rcc_clk AXIDCG>,
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<&rcc_clk DDRC1>,
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<&rcc_clk DDRC2>,
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<&rcc_clk DDRPHYC>,
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<&rcc_clk DDRCAPB>,
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<&rcc_clk DDRPHYCAPB>;
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clock-names = "axidcg",
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"ddrc1",
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"ddrc2",
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"ddrphyc",
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"ddrcapb",
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"ddrphycapb";
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st,mem-name = "DDR3 2x4Gb 533MHz";
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st,mem-speed = <533000>;
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st,mem-size = <0x40000000>;
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st,ctl-reg = <
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0x00040401 /*MSTR*/
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0x00000010 /*MRCTRL0*/
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0x00000000 /*MRCTRL1*/
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0x00000000 /*DERATEEN*/
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0x00800000 /*DERATEINT*/
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0x00000000 /*PWRCTL*/
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0x00400010 /*PWRTMG*/
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0x00000000 /*HWLPCTL*/
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0x00210000 /*RFSHCTL0*/
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0x00000000 /*RFSHCTL3*/
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0x00000000 /*CRCPARCTL0*/
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0xC2000040 /*ZQCTL0*/
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0x02050105 /*DFITMG0*/
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0x00000202 /*DFITMG1*/
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0x07000000 /*DFILPCFG0*/
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0xC0400003 /*DFIUPD0*/
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0x00000000 /*DFIUPD1*/
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0x00000000 /*DFIUPD2*/
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0x00000000 /*DFIPHYMSTR*/
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0x00000001 /*ODTMAP*/
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0x00000000 /*DBG0*/
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0x00000000 /*DBG1*/
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0x00000000 /*DBGCMD*/
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0x00000000 /*POISONCFG*/
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0x00000010 /*PCCFG*/
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>;
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st,ctl-timing = <
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0x0080008A /*RFSHTMG*/
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0x121B2414 /*DRAMTMG0*/
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0x000D041B /*DRAMTMG1*/
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0x0607080E /*DRAMTMG2*/
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0x0050400C /*DRAMTMG3*/
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0x07040407 /*DRAMTMG4*/
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0x06060303 /*DRAMTMG5*/
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0x02020002 /*DRAMTMG6*/
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0x00000202 /*DRAMTMG7*/
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0x00001005 /*DRAMTMG8*/
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0x000D041B /*DRAMTMG1*/4
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0x06000600 /*ODTCFG*/
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>;
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st,ctl-map = <
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0x00080808 /*ADDRMAP1*/
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0x00000000 /*ADDRMAP2*/
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0x00000000 /*ADDRMAP3*/
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0x00001F1F /*ADDRMAP4*/
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0x07070707 /*ADDRMAP5*/
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0x0F070707 /*ADDRMAP6*/
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0x00000000 /*ADDRMAP9*/
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0x00000000 /*ADDRMAP10*/
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0x00000000 /*ADDRMAP11*/
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>;
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st,ctl-perf = <
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0x00001201 /*SCHED*/
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0x00001201 /*SCHED*/1
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0x01000001 /*PERFHPR1*/
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0x08000200 /*PERFLPR1*/
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0x08000400 /*PERFWR1*/
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0x00010000 /*PCFGR_0*/
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0x00000000 /*PCFGW_0*/
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0x02100B03 /*PCFGQOS0_0*/
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0x00800100 /*PCFGQOS1_0*/
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0x01100B03 /*PCFGWQOS0_0*/
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0x01000200 /*PCFGWQOS1_0*/
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0x00010000 /*PCFGR_1*/
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0x00000000 /*PCFGW_1*/
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0x02100B03 /*PCFGQOS0_1*/
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0x00800000 /*PCFGQOS1_1*/
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0x01100B03 /*PCFGWQOS0_1*/
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0x01000200 /*PCFGWQOS1_1*/
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>;
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st,phy-reg = <
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0x01442E02 /*PGCR*/
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0x10400812 /*ACIOCR*/
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0x00000C40 /*DXCCR*/
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0xF200001F /*DSGCR*/
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0x0000000B /*DCR*/
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0x00010000 /*ODTCR*/
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0x0000007B /*ZQ0CR1*/
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0x0000CE81 /*DX0GCR*/
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0x0000CE81 /*DX1GCR*/
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0x0000CE81 /*DX2GCR*/
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0x0000CE81 /*DX3GCR*/
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>;
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st,phy-timing = <
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0x0022A41B /*PTR0*/
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0x047C0740 /*PTR1*/
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0x042D9C80 /*PTR2*/
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0x369477D0 /*DTPR0*/
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0x098A00D8 /*DTPR1*/
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0x10023600 /*DTPR2*/
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0x00000830 /*MR0*/
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0x00000000 /*MR1*/
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0x00000208 /*MR2*/
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0x00000000 /*MR3*/
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>;
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st,phy-cal = <
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0x40000000 /*DX0DLLCR*/
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0xFFFFFFFF /*DX0DQTR*/
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0x3DB02000 /*DX0DQSTR*/
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0x40000000 /*DX1DLLCR*/
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0xFFFFFFFF /*DX1DQTR*/
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0x3DB02000 /*DX1DQSTR*/
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0x40000000 /*DX2DLLCR*/
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0xFFFFFFFF /*DX2DQTR*/
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0x3DB02000 /*DX2DQSTR*/
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0x40000000 /*DX3DLLCR*/
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0xFFFFFFFF /*DX3DQTR*/
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0x3DB02000 /*DX3DQSTR*/
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>;
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status = "okay";
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};
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};
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};
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