GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,4 @@
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Altera sysid
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Required properties:
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- compatible : should be "altr,sysid-1.0"
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@@ -0,0 +1,38 @@
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Chrome OS CROS_EC Binding
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======================
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The device tree node which describes the operation of the CROS_EC interface
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is as follows:
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Required properties :
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- compatible = "google,cros-ec"
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Optional properties :
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- spi-max-frequency : Sets the maximum frequency (in Hz) for SPI bus
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operation
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- i2c-max-frequency : Sets the maximum frequency (in Hz) for I2C bus
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operation
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- ec-interrupt : Selects the EC interrupt, defined as a GPIO according
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to the platform
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- optimise-flash-write : Boolean property - if present then flash blocks
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containing all 0xff will not be written, since we assume that the EC
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uses that pattern for erased blocks
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The CROS_EC node should appear as a subnode of the interrupt that connects it
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to the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate
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the unit address on that bus.
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Example
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=======
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spi@131b0000 {
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cros-ec@0 {
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reg = <0>;
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compatible = "google,cros-ec";
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spi-max-frequency = <5000000>;
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ec-interrupt = <&gpio 174 1>;
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optimise-flash-write;
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status = "disabled";
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};
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};
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@@ -0,0 +1,48 @@
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* File system firmware loader
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Required properties:
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--------------------
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- compatible: should contain "u-boot,fs-loader"
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- phandlepart: which block storage device and partition the image loading from,
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this property is required for mmc, usb and sata. This is unsigned
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32-bit array. For example phandlepart=<&mmc_0 1>, meaning use
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that MMC0 node pointer, partition 1.
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- mdtpart: which partition of ubi the image loading from, this property is
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required for ubi and mounting.
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- ubivol: which volume of ubi the image loading from, this property is required
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for ubi and mounting.
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Example of storage device and partition search set for mmc, usb, sata and
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ubi in device tree source as shown in below:
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Example of storage type and device partition search set for mmc, usb,
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sata and ubi as shown in below:
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Example for mmc:
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fs_loader0: fs-loader@0 {
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u-boot,dm-pre-reloc;
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compatible = "u-boot,fs-loader";
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phandlepart = <&mmc_0 1>;
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};
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Example for usb:
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fs_loader1: fs-loader@1 {
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u-boot,dm-pre-reloc;
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compatible = "u-boot,fs-loader";
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phandlepart = <&usb0 1>;
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};
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Example for sata:
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fs_loader2: fs-loader@2 {
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u-boot,dm-pre-reloc;
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compatible = "u-boot,fs-loader";
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phandlepart = <&sata0 1>;
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};
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Example for ubi:
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fs_loader3: fs-loader@3 {
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u-boot,dm-pre-reloc;
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compatible = "u-boot,fs-loader";
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mtdpart = "UBI",
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ubivol = "ubi0";
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};
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+155
@@ -0,0 +1,155 @@
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Intel Bay Trail FSP UPD Binding
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===============================
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The device tree node which describes the overriding of the Intel Bay Trail FSP
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UPD data for configuring the SoC.
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All properties can be found within the `upd-region` struct in
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arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in
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Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties
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is matched up to Intel's E3800 FSPv4 release.
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# Boolean properties:
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- fsp,enable-sdio
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- fsp,enable-sdcard
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- fsp,enable-hsuart0
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- fsp,enable-hsuart1
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- fsp,enable-spi
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- fsp,enable-sata
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- fsp,enable-azalia
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- fsp,enable-xhci
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- fsp,enable-dma0
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- fsp,enable-dma1
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- fsp,enable-i2-c0
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- fsp,enable-i2-c1
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- fsp,enable-i2-c2
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- fsp,enable-i2-c3
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- fsp,enable-i2-c4
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- fsp,enable-i2-c5
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- fsp,enable-i2-c6
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- fsp,enable-pwm0
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- fsp,enable-pwm1
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- fsp,enable-hsi
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- fsp,mrc-debug-msg
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- fsp,isp-enable
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- fsp,igd-render-standby
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- fsp,txe-uma-enable
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- fsp,emmc45-ddr50-enabled
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- fsp,emmc45-hs200-enabled
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- fsp,enable-igd
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- fsp,enable-memory-down
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If you set "fsp,enable-memory-down" you are strongly encouraged to provide an
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"fsp,memory-down-params{};" to specify how your memory is configured. If you
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do not set "fsp,enable-memory-down", then the DIMM SPD information will be
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discovered by the FSP and used to setup main memory.
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# Integer properties:
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- fsp,mrc-init-tseg-size
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- fsp,mrc-init-mmio-size
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- fsp,mrc-init-spd-addr1
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- fsp,mrc-init-spd-addr2
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- fsp,emmc-boot-mode
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- fsp,sata-mode
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- fsp,lpe-mode
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- fsp,lpss-sio-mode
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- fsp,igd-dvmt50-pre-alloc
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- fsp,aperture-size
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- fsp,gtt-size
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- fsp,scc-mode
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- fsp,os-selection
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- fsp,emmc45-retune-timer-value
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- fsp,memory-down-params {
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# Boolean properties:
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- fsp,dimm-0-enable
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- fsp,dimm-1-enable
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# Integer properties:
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- fsp,dram-speed
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- fsp,dram-type
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- fsp,dimm-width
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- fsp,dimm-density
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- fsp,dimm-bus-width
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- fsp,dimm-sides
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- fsp,dimm-tcl
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- fsp,dimm-trpt-rcd
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- fsp,dimm-twr
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- fsp,dimm-twtr
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- fsp,dimm-trrd
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- fsp,dimm-trtp
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- fsp,dimm-tfaw
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};
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For all integer properties, available options are listed in fsp_configs.h in
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arch/x86/include/asm/arch-baytrail/fsp directory (eg: MRC_INIT_TSEG_SIZE_1MB).
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Example (from MinnowMax Dual Core):
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-----------------------------------
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/ {
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...
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fsp {
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compatible = "intel,baytrail-fsp";
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fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
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fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
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fsp,mrc-init-spd-addr1 = <0xa0>;
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fsp,mrc-init-spd-addr2 = <0xa2>;
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fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
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fsp,enable-sdio;
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fsp,enable-sdcard;
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fsp,enable-hsuart1;
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fsp,enable-spi;
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fsp,enable-sata;
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fsp,sata-mode = <SATA_MODE_AHCI>;
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fsp,lpe-mode = <LPE_MODE_PCI>;
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fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
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fsp,enable-dma0;
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fsp,enable-dma1;
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fsp,enable-i2c0;
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fsp,enable-i2c1;
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fsp,enable-i2c2;
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fsp,enable-i2c3;
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fsp,enable-i2c4;
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fsp,enable-i2c5;
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fsp,enable-i2c6;
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fsp,enable-pwm0;
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fsp,enable-pwm1;
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fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
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fsp,aperture-size = <APERTURE_SIZE_256MB>;
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fsp,gtt-size = <GTT_SIZE_2MB>;
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fsp,scc-mode = <SCC_MODE_PCI>;
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fsp,os-selection = <OS_SELECTION_LINUX>;
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fsp,emmc45-ddr50-enabled;
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fsp,emmc45-retune-timer-value = <8>;
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fsp,enable-igd;
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fsp,enable-memory-down;
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fsp,memory-down-params {
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compatible = "intel,baytrail-fsp-mdp";
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fsp,dram-speed = <DRAM_SPEED_1066MTS>;
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fsp,dram-type = <DRAM_TYPE_DDR3L>;
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fsp,dimm-0-enable;
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fsp,dimm-width = <DIMM_WIDTH_X16>;
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fsp,dimm-density = <DIMM_DENSITY_4GBIT>;
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fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
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fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
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fsp,dimm-tcl = <0xb>;
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fsp,dimm-trpt-rcd = <0xb>;
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fsp,dimm-twr = <0xc>;
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fsp,dimm-twtr = <6>;
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fsp,dimm-trrd = <6>;
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fsp,dimm-trtp = <6>;
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fsp,dimm-tfaw = <0x14>;
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};
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};
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...
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};
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@@ -0,0 +1,61 @@
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Intel Interrupt Router Device Binding
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=====================================
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The device tree node which describes the operation of the Intel Interrupt Router
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device is as follows:
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Required properties :
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- reg : Specifies the interrupt router's PCI configuration space address as
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defined by the Open Firmware spec.
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- compatible = "intel,irq-router"
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- intel,pirq-config : Specifies the IRQ routing register programming mechanism.
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Valid values are:
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"pci": IRQ routing is controlled by PCI configuration registers
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"ibase": IRQ routing is in the memory-mapped IBASE register block
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- intel,ibase-offset : IBASE register offset in the interrupt router's PCI
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configuration space, required only if intel,pirq-config = "ibase".
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- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must
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be specified. The 8-bit ACTL register is seen on ICH series chipset, like
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ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register.
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- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either
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in the interrupt router's PCI configuration space, or IBASE.
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- intel,pirq-link : Specifies the PIRQ link information with two cells. The
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first cell is the register offset that controls the first PIRQ link routing.
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The second cell is the total number of PIRQ links the router supports.
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- intel,pirq-regmap : Specifies PIRQ routing register offset of all PIRQ links,
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encoded as 2 cells a group for each link. The first cell is the PIRQ link
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number (0 for PIRQA, 1 for PIRQB, etc). The second cell is the PIRQ routing
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register offset from the interrupt router's base address. If this property
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is omitted, it indicates a consecutive register offset from the first PIRQ
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link, as specified by the first cell of intel,pirq-link.
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- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
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8259 PIC. Bit N is 1 means IRQ N is available to be routed.
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- intel,pirq-routing : Specifies all PCI devices' IRQ routing information,
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encoded as 3 cells a group for a device. The first cell is the device's PCI
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bus number, device number and function number encoding with PCI_BDF() macro.
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The second cell is the PCI interrupt pin used by this device. The last cell
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is which PIRQ line the PCI interrupt pin is routed to.
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Example
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-------
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#include <dt-bindings/interrupt-router/intel-irq.h>
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irq-router@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,irq-router";
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intel,pirq-config = "pci";
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intel,pirq-link = <0x60 8>;
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intel,pirq-mask = <0xdef8>;
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intel,pirq-routing = <
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PCI_BDF(0, 2, 0) INTA PIRQA
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PCI_BDF(0, 3, 0) INTA PIRQB
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PCI_BDF(0, 8, 0) INTA PIRQC
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PCI_BDF(0, 8, 1) INTB PIRQD
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PCI_BDF(1, 6, 0) INTA PIRQE
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PCI_BDF(1, 6, 1) INTB PIRQF
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PCI_BDF(1, 6, 2) INTC PIRQG
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PCI_BDF(1, 6, 3) INTD PIRQH
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>;
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};
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@@ -0,0 +1,64 @@
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Intel LPC Device Binding
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========================
|
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The device tree node which describes the operation of the Intel Low Pin
|
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Count device is as follows:
|
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|
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Required properties :
|
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- compatible = "intel,lpc"
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- intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the
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ALT_GP_SMI_EN register
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- intel,gen-dec : Specifies the values for the gen-dec registers. Up to four
|
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cell pairs can be provided - the first of each pair is the base address and
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the second is the size. These are written into the GENx_DEC registers of
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the LPC device
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- intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid
|
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values are:
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0 No effect (default)
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1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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2 SCI (if corresponding GPIO_EN bit is also set)
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- intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H,
|
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one cell for each.
|
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0x00 - 0000 = Reserved
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0x01 - 0001 = Reserved
|
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0x02 - 0010 = Reserved
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0x03 - 0011 = IRQ3
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0x04 - 0100 = IRQ4
|
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0x05 - 0101 = IRQ5
|
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0x06 - 0110 = IRQ6
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0x07 - 0111 = IRQ7
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||||
0x08 - 1000 = Reserved
|
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0x09 - 1001 = IRQ9
|
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0x0A - 1010 = IRQ10
|
||||
0x0B - 1011 = IRQ11
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||||
0x0C - 1100 = IRQ12
|
||||
0x0D - 1101 = Reserved
|
||||
0x0E - 1110 = IRQ14
|
||||
0x0F - 1111 = IRQ15
|
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PIRQ[n]_ROUT[7] - PIRQ Routing Control
|
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0x80 - The PIRQ is not routed.
|
||||
|
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|
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Example
|
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-------
|
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|
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lpc {
|
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compatible = "intel,lpc";
|
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#address-cells = <1>;
|
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#size-cells = <1>;
|
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intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
|
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|
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intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
|
||||
0x80 0x80 0x80 0x80>;
|
||||
/*
|
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* GPI routing
|
||||
* 0 No effect (default)
|
||||
* 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is
|
||||
* also set)
|
||||
* 2 SCI (if corresponding GPIO_EN bit is also set)
|
||||
*/
|
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intel,gpi-routing = <0 0 0 0 0 0 0 2
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||||
1 0 0 0 0 0 0 0>;
|
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/* Enable EC SMI source */
|
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intel,alt-gp-smi-enable = <0x0100>;
|
||||
};
|
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+24
@@ -0,0 +1,24 @@
|
||||
MPC83xx SerDes controller devices
|
||||
|
||||
MPC83xx SoCs contain a built-in SerDes controller that determines which
|
||||
protocols (SATA, PCI Express, SGMII, ...) are used on the system's serdes lines
|
||||
and how the lines are configured.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "fsl,mpc83xx-serdes"
|
||||
- reg: must point to the serdes controller's register map
|
||||
- proto: selects for which protocol the serdes lines are configured. One of
|
||||
"sata", "pex", "pex-x2", "sgmii"
|
||||
- serdes-clk: determines the frequency the serdes lines are configured for. One
|
||||
of 100, 125, 150.
|
||||
- vdd: determines whether 1.0V core VDD is used or not
|
||||
|
||||
Example:
|
||||
|
||||
SERDES: serdes@e3000 {
|
||||
reg = <0xe3000 0x200>;
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||||
compatible = "fsl,mpc83xx-serdes";
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||||
proto = "pex";
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||||
serdes-clk = <100>;
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vdd;
|
||||
};
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+20
@@ -0,0 +1,20 @@
|
||||
gdsys IO endpoint of IHS FPGA devices
|
||||
|
||||
The IO endpoint of IHS FPGA devices is a packet-based transmission interface
|
||||
that allows interconnected gdsys devices to send and receive data over the
|
||||
FPGA's main ethernet connection.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "gdsys,io-endpoint"
|
||||
- reg: describes the address and length of the endpoint's register map (within
|
||||
the FPGA's register space)
|
||||
|
||||
Example:
|
||||
|
||||
fpga0_ep0 {
|
||||
compatible = "gdsys,io-endpoint";
|
||||
reg = <0x020 0x10
|
||||
0x320 0x10
|
||||
0x340 0x10
|
||||
0x360 0x10>;
|
||||
};
|
||||
+19
@@ -0,0 +1,19 @@
|
||||
gdsys IHS FPGA for CON devices
|
||||
|
||||
The gdsys IHS FPGA is the main FPGA on gdsys CON devices. This driver provides
|
||||
support for enabling and starting the FPGA, as well as verifying working bus
|
||||
communication.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "gdsys,iocon_fpga"
|
||||
- reset-gpios: List of GPIOs controlling the FPGA's reset
|
||||
- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is
|
||||
done
|
||||
|
||||
Example:
|
||||
|
||||
FPGA0 {
|
||||
compatible = "gdsys,iocon_fpga";
|
||||
reset-gpios = <&PPCPCA 26 0>;
|
||||
done-gpios = <&GPIO_VB0 19 0>;
|
||||
};
|
||||
+19
@@ -0,0 +1,19 @@
|
||||
gdsys IHS FPGA for CPU devices
|
||||
|
||||
The gdsys IHS FPGA is the main FPGA on gdsys CPU devices. This driver provides
|
||||
support for enabling and starting the FPGA, as well as verifying working bus
|
||||
communication.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "gdsys,iocpu_fpga"
|
||||
- reset-gpios: List of GPIOs controlling the FPGA's reset
|
||||
- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is
|
||||
done
|
||||
|
||||
Example:
|
||||
|
||||
FPGA0 {
|
||||
compatible = "gdsys,iocpu_fpga";
|
||||
reset-gpios = <&PPCPCA 26 0>;
|
||||
done-gpios = <&GPIO_VB0 19 0>;
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
gdsys soc bus driver
|
||||
|
||||
This driver provides a simple interface for the busses associated with gdsys
|
||||
IHS FPGAs. The bus itself contains devices whose register maps are contained
|
||||
within the FPGA's register space.
|
||||
|
||||
Required properties:
|
||||
- fpga: A phandle to the controlling IHS FPGA
|
||||
|
||||
Example:
|
||||
|
||||
FPGA0BUS: fpga0bus {
|
||||
compatible = "gdsys,soc";
|
||||
ranges = <0x0 0xe0600000 0x00004000>;
|
||||
fpga = <&FPGA0>;
|
||||
};
|
||||
Reference in New Issue
Block a user