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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
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source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/allwinner,sun4i-emac.txt
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* Allwinner EMAC ethernet controller
Required properties:
- compatible: should be "allwinner,sun4i-a10-emac" (Deprecated:
"allwinner,sun4i-emac")
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device
- phy: see ethernet.txt file in the same directory.
- clocks: A phandle to the reference clock for this device
Example:
emac: ethernet@01c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
interrupts = <55>;
clocks = <&ahb_gates 17>;
phy = <&phy0>;
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/allwinner,sun4i-mdio.txt
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* Allwinner A10 MDIO Ethernet Controller interface
Required properties:
- compatible: should be "allwinner,sun4i-a10-mdio"
(Deprecated: "allwinner,sun4i-mdio").
- reg: address and length of the register set for the device.
Optional properties:
- phy-supply: phandle to a regulator if the PHY needs one
Example at the SoC level:
mdio@01c0b080 {
compatible = "allwinner,sun4i-a10-mdio";
reg = <0x01c0b080 0x14>;
#address-cells = <1>;
#size-cells = <0>;
};
And at the board level:
mdio@01c0b080 {
phy-supply = <&reg_emac_3v3>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/allwinner,sun7i-a20-gmac.txt
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* Allwinner GMAC ethernet controller
This device is a platform glue layer for stmmac.
Please see stmmac.txt for the other unchanged properties.
Required properties:
- compatible: Should be "allwinner,sun7i-a20-gmac"
- clocks: Should contain the GMAC main clock, and tx clock
The tx clock type should be "allwinner,sun7i-a20-gmac-clk"
- clock-names: Should contain the clock names "stmmaceth",
and "allwinner_gmac_tx"
Optional properties:
- phy-supply: phandle to a regulator if the PHY needs one
Examples:
gmac: ethernet@01c50000 {
compatible = "allwinner,sun7i-a20-gmac";
reg = <0x01c50000 0x10000>,
<0x01c20164 0x4>;
interrupts = <0 85 1>;
interrupt-names = "macirq";
clocks = <&ahb_gates 49>, <&gmac_tx>;
clock-names = "stmmaceth", "allwinner_gmac_tx";
phy-mode = "mii";
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/altera_tse.txt
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* Altera Triple-Speed Ethernet MAC driver (TSE)
Required properties:
- compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
- reg: Address and length of the register set for the device. It contains
the information of registers in the same order as described by reg-names
- reg-names: Should contain the reg names
"control_port": MAC configuration space region
"tx_csr": xDMA Tx dispatcher control and status space region
"tx_desc": MSGDMA Tx dispatcher descriptor space region
"rx_csr" : xDMA Rx dispatcher control and status space region
"rx_desc": MSGDMA Rx dispatcher descriptor space region
"rx_resp": MSGDMA Rx dispatcher response space region
"s1": SGDMA descriptor memory
- interrupts: Should contain the TSE interrupts and it's mode.
- interrupt-names: Should contain the interrupt names
"rx_irq": xDMA Rx dispatcher interrupt
"tx_irq": xDMA Tx dispatcher interrupt
- rx-fifo-depth: MAC receive FIFO buffer depth in bytes
- tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
- phy-mode: See ethernet.txt in the same directory.
- phy-handle: See ethernet.txt in the same directory.
- phy-addr: See ethernet.txt in the same directory. A configuration should
include phy-handle or phy-addr.
- altr,has-supplementary-unicast:
If present, TSE supports additional unicast addresses.
Otherwise additional unicast addresses are not supported.
- altr,has-hash-multicast-filter:
If present, TSE supports a hash based multicast filter.
Otherwise, hash-based multicast filtering is not supported.
- mdio device tree subnode: When the TSE has a phy connected to its local
mdio, there must be device tree subnode with the following
required properties:
- compatible: Must be "altr,tse-mdio".
- #address-cells: Must be <1>.
- #size-cells: Must be <0>.
For each phy on the mdio bus, there must be a node with the following
fields:
- reg: phy id used to communicate to phy.
- device_type: Must be "ethernet-phy".
Optional properties:
- local-mac-address: See ethernet.txt in the same directory.
- max-frame-size: See ethernet.txt in the same directory.
Example:
tse_sub_0_eth_tse_0: ethernet@0x1,00000000 {
compatible = "altr,tse-msgdma-1.0";
reg = <0x00000001 0x00000000 0x00000400>,
<0x00000001 0x00000460 0x00000020>,
<0x00000001 0x00000480 0x00000020>,
<0x00000001 0x000004A0 0x00000008>,
<0x00000001 0x00000400 0x00000020>,
<0x00000001 0x00000420 0x00000020>;
reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
interrupt-parent = <&hps_0_arm_gic_0>;
interrupts = <0 41 4>, <0 40 4>;
interrupt-names = "rx_irq", "tx_irq";
rx-fifo-depth = <2048>;
tx-fifo-depth = <2048>;
address-bits = <48>;
max-frame-size = <1500>;
local-mac-address = [ 00 00 00 00 00 00 ];
phy-mode = "gmii";
altr,has-supplementary-unicast;
altr,has-hash-multicast-filter;
phy-handle = <&phy0>;
mdio {
compatible = "altr,tse-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
reg = <0x1>;
device_type = "ethernet-phy";
};
};
};
tse_sub_1_eth_tse_0: ethernet@0x1,00001000 {
compatible = "altr,tse-msgdma-1.0";
reg = <0x00000001 0x00001000 0x00000400>,
<0x00000001 0x00001460 0x00000020>,
<0x00000001 0x00001480 0x00000020>,
<0x00000001 0x000014A0 0x00000008>,
<0x00000001 0x00001400 0x00000020>,
<0x00000001 0x00001420 0x00000020>;
reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
interrupt-parent = <&hps_0_arm_gic_0>;
interrupts = <0 43 4>, <0 42 4>;
interrupt-names = "rx_irq", "tx_irq";
rx-fifo-depth = <2048>;
tx-fifo-depth = <2048>;
address-bits = <48>;
max-frame-size = <1500>;
local-mac-address = [ 00 00 00 00 00 00 ];
phy-mode = "gmii";
altr,has-supplementary-unicast;
altr,has-hash-multicast-filter;
phy-handle = <&phy1>;
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/aquantia-phy.txt
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PHY nodes for Aquantia devices.
This text describes properties that are applicable to Aquantia PHY nodes in
addition to the bindings in phy.txt.
Aquantia PHYs allow some flexibility in the way they are wired in a system,
they allow MDI pins to be reversed, LEDs linked up in different weays, have an
I2C slave interface that can be used for debug. Normally the configuration
corresponding to these is driven by the PHY firmware with the downside that
a custom firmware is needed for each integration of a PHY.
Several optional bindings are defined that allow these configuration points to
be driven by the PHY driver and reduce dependency on specific FW versions.
Optional properties:
mdi-reversal: 0 or 1 indicating that reversal must be disabled/enabled.
Firmware default is used if the property is missing.
smb-addr: I2C/SMBus address to use, firmware default is used if the property
is missing.
Example node:
phy@00 {
reg = <0x00>;
mdi-reversal = <1>;
smb-addr = <0x25>;
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/ethernet.txt
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The following properties are common to the Ethernet controllers:
NOTE: All 'phy*' properties documented below are Ethernet specific. For the
generic PHY 'phys' property, see
Documentation/devicetree/bindings/phy/phy-bindings.txt.
- local-mac-address: array of 6 bytes, specifies the MAC address that was
assigned to the network device;
- mac-address: array of 6 bytes, specifies the MAC address that was last used by
the boot program; should be used in cases where the MAC address assigned to
the device by the boot program is different from the "local-mac-address"
property;
- nvmem-cells: phandle, reference to an nvmem node for the MAC address;
- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used;
- max-speed: number, specifies maximum speed in Mbit/s supported by the device;
- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
the maximum frame size (there's contradiction in the Devicetree
Specification).
- phy-mode: string, operation mode of the PHY interface. This is now a de-facto
standard property; supported values are:
* "internal"
* "mii"
* "gmii"
* "sgmii"
* "qsgmii"
* "tbi"
* "rev-mii"
* "rmii"
* "rgmii" (RX and TX delays are added by the MAC when required)
* "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the
MAC should not add the RX or TX delays in this case)
* "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC
should not add an RX delay in this case)
* "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC
should not add an TX delay in this case)
* "rtbi"
* "smii"
* "xgmii"
* "trgmii"
* "2000base-x",
* "2500base-x",
* "rxaui"
* "xaui"
* "10gbase-kr" (10GBASE-KR, XFI, SFI)
- phy-connection-type: the same as "phy-mode" property but described in the
Devicetree Specification;
- phy-handle: phandle, specifies a reference to a node representing a PHY
device; this property is described in the Devicetree Specification and so
preferred;
- phy: the same as "phy-handle" property, not recommended for new bindings.
- phy-device: the same as "phy-handle" property, not recommended for new
bindings.
- rx-fifo-depth: the size of the controller's receive fifo in bytes. This
is used for components that can have configurable receive fifo sizes,
and is useful for determining certain configuration settings such as
flow control thresholds.
- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This
is used for components that can have configurable fifo sizes.
- managed: string, specifies the PHY management type. Supported values are:
"auto", "in-band-status". "auto" is the default, it usess MDIO for
management if fixed-link is not specified.
Child nodes of the Ethernet controller are typically the individual PHY devices
connected via the MDIO bus (sometimes the MDIO bus controller is separate).
They are described in the phy.txt file in this same directory.
For non-MDIO PHY management see fixed-link.txt.
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/fixed-link.txt
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Fixed link Device Tree binding
------------------------------
Some Ethernet MACs have a "fixed link", and are not connected to a
normal MDIO-managed PHY device. For those situations, a Device Tree
binding allows to describe a "fixed link".
Such a fixed link situation is described by creating a 'fixed-link'
sub-node of the Ethernet MAC device node, with the following
properties:
* 'speed' (integer, mandatory), to indicate the link speed. Accepted
values are 10, 100 and 1000
* 'full-duplex' (boolean, optional), to indicate that full duplex is
used. When absent, half duplex is assumed.
* 'pause' (boolean, optional), to indicate that pause should be
enabled.
* 'asym-pause' (boolean, optional), to indicate that asym_pause should
be enabled.
Examples:
ethernet@0 {
...
fixed-link {
speed = <1000>;
full-duplex;
};
...
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/fsl-tsec-phy.txt
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* TSEC-compatible ethernet nodes
Properties:
- compatible : Should be "fsl,tsec"
- reg : Offset and length of the register set for the device
- phy-handle : See ethernet.txt file in the same directory.
- phy-connection-type : See ethernet.txt file in the same directory. This
property is only really needed if the connection is of type "rgmii-id",
"rgmii-rxid" and "rgmii-txid" as all other connection types are detected
by hardware.
Example:
ethernet@24000 {
compatible = "fsl,tsec";
reg = <0x24000 0x1000>;
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
};
Child nodes of the TSEC controller are typically the individual PHY devices
connected via the MDIO bus (sometimes the MDIO bus controller is separate).
* MDIO IO device
The MDIO is a bus to which the PHY devices are connected. For each
device that exists on this bus, a PHY node should be created.
Required properties:
- compatible : Should define the compatible device type for the
mdio. Currently supported string/device is "fsl,etsec2-mdio".
- reg : Offset and length of the register set for the device
Example:
mdio@24520 {
compatible = "fsl,etsec2-mdio";
reg = <0x24520 0x20>;
ethernet-phy@0 {
reg = <0>;
};
};
* TBI Internal MDIO bus
As of this writing, every tsec is associated with an internal TBI PHY.
This PHY is accessed through the local MDIO bus. These buses are defined
similarly to the mdio buses. The TBI PHYs underneath them are similar to
normal PHYs, but the reg property is considered instructive, rather than
descriptive. The reg property should be chosen so it doesn't interfere
with other PHYs on the bus. The TBI PHYs are referred to by a "tbi-handle"
property under the tsec node, which has a similar meaning of "phy-handle".
Example:
ethernet@24000 {
phy-handle = <&tbi1>;
};
mdio@24520 {
tbi1: tbi-phy@1f {
reg = <0x1f>;
};
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/marvell-mdio.txt
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* Marvell MDIO Ethernet Controller interface
The Ethernet controllers of the Marvel Armada 3700 and Armada 7k/8k
have an identical unit that provides an interface with the MDIO bus.
This driver handles this MDIO interface.
Mandatory properties:
SoC specific:
- #address-cells: Must be <1>.
- #size-cells: Must be <0>.
- compatible: Should be "marvell,orion-mdio" (for SMI)
"marvell,xmdio" (for XSMI)
- reg: Base address and size SMI/XMSI bus.
Please refer to "mdio.txt" for generic MDIO bus bindings.
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/mdio-mux-reg.txt
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Device tree structures used by register based MDIO muxes is described here.
This binding is based on reg-mux.txt binding in Linux and is currently used by
mdio-mux-i2creg driver in U-Boot.
Required properties:
#mux-control-cells = <1> indicates how many registers are used for mux
selection. mux-reg-mask property described below must
include this number of pairs.
mux-reg-masks = <reg mask> describes pairs of register offset and register mask.
Register bits enabled in mask are set to the selection
value defined in reg property of child MDIOs to control
selection.
Properties described in mdio-mux.txt also apply.
Example structure, used on Freescale LS1028A QDS board:
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
fpga@66 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-mfd";
reg = <0x66>;
mux-mdio@54 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-i2creg";
reg = <0x54>;
#mux-control-cells = <1>;
mux-reg-masks = <0x54 0xf0>;
mdio-parent-bus = <&mdio0>;
/* on-board MDIO with a single RGMII PHY */
mdio@00 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
/* on-board 1G RGMII PHY */
qds_phy0: phy@5 {
reg = <5>;
};
};
/* card slot 1 */
mdio@40 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40>;
/* VSC8234 1G SGMII card */
sgmii_port0: phy@1c {
reg = <0x1c>;
};
};
/* card slot 2 */
mdio@50 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x50>;
};
/* card slot 3 */
mdio@60 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60>;
};
/* card slot 4 */
mdio@70 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
};
};
};
};
/* Parent MDIO, defined in SoC .dtsi file, just enabled here */
&mdio0 {
status = "okay";
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/mdio-mux.txt
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The expected structure of an MDIO MUX device tree node is described here. This
is heavily based on current Linux specification.
One notable difference to Linux is that mdio-parent-bus is currently required
by U-Boot, not optional as is in Linux. Current U-Boot MDIO MUX udevice class
implementation does not have specific support for MDIOs with an integrated MUX,
the property should be made optional if such support is added.
The MDIO buses downstream of the MUX should be described in the device tree as
child nodes as indicated below.
Required properties:
mdio-parent-bus = a phandle to the MDIO bus used to perform actual I/O. This is
typically a real MDIO device, unless there are cascaded MUXes.
#address-cells = <1>, each MDIO group is identified by one 32b value.
#size-cells = <0>
Other properties:
The properties described here are sufficient for MDIO MUX DM class code, but
MUX drivers may define additional properties, either required or optional.
Required properties in child nodes:
reg = value to be configured on the MUX to select the respective downstream
MDIO.
Child nodes should normally contain PHY nodes, referenced by phandle from
ethernet nodes of the eth interfaces using these PHYs.
Example structure, extracted from Linux bindings document:
/* The parent MDIO bus. */
smi1: mdio@1180000001900 {
compatible = "cavium,octeon-3860-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x11800 0x00001900 0x0 0x40>;
};
/*
* An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
* pair of GPIO lines. Child busses 2 and 3 populated with 4
* PHYs each.
*/
mdio-mux {
compatible = "mdio-mux-gpio";
gpios = <&gpio1 3 0>, <&gpio1 4 0>;
mdio-parent-bus = <&smi1>;
#address-cells = <1>;
#size-cells = <0>;
mdio@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
phy11: ethernet-phy@1 {
reg = <1>;
compatible = "marvell,88e1149r";
marvell,reg-init = <3 0x10 0 0x5777>,
<3 0x11 0 0x00aa>,
<3 0x12 0 0x4105>,
<3 0x13 0 0x0a60>;
interrupt-parent = <&gpio>;
interrupts = <10 8>; /* Pin 10, active low */
};
phy12: ethernet-phy@2 {
reg = <2>;
compatible = "marvell,88e1149r";
marvell,reg-init = <3 0x10 0 0x5777>,
<3 0x11 0 0x00aa>,
<3 0x12 0 0x4105>,
<3 0x13 0 0x0a60>;
interrupt-parent = <&gpio>;
interrupts = <10 8>; /* Pin 10, active low */
};
phy13: ethernet-phy@3 {
reg = <3>;
compatible = "marvell,88e1149r";
marvell,reg-init = <3 0x10 0 0x5777>,
<3 0x11 0 0x00aa>,
<3 0x12 0 0x4105>,
<3 0x13 0 0x0a60>;
interrupt-parent = <&gpio>;
interrupts = <10 8>; /* Pin 10, active low */
};
phy14: ethernet-phy@4 {
reg = <4>;
compatible = "marvell,88e1149r";
marvell,reg-init = <3 0x10 0 0x5777>,
<3 0x11 0 0x00aa>,
<3 0x12 0 0x4105>,
<3 0x13 0 0x0a60>;
interrupt-parent = <&gpio>;
interrupts = <10 8>; /* Pin 10, active low */
};
};
mdio@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
phy21: ethernet-phy@1 {
reg = <1>;
compatible = "marvell,88e1149r";
marvell,reg-init = <3 0x10 0 0x5777>,
<3 0x11 0 0x00aa>,
<3 0x12 0 0x4105>,
<3 0x13 0 0x0a60>;
interrupt-parent = <&gpio>;
interrupts = <12 8>; /* Pin 12, active low */
};
phy22: ethernet-phy@2 {
reg = <2>;
compatible = "marvell,88e1149r";
marvell,reg-init = <3 0x10 0 0x5777>,
<3 0x11 0 0x00aa>,
<3 0x12 0 0x4105>,
<3 0x13 0 0x0a60>;
interrupt-parent = <&gpio>;
interrupts = <12 8>; /* Pin 12, active low */
};
phy23: ethernet-phy@3 {
reg = <3>;
compatible = "marvell,88e1149r";
marvell,reg-init = <3 0x10 0 0x5777>,
<3 0x11 0 0x00aa>,
<3 0x12 0 0x4105>,
<3 0x13 0 0x0a60>;
interrupt-parent = <&gpio>;
interrupts = <12 8>; /* Pin 12, active low */
};
phy24: ethernet-phy@4 {
reg = <4>;
compatible = "marvell,88e1149r";
marvell,reg-init = <3 0x10 0 0x5777>,
<3 0x11 0 0x00aa>,
<3 0x12 0 0x4105>,
<3 0x13 0 0x0a60>;
interrupt-parent = <&gpio>;
interrupts = <12 8>; /* Pin 12, active low */
};
};
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/mdio.txt
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Common MDIO bus properties.
These are generic properties that can apply to any MDIO bus.
Optional properties:
- device-name - If present it is used to name the device and MDIO bus.
The name must be unique and must not contain spaces.
A list of child nodes, one per device on the bus is expected. These could be
PHYs, switches or similar devices and child nodes should follow the specific
binding for the device type.
Example :
This example shows the structure used for the external MDIO bus on NXP LS1028A
RDB board. Note that this MDIO device is an integrated PCI function and
requires no compatible property for probing.
/* definition in SoC dtsi file */
pcie@1f0000000 {
mdio0: pci@0,3 {
#address-cells=<0>;
#size-cells=<1>;
reg = <0x000300 0 0 0 0>;
status = "disabled";
device-name = "emdio";
};
};
/* definition of PHYs in RDB dts file */
&mdio0 {
status = "okay";
rdb_phy0: phy@2 {
reg = <2>;
};
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/mediatek,mt7628-eth.txt
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* MediaTek Frame Engine Ethernet controller
Required properties:
- compatible: should be "mediatek,mt7628-eth"
- reg: address and length of the register set for the frame
engine ethernet controller and the internal switch.
- syscon: phandle to the system controller
Example:
eth@10100000 {
compatible = "mediatek,mt7628-eth";
reg = <0x10100000 0x10000
0x10110000 0x8000>;
syscon = <&sysc>;
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/micrel-ksz90x1.txt
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Micrel KSZ9021/KSZ9031 Gigabit Ethernet PHY
Some boards require special tuning values, particularly when it comes to
clock delays. You can specify clock delay values by adding
micrel-specific properties to an Ethernet OF device node.
Note that these settings are applied after any phy-specific fixup from
phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c),
and therefore may overwrite them.
KSZ9021:
All skew control options are specified in picoseconds. The minimum
value is 0, the maximum value is 1800, and it is incremented by 120ps
steps.
The KSZ9021 hardware supports a range of skew values from negative to
positive, where the specific range is property dependent. All values
specified in the devicetree are offset by the minimum value so they
can be represented as positive integers in the devicetree since it's
difficult to represent a negative number in the devictree.
The following 4-bit values table applies to all the skew properties:
Pad Skew Value Delay (ps) Devicetree Value
------------------------------------------------------
0000 -840ps 0
0001 -720ps 120
0010 -600ps 240
0011 -480ps 360
0100 -360ps 480
0101 -240ps 600
0110 -120ps 720
0111 0ps 840
1000 120ps 960
1001 240ps 1080
1010 360ps 1200
1011 480ps 1320
1100 600ps 1440
1101 720ps 1560
1110 840ps 1680
1111 960ps 1800
Optional properties:
- rxc-skew-ps : Skew control of RXC pad
- rxdv-skew-ps : Skew control of RX CTL pad
- txc-skew-ps : Skew control of TXC pad
- txen-skew-ps : Skew control of TX CTL pad
- rxd0-skew-ps : Skew control of RX data 0 pad
- rxd1-skew-ps : Skew control of RX data 1 pad
- rxd2-skew-ps : Skew control of RX data 2 pad
- rxd3-skew-ps : Skew control of RX data 3 pad
- txd0-skew-ps : Skew control of TX data 0 pad
- txd1-skew-ps : Skew control of TX data 1 pad
- txd2-skew-ps : Skew control of TX data 2 pad
- txd3-skew-ps : Skew control of TX data 3 pad
KSZ9031:
All skew control options are specified in picoseconds. The minimum
value is 0, and the maximum is property-dependent. The increment
step is 60ps.
The KSZ9031 hardware supports a range of skew values from negative to
positive, where the specific range is property dependent. All values
specified in the devicetree are offset by the minimum value so they
can be represented as positive integers in the devicetree since it's
difficult to represent a negative number in the devictree.
The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps.
Pad Skew Value Delay (ps) Devicetree Value
------------------------------------------------------
0_0000 -900ps 0
0_0001 -840ps 60
0_0010 -780ps 120
0_0011 -720ps 180
0_0100 -660ps 240
0_0101 -600ps 300
0_0110 -540ps 360
0_0111 -480ps 420
0_1000 -420ps 480
0_1001 -360ps 540
0_1010 -300ps 600
0_1011 -240ps 660
0_1100 -180ps 720
0_1101 -120ps 780
0_1110 -60ps 840
0_1111 0ps 900
1_0000 60ps 960
1_0001 120ps 1020
1_0010 180ps 1080
1_0011 240ps 1140
1_0100 300ps 1200
1_0101 360ps 1260
1_0110 420ps 1320
1_0111 480ps 1380
1_1000 540ps 1440
1_1001 600ps 1500
1_1010 660ps 1560
1_1011 720ps 1620
1_1100 780ps 1680
1_1101 840ps 1740
1_1110 900ps 1800
1_1111 960ps 1860
The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps
data pads, and the rxdv-skew-ps, txen-skew-ps control pads.
Pad Skew Value Delay (ps) Devicetree Value
------------------------------------------------------
0000 -420ps 0
0001 -360ps 60
0010 -300ps 120
0011 -240ps 180
0100 -180ps 240
0101 -120ps 300
0110 -60ps 360
0111 0ps 420
1000 60ps 480
1001 120ps 540
1010 180ps 600
1011 240ps 660
1100 300ps 720
1101 360ps 780
1110 420ps 840
1111 480ps 900
Optional properties:
Maximum value of 1860:
- rxc-skew-ps : Skew control of RX clock pad
- txc-skew-ps : Skew control of TX clock pad
Maximum value of 900:
- rxdv-skew-ps : Skew control of RX CTL pad
- txen-skew-ps : Skew control of TX CTL pad
- rxd0-skew-ps : Skew control of RX data 0 pad
- rxd1-skew-ps : Skew control of RX data 1 pad
- rxd2-skew-ps : Skew control of RX data 2 pad
- rxd3-skew-ps : Skew control of RX data 3 pad
- txd0-skew-ps : Skew control of TX data 0 pad
- txd1-skew-ps : Skew control of TX data 1 pad
- txd2-skew-ps : Skew control of TX data 2 pad
- txd3-skew-ps : Skew control of TX data 3 pad
Examples:
/* Attach to an Ethernet device with autodetected PHY */
&enet {
rxc-skew-ps = <1800>;
rxdv-skew-ps = <0>;
txc-skew-ps = <1800>;
txen-skew-ps = <0>;
status = "okay";
};
/* Attach to an explicitly-specified PHY */
mdio {
phy0: ethernet-phy@0 {
rxc-skew-ps = <1800>;
rxdv-skew-ps = <0>;
txc-skew-ps = <1800>;
txen-skew-ps = <0>;
reg = <0>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
References
Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014.
http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf
Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014.
http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf
Notes:
Note that a previous version of the Micrel ksz9021rl/rn Data Sheet
was missing extended register 106 (transmit data pad skews), and
incorrectly specified the ps per step as 200ps/step instead of
120ps/step. The latest update to this document reflects the latest
revision of the Micrel specification even though usage in the kernel
still reflects that incorrect document.
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/phy.txt
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PHY nodes
If the device tree is used to describe networking interfaces, U-Boot expects a
node for each PHY. Parent node for such a PHY node is expected to correspond to
a MDIO bus and the bus is used to access the PHY.
Required properties:
- reg : The ID number for the phy, usually a small integer
Example:
ethernet-phy@0 {
compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
interrupt-parent = <&PIC>;
interrupts = <35 IRQ_TYPE_EDGE_RISING>;
reg = <0>;
resets = <&rst 8>;
reset-names = "phy";
reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <2000>;
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt
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* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
IP block. The IP supports multiple options for bus type, clocking and reset
structure, and feature list. Consequently, a number of properties and list
entries in properties are marked as optional, or only required in specific HW
configurations.
Required properties:
- compatible: One of:
- "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
- "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
- "snps,dwc-qos-ethernet-4.10"
This combination is deprecated. It should be treated as equivalent to
"axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
compatible with earlier revisions of this binding.
- reg: Address and length of the register set for the device
- clocks: Phandle and clock specifiers for each entry in clock-names, in the
same order. See ../clock/clock-bindings.txt.
- clock-names: May contain any/all of the following depending on the IP
configuration, in any order:
- "tx"
The EQOS transmit path clock. The HW signal name is clk_tx_i.
In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
path. In other configurations, other clocks (such as tx_125, rmii) may
drive the PHY TX path.
- "rx"
The EQOS receive path clock. The HW signal name is clk_rx_i.
In some configurations (e.g. GMII/RGMII), this clock is derived from the
PHY's RX clock output. In other configurations, other clocks (such as
rx_125, rmii) may drive the EQOS RX path.
In cases where the PHY clock is directly fed into the EQOS receive path
without intervening logic, the DT need not represent this clock, since it
is assumed to be fully under the control of the PHY device/driver. In
cases where SoC integration adds additional logic to this path, such as a
SW-controlled clock gate, this clock should be represented in DT.
- "slave_bus"
The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
buses).
- "master_bus"
The master bus interface clock. Only required in configurations that use a
separate clock for the master and slave bus interfaces. The HW signal name
is hclk_i (AHB) or aclk_i (AXI).
- "ptp_ref"
The PTP reference clock. The HW signal name is clk_ptp_ref_i.
- "phy_ref_clk"
This clock is deprecated and should not be used by new compatible values.
It is equivalent to "tx".
- "apb_pclk"
This clock is deprecated and should not be used by new compatible values.
It is equivalent to "slave_bus".
Note: Support for additional IP configurations may require adding the
following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i,
clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i.
Configurations exist where multiple similar clocks are used at once, e.g. all
of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to
extend the binding with a separate clock-names entry for each of those RX
clocks, rather than repurposing the existing "rx" clock-names entry as a
generic/logical clock in a similar fashion to "master_bus" and "slave_bus".
This will allow easy support for configurations that support multiple PHY
interfaces using a mux, and hence need to have explicit control over
specific RX clocks.
The following compatible values require the following set of clocks:
- "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
- "slave_bus"
- "master_bus"
- "rx"
- "tx"
- "ptp_ref"
- "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
- "slave_bus"
- "master_bus"
- "tx"
- "ptp_ref"
- "snps,dwc-qos-ethernet-4.10" (deprecated):
- "phy_ref_clk"
- "apb_clk"
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
- interrupts: Should contain the core's combined interrupt signal
- phy-mode: See ethernet.txt file in the same directory
- resets: Phandle and reset specifiers for each entry in reset-names, in the
same order. See ../reset/reset.txt.
- reset-names: May contain any/all of the following depending on the IP
configuration, in any order:
- "eqos". The reset to the entire module. The HW signal name is hreset_n
(AHB) or aresetn_i (AXI).
The following compatible values require the following set of resets:
(the reset properties may be omitted if empty)
- "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
- "eqos".
- "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
- None.
- "snps,dwc-qos-ethernet-4.10" (deprecated):
- None.
Optional properties:
- dma-coherent: Present if dma operations are coherent
- mac-address: See ethernet.txt in the same directory
- local-mac-address: See ethernet.txt in the same directory
- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY.
See ../gpio/gpio.txt.
- snps,en-lpi: If present it enables use of the AXI low-power interface
- snps,write-requests: Number of write requests that the AXI port can issue.
It depends on the SoC configuration.
- snps,read-requests: Number of read requests that the AXI port can issue.
It depends on the SoC configuration.
- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB
representing 4, then 8 etc.
- snps,txpbl: DMA Programmable burst length for the TX DMA
- snps,rxpbl: DMA Programmable burst length for the RX DMA
- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
TX low-power mode.
- phy-handle: See ethernet.txt file in the same directory
- mdio device tree subnode: When the GMAC has a phy connected to its local
mdio, there must be device tree subnode with the following
required properties:
- compatible: Must be "snps,dwc-qos-ethernet-mdio".
- #address-cells: Must be <1>.
- #size-cells: Must be <0>.
For each phy on the mdio bus, there must be a node with the following
fields:
- reg: phy id used to communicate to phy.
- device_type: Must be "ethernet-phy".
- fixed-mode device tree subnode: see fixed-link.txt in the same directory
Examples:
ethernet2@40010000 {
clock-names = "phy_ref_clk", "apb_pclk";
clocks = <&clkc 17>, <&clkc 15>;
compatible = "snps,dwc-qos-ethernet-4.10";
interrupt-parent = <&intc>;
interrupts = <0x0 0x1e 0x4>;
reg = <0x40010000 0x4000>;
phy-handle = <&phy2>;
phy-mode = "gmii";
phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>;
snps,en-tx-lpi-clockgating;
snps,en-lpi;
snps,write-requests = <2>;
snps,read-requests = <16>;
snps,burst-map = <0x7>;
snps,txpbl = <8>;
snps,rxpbl = <2>;
dma-coherent;
mdio {
#address-cells = <0x1>;
#size-cells = <0x0>;
phy2: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
device_type = "ethernet-phy";
reg = <0x1>;
};
};
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/stmmac.txt
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* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
Required properties:
- compatible: Should be "snps,dwmac-<ip_version>" "snps,dwmac"
For backwards compatibility: "st,spear600-gmac" is also supported.
- reg: Address and length of the register set for the device
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
- interrupts: Should contain the STMMAC interrupts
- interrupt-names: Should contain the interrupt names "macirq"
"eth_wake_irq" if this interrupt is supported in the "interrupts"
property
- phy-mode: See ethernet.txt file in the same directory.
- snps,reset-gpio gpio number for phy reset.
- snps,reset-active-low boolean flag to indicate if phy reset is active low.
- snps,reset-delays-us is triplet of delays
The 1st cell is reset pre-delay in micro seconds.
The 2nd cell is reset pulse in micro seconds.
The 3rd cell is reset post-delay in micro seconds.
- snps,pbl Programmable Burst Length
- snps,fixed-burst Program the DMA to use the fixed burst mode
- snps,mixed-burst Program the DMA to use the mixed burst mode
- snps,force_thresh_dma_mode Force DMA to use the threshold mode for
both tx and rx
- snps,force_sf_dma_mode Force DMA to use the Store and Forward
mode for both tx and rx. This flag is
ignored if force_thresh_dma_mode is set.
- snps,multicast-filter-bins: Number of multicast filter hash bins
supported by this device instance
- snps,perfect-filter-entries: Number of perfect filter entries supported
by this device instance
Optional properties:
- resets: Should contain a phandle to the STMMAC reset signal, if any
- reset-names: Should contain the reset signal name "stmmaceth", if a
reset phandle is given
- max-frame-size: See ethernet.txt file in the same directory
- clocks: If present, the first clock should be the GMAC main clock,
further clocks may be specified in derived bindings.
- clock-names: One name for each entry in the clocks property, the
first one should be "stmmaceth".
- clk_ptp_ref: this is the PTP reference clock; in case of the PTP is
available this clock is used for programming the Timestamp Addend Register.
If not passed then the system clock will be used and this is fine on some
platforms.
- snps,burst_len: The AXI burst lenth value of the AXI BUS MODE register.
Examples:
gmac0: ethernet@e0800000 {
compatible = "st,spear600-gmac";
reg = <0xe0800000 0x8000>;
interrupt-parent = <&vic1>;
interrupts = <24 23>;
interrupt-names = "macirq", "eth_wake_irq";
mac-address = [000000000000]; /* Filled in by U-Boot */
max-frame-size = <3800>;
phy-mode = "gmii";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
clocks = <&clock>;
clock-names = "stmmaceth";
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/net/ti,dp83867.txt
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* Texas Instruments - dp83867 Giga bit ethernet phy
Required properties:
- reg - The ID number for the phy, usually a small integer
- ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values
- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values
- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
for applicable values
- enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
compensate for the board being designed with the lanes swapped.
- enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
TX/RX lanes.
- ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
for applicable values. The CLK_OUT pin can also
be disabled by this property. When omitted, the
PHY's default will be left as is.
Default child nodes are standard Ethernet PHY device
nodes as described in doc/devicetree/bindings/net/ethernet.txt
Example:
ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
};
Datasheet can be found:
http://www.ti.com/product/DP83867IR/datasheet