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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/bootloader/u-boot-2020.01/doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
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* Atmel PIO4 Controller
The Atmel PIO4 controller is used to select the function of a pin and to
configure it.
Required properties:
- compatible: "atmel,sama5d2-pinctrl".
- reg: base address and length of the PIO controller.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
Each node (or subnode) will list the pins it needs and how to configured these
pins.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: integer array. Each integer represents a pin number plus mux and
ioset settings. Use the macros from boot/dts/<soc>-pinfunc.h file to get the
right representation of the pin.
Optional properties:
- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable,
bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable,
input-debounce.
Example:
#include <sama5d2-pinfunc.h>
...
{
spi0: spi@f8000000 {
cs-gpios = <&pioA 17 0>, <0>, <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
status = "okay";
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
...
pioA: pinctrl@fc038000 {
compatible = "atmel,sama5d2-pinctrl";
reg = <0xfc038000 0x600>;
pinctrl_spi0_default: spi0_default {
pinmux = <PIN_PA14__SPI0_SPCK>,
<PIN_PA15__SPI0_MOSI>,
<PIN_PA16__SPI0_MISO>;
bias-disable;
};
...
};
};
...
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/pinctrl/bcm6838-pinctrl.txt
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* broadcom bcm6838 pinctrl
Required properties for the pinctrl driver:
- compatible: "brcm,bcm6838-pinctrl"
- regmap: specify the gpio test port syscon
- brcm,pins-count: the number of pin
- brcm,functions-count: the number of function
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Example:
gpio_test_port: syscon@14e00294 {
compatible = "syscon";
reg = <0x14e00294 0x1c>;
};
pinctrl: pinctrl {
compatible = "brcm,bcm6838-pinctrl";
regmap = <&gpio_test_port>;
brcm,pins-count = <74>;
brcm,functions-count = <8>;
usb0: usb0 {
usb0_pwrflt {
pins = "69";
function = "1";
};
usb0_pwron {
pins = "70";
function = "1";
};
};
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
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* Marvell Armada 37xx SoC pin and GPIO controller
Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
South Bridge and the other for the North Bridge.
GPIO and pin controller:
------------------------
Main node:
Refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning
of the phrase "pin configuration node".
Required properties for pinctrl driver:
- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
for the South Bridge
"marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
for the North Bridge
- reg: The first set of registers is for pinctrl/GPIO and the second
set is for the interrupt controller
- interrupts: list of interrupts used by the GPIO
Available groups and functions for the North Bridge:
group: jtag
- pins 20-24
- functions jtag, gpio
group sdio0
- pins 8-10
- functions sdio, gpio
group emmc_nb
- pins 27-35
- functions emmc, gpio
group pwm0
- pin 11 (GPIO1-11)
- functions pwm, gpio
group pwm1
- pin 12
- functions pwm, gpio
group pwm2
- pin 13
- functions pwm, gpio
group pwm3
- pin 14
- functions pwm, gpio
group pmic1
- pin 7
- functions pmic, gpio
group pmic0
- pin 6
- functions pmic, gpio
group i2c2
- pins 2-3
- functions i2c, gpio
group i2c1
- pins 0-1
- functions i2c, gpio
group spi_cs1
- pin 17
- functions spi, gpio
group spi_cs2
- pin 18
- functions spi, gpio
group spi_cs3
- pin 19
- functions spi, gpio
group onewire
- pin 4
- functions onewire, gpio
group uart1
- pins 25-26
- functions uart, gpio
group spi_quad
- pins 15-16
- functions spi, gpio
group uart_2
- pins 9-10
- functions uart, gpio
Available groups and functions for the South Bridge:
group usb32_drvvbus0
- pin 36
- functions drvbus, gpio
group usb2_drvvbus1
- pin 37
- functions drvbus, gpio
group sdio_sb
- pins 60-65
- functions sdio, gpio
group rgmii
- pins 42-53
- functions mii, gpio
group pcie1
- pins 39-41
- functions pcie, gpio
group smi
- pins 54-55
- functions smi, gpio
group ptp
- pins 56-58
- functions ptp, gpio
group ptp_clk
- pin 57
- functions ptp, mii
group ptp_trig
- pin 58
- functions ptp, mii
group mii_col
- pin 59
- functions mii, mii_err
GPIO subnode:
Please refer to gpio.txt in "gpio" directory for details of gpio-ranges property
and the common GPIO bindings used by client devices.
Required properties for the GPIO driver under the gpio subnode:
- interrupts: List of interrupt specifiers for the controllers interrupt.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the
second cell specifies GPIO flags, as defined in
<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
GPIO_ACTIVE_LOW flags are supported.
- gpio-ranges: Range of pins managed by the GPIO controller.
Example:
pinctrl_sb: pinctrl-sb@18800 {
compatible = "marvell,armada3710-sb-pinctrl",
"syscon", "simple-mfd";
reg = <0x18800 0x100>, <0x18C00 0x20>;
gpiosb: gpiosb {
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_sb 0 0 30>;
gpio-controller;
interrupts =
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
};
rgmii_pins: mii-pins {
groups = "rgmii";
function = "mii";
};
sdio_pins: sdio-pins {
groups = "sdio_sb";
function = "sdio";
};
pcie_pins: pcie-pins {
groups = "pcie1";
function = "pcie";
};
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt
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Functions of Armada APN806 pin controller
Function 0x0 for any MPP ID activates GPIO pin mode
----------------------------------------------------------------------
MPP# 0x1 0x2 0x3 0x4
----------------------------------------------------------------------
0 SDIO_CLK - SPI0_CLK -
1 SDIO_CMD - SPI0_MISO -
2 SDIO_D[0] - SPI0_MOSI -
3 SDIO_D[1] - SPI0_CS0n -
4 SDIO_D[2] - I2C0_SDA SPI0_CS1n
5 SDIO_D[3] - I2C0_SCK -
6 SDIO_DS - - -
7 SDIO_D[4] - UART1_RXD -
8 SDIO_D[5] - UART1_TXD -
9 SDIO_D[6] - SPI0_CS1n -
10 SDIO_D[7] - - -
11 - - UART0_TXD -
12 SDIO_CARD_PW_OFF SDIO_HW_RST - -
13 - - - -
14 - - - -
15 - - - -
16 - - - -
17 - - - -
18 - - - -
19 - - UART0_RXD -
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/pinctrl/marvell,armada-cp110-pinctrl.txt
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Functions of Armada CP110 pin controller
Function 0x0 for any MPP ID activates GPIO pin mode
Function 0xc for any MPP ID activates DEBUG_BUS pin mode
-------------------------------------------------------------------------------
MPP# 0x1 0x2 0x3 0x4
-------------------------------------------------------------------------------
0 DEV_ALE[1] AU_I2SMCLK GE0_RXD[3] TDM_PCLK
1 DEV_ALE[0] AU_I2SDO_SPDIFO GE0_RXD[2] TDM_DRX
2 DEV_AD[15] AU_I2SEXTCLK GE0_RXD[1] TDM_DTX
3 DEV_AD[14] AU_I2SLRCLK GE0_RXD[0] TDM_FSYNC
4 DEV_AD[13] AU_I2SBCLK GE0_RXCTL TDM_RSTn
5 DEV_AD[12] AU_I2SDI GE0_RXCLK TDM_INTn
6 DEV_AD[11] - GE0_TXD[3] SPI0_CSn[2]
7 DEV_AD[10] - GE0_TXD[2] SPI0_CSn[1]
8 DEV_AD[9] - GE0_TXD[1] SPI0_CSn[0]
9 DEV_AD[8] - GE0_TXD[0] SPI0_MOSI
10 DEV_READYn - GE0_TXCTL SPI0_MISO
11 DEV_WEn[1] - GE0_TXCLKOUT SPI0_CLK
12 DEV_CLK_OUT NF_RBn[1] SPI1_CSn[1] GE0_RXCLK
13 DEV_BURSTn NF_RBn[0] SPI1_MISO GE0_RXCTL
14 DEV_BOOTCSn DEV_CSn[0] SPI1_CSn[0] SPI0_CSn[3]
15 DEV_AD[7] - SPI1_MOSI -
16 DEV_AD[6] - SPI1_CLK -
17 DEV_AD[5] - - GE0_TXD[3]
18 DEV_AD[4] - - GE0_TXD[2]
19 DEV_AD[3] - - GE0_TXD[1]
20 DEV_AD[2] - - GE0_TXD[0]
21 DEV_AD[1] - - GE0_TXCTL
22 DEV_AD[0] - - GE0_TXCLKOUT
23 DEV_A[1] - - -
24 DEV_A[0] - - -
25 DEV_OEn - - - -
26 DEV_WEn[0] - - -
27 DEV_CSn[0] SPI1_MISO MSS_GPIO[4] GE0_RXD[3]
28 DEV_CSn[1] SPI1_CSn[0] MSS_GPIO[5] GE0_RXD[2]
29 DEV_CSn[2] SPI1_MOSI MSS_GPIO[6] GE0_RXD[1]
30 DEV_CSn[3] SPI1_CLK MSS_GPIO[7] GE0_RXD[0]
31 DEV_A[2] - MSS_GPIO[4] -
32 MII_COL MII_TXERR MSS_SPI_MISO TDM_DRX
33 MII_TXCLK SDIO_PWR1[0] MSS_SPI_CSn TDM_FSYNC
34 MII_RXERR SDIO_PWR1[1] MSS_SPI_MOSI TDM_DTX
35 SATA1_PRESENT_ACTIVEn TWSI1_SDA MSS_SPI_CLK TDM_PCLK
36 SYNCE2_CLK TWSI1_SCK PTP_CLK SYNCE1_CLK
37 UART2_RXD TWSI0_SCK PTP_PCLK_OUT TDM_INTn
38 UART2_TXD TWSI0_SDA PTP_PULSE TDM_RSTn
39 SDIO_WR_PROTECT - - AU_I2SBCLK PTP_CLK
40 SDIO_PWR1[1] SYNCE1_CLK MSS_TWSI_SDA AU_I2SDO_SPDIFO
41 SDIO_PWR1[0] SDIO_BUS_PWR MSS_TWSI_SCK AU_I2SLRCLK
42 SDIO_V18_EN SDIO_WR_PROTECT SYNCE2_CLK AU_I2SMCLK
43 SDIO_CARD_DETECT - SYNCE1_CLK AU_I2SEXTCLK
44 GE1_TXD[2] - - -
45 GE1_TXD[3] - - -
46 GE1_TXD[1] - - -
47 GE1_TXD[0] - - -
48 GE1_TXCTL_MII_TXEN - - -
49 GE1_TXCLKOUT MII_CRS - -
50 GE1_RXCLK MSS_TWSI_SDA - -
51 GE1_RXD[0] MSS_TWSI_SCK - -
52 GE1_RXD[1] SYNCE1_CLK - SYNCE2_CLK
53 GE1_RXD[2] - PTP_CLK -
54 GE1_RXD[3] SYNCE2_CLK PTP_PCLK_OUT SYNCE1_CLK
55 GE1_RXCTL_MII_RXDV - PTP_PULSE -
56 - - - TDM_DRX
57 - MSS_TWSI_SDA PTP_PCLK_OUT TDM_INTn
58 - MSS_TWSI_SCK PTP_CLK TDM_RSTn
59 MSS_GPIO[7] SYNCE2_CLK - TDM_FSYNC
60 MSS_GPIO[6] - PTP_PULSE TDM_DTX
61 MSS_GPIO[5] - PTP_CLK TDM_PCLK
62 MSS_GPIO[4] SYNCE1_CLK PTP_PCLK_OUT -
-------------------------------------------------------------------------------
MPP# 0x5 0x6 0x7
-------------------------------------------------------------------------------
0 - PTP_PULSE MSS_TWSI_SDA
1 - PTP_CLK MSS_TWSI_SCK
2 MSS_UART_RXD PTP_PCLK_OUT TWSI1_SCK
3 MSS_UART_TXD PCIe_RSTOUTn TWSI1_SDA
4 MSS_UART_RXD UART1_CTS PCIe0_CLKREQ
5 MSS_UART_TXD UART1_RTS PCIe1_CLKREQ
6 AU_I2SEXTCLK SATA1_PRESENT_ACTIVEn PCIe2_CLKREQ
7 SPI1_CSn[1] SATA0_PRESENT_ACTIVEn LED_DATA
8 SPI1_CSn[0] UART0_CTS LED_STB
9 SPI1_MOSI - PCIe_RSTOUTn
10 SPI1_MISO UART0_CTS SATA1_PRESENT_ACTIVEn
11 SPI1_CLK UART0_RTS LED_CLK
12 - - -
13 - - -
14 AU_I2SEXTCLK SPI0_MISO SATA0_PRESENT_ACTIVEn
15 - SPI0_MOSI -
16 - - -
17 - - -
18 - - -
19 - - -
20 - - -
21 - - -
22 - - -
23 AU_I2SMCLK - -
24 AU_I2SLRCLK - -
25 AU_I2SDO_SPDIFO - -
26 AU_I2SBCLK - -
27 SPI0_CSn[4] - -
28 SPI0_CSn[5] PCIe2_CLKREQ PTP_PULSE
29 SPI0_CSn[6] PCIe1_CLKREQ PTP_CLK
30 SPI0_CSn[7] PCIe0_CLKREQ PTP_PCLK_OUT
31 - PCIe_RSTOUTn -
32 AU_I2SEXTCLK AU_I2SDI GE_MDIO
33 AU_I2SMCLK SDIO_BUS_PWR -
34 AU_I2SLRCLK SDIO_WR_PROTECT GE_MDC
35 AU_I2SDO_SPDIFO SDIO_CARD_DETECT XG_MDIO
36 AU_I2SBCLK SATA0_PRESENT_ACTIVEn XG_MDC
37 MSS_TWSI_SCK SATA1_PRESENT_ACTIVEn GE_MDC
38 MSS_TWSI_SDA SATA0_PRESENT_ACTIVEn GE_MDIO
39 SPI0_CSn[1] - -
40 PTP_PCLK_OUT SPI0_CLK UART1_TXD
41 PTP_PULSE SPI0_MOSI UART1_RXD
42 MSS_UART_TXD SPI0_MISO UART1_CTS
43 MSS_UART_RXD SPI0_CSn[0] UART1_RTS
44 - - UART0_RTS
45 - - UART0_TXD
46 - - UART1_RTS
47 SPI1_CLK - UART1_TXD
48 SPI1_MOSI - -
49 SPI1_MISO - UART1_RXD
50 SPI1_CSn[0] UART2_TXD UART0_RXD
51 SPI1_CSn[1] UART2_RXD UART0_CTS
52 SPI1_CSn[2] - UART1_CTS
53 SPI1_CSn[3] - UART1_RXD
54 - - -
55 - - -
56 AU_I2SDO_SPDIFO SPI0_CLK UART1_RXD
57 AU_I2SBCLK SPI0_MOSI UART1_TXD
58 AU_I2SDI SPI0_MISO UART1_CTS
59 AU_I2SLRCLK SPI0_CSn[0] UART0_CTS
60 AU_I2SMCLK SPI0_CSn[1] UART0_RTS
61 AU_I2SEXTCLK SPI0_CSn[2] UART0_TXD
62 SATA1_PRESENT_ACTIVEn SPI0_CSn[3] UART0_RXD
-------------------------------------------------------------------------------
MPP# 0x8 0x9 0xA
-------------------------------------------------------------------------------
0 UART0_RXD SATA0_PRESENT_ACTIVEn GE_MDIO
1 UART0_TXD SATA1_PRESENT_ACTIVEn GE_MDC
2 UART1_RXD SATA0_PRESENT_ACTIVEn XG_MDC
3 UART1_TXD SATA1_PRESENT_ACTIVEn XG_MDIO
4 UART3_RXD - GE_MDC
5 UART3_TXD - GE_MDIO
6 UART0_RXD PTP_PULSE -
7 UART0_TXD PTP_CLK -
8 UART2_RXD PTP_PCLK_OUT SYNCE1_CLK
9 - - SYNCE2_CLK
10 - - -
11 UART2_TXD SATA0_PRESENT_ACTIVEn -
12 - - -
13 MSS_SPI_MISO - -
14 MSS_SPI_CSn - -
15 MSS_SPI_MOSI - -
16 MSS_SPI_CLK - -
17 - - -
18 - - -
19 - - -
20 - - -
21 - - -
22 - - -
23 - - -
24 - - -
25 - - -
26 - - -
27 GE_MDIO SATA0_PRESENT_ACTIVEn UART0_RTS
28 GE_MDC SATA1_PRESENT_ACTIVEn UART0_CTS
29 MSS_TWSI_SDA SATA0_PRESENT_ACTIVEn UART0_RXD
30 MSS_TWSI_SCK SATA1_PRESENT_ACTIVEn UART0_TXD
31 GE_MDC - -
32 SDIO_V18_EN PCIe1_CLKREQ MSS_GPIO[0]
33 XG_MDIO PCIe2_CLKREQ MSS_GPIO[1]
34 - PCIe0_CLKREQ MSS_GPIO[2]
35 GE_MDIO PCIe_RSTOUTn MSS_GPIO[3]
36 GE_MDC PCIe2_CLKREQ MSS_GPIO[5]
37 XG_MDC PCIe1_CLKREQ MSS_GPIO[6]
38 XG_MDIO AU_I2SEXTCLK MSS_GPIO[7]
39 SATA1_PRESENT_ACTIVEn MSS_GPIO[0]
40 GE_MDIO SATA0_PRESENT_ACTIVEn MSS_GPIO[1]
41 GE_MDC SATA1_PRESENT_ACTIVEn MSS_GPIO[2]
42 XG_MDC SATA0_PRESENT_ACTIVEn MSS_GPIO[4]
43 XG_MDIO SATA1_PRESENT_ACTIVEn MSS_GPIO[5]
44 - - -
45 - PCIe_RSTOUTn -
46 - - -
47 GE_MDC CLKOUT -
48 XG_MDC - -
49 GE_MDIO PCIe0_CLKREQ SDIO_V18_EN
50 XG_MDIO - SDIO_PWR1[1]
51 - - SDIO_PWR1[0]
52 LED_CLK PCIe_RSTOUTn PCIe0_CLKREQ
53 LED_STB - -
54 LED_DATA - SDIO_HW_RST
55 - - SDIO_LED
56 - SATA1_PRESENT_ACTIVEn -
57 - SATA0_PRESENT_ACTIVEn -
58 LED_CLK - -
59 LED_STB UART1_TXD -
60 LED_DATA UART1_RXD -
61 UART2_TXD SATA1_PRESENT_ACTIVEn GE_MDIO
62 UART2_RXD SATA0_PRESENT_ACTIVEn GE_MDC
-------------------------------------------------------------------------------
MPP# 0xB 0xD 0xE
-------------------------------------------------------------------------------
0 - - -
1 - - -
2 - - -
3 - - -
4 - - -
5 - - -
6 - - -
7 - - -
8 - - -
9 - - -
10 - - -
11 - CLKOUT_MPP_11 -
12 - - -
13 - - -
14 - - -
15 PTP_PULSE_CP2CP SAR_IN[5] -
16 - SAR_IN[3] -
17 - SAR_IN[6] -
18 PTP_CLK_CP2CP SAR_IN[11] -
19 WAKEUP_OUT_CP2CP SAR_IN[7] -
20 - SAR_IN[9] -
21 SEI_IN_CP2CP SAR_IN[8] -
22 WAKEUP_IN_CP2CP SAR_IN[10] -
23 LINK_RD_IN_CP2CP SAR_IN[4] -
24 - - -
25 - CLKOUT_MPP_25 -
26 - SAR_IN[0] -
27 REI_IN_CP2CP SAR_IN[1] -
28 LED_DATA SAR_IN[2] -
29 LED_STB AVS_FB_IN_CP2CP -
30 LED_CLK SAR_IN[13] -
31 - - -
32 - SAR_CP2CP_OUT[0] -
33 - SAR_CP2CP_OUT[1] -
34 - SAR_CP2CP_OUT[2] -
35 - SAR_CP2CP_OUT[3] -
36 - CLKIN -
37 LINK_RD_OUT_CP2CP SAR_CP2CP_OUT[4] -
38 PTP_PULSE_CP2CP SAR_CP2CP_OUT[5] -
39 - AVS_FB_OUT_CP2CP -
40 - - -
41 REI_OUT_CP2CP - -
42 - SAR_CP2CP_OUT[9] -
43 WAKEUP_OUT_CP2CP SAR_CP2CP_OUT[10] -
44 PTP_CLK_CP2CP SAR_CP2CP_OUT[11] -
45 - SAR_CP2CP_OUT[6] -
46 - SAR_CP2CP_OUT[13] -
47 - - -
48 WAKEUP_IN_CP2CP SAR_CP2CP_OUT[7] -
49 SEI_OUT_CP2CP SAR_CP2CP_OUT[8] -
50 - - -
51 - - -
52 - - -
53 SDIO_LED - -
54 SDIO_WR_PROTECT - -
55 SDIO_CARD_DETECT - -
56 - - SDIO0_CLK
57 - - SDIO0_CMD
58 - - SDIO0_D[0]
59 - - SDIO0_D[1]
60 - - SDIO0_D[2]
61 - - SDIO0_D[3]
62 - - -
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt
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The pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose
pins (mpp) to a specific function.
A Marvell SoC pin configuration node is a node of a group of pins which can
be used for a specific device or function. Each node requires one or more
mpp pins or group of pins and a mpp function common to all pins.
Required properties for the pinctrl driver:
- compatible: "marvell,mvebu-pinctrl",
"marvell,ap806-pinctrl",
"marvell,armada-7k-pinctrl",
"marvell,armada-8k-cpm-pinctrl",
"marvell,armada-8k-cps-pinctrl"
- bank-name: A string defining the pinc controller bank name
- reg: A pair of values defining the pin controller base address
and the address space
- pin-count: Numeric value defining the amount of multi purpose pins
included in this bank
- max-func: Numeric value defining the maximum function value for
pins in this bank
- pin-func: Array of pin function values for every pin in the bank.
When the function value for a specific pin equal 0xFF,
the pin configuration is skipped and a default function
value is used for this pin.
The A8K is a hybrid SoC that contains several silicon dies interconnected in
a single package. Each such die may have a separate pin controller.
Example:
/ {
ap806 {
config-space {
pinctl: pinctl@6F4000 {
compatible = "marvell,mvebu-pinctrl",
"marvell,ap806-pinctrl";
bank-name ="apn-806";
reg = <0x6F4000 0x10>;
pin-count = <20>;
max-func = <3>;
/* MPP Bus:
* SPI0 [0-3]
* I2C0 [4-5]
* UART0 [11,19]
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 3 3 3 3 3 3 0 0 0 0
0 3 0 0 0 0 0 0 0 3>;
};
};
};
cp110-master {
config-space {
cpm_pinctl: pinctl@44000 {
compatible = "marvell,mvebu-pinctrl",
"marvell,armada-7k-pinctrl",
"marvell,armada-8k-cpm-pinctrl";
bank-name ="cp0-110";
reg = <0x440000 0x20>;
pin-count = <63>;
max-func = <0xf>;
/* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins:
* [11] CLKOUT_MPP_11 (out)
* [23] LINK_RD_IN_CP2CP (in)
* [25] CLKOUT_MPP_25 (out)
* [29] AVS_FB_IN_CP2CP (in)
* [32,34] SMI
* [31] GPIO: push button/Wake
* [35-36] GPIO
* [37-38] I2C
* [40-41] SATA[0/1]_PRESENT_ACTIVEn
* [42-43] XSMI
* [44-55] RGMII1
* [56-62] SD
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0 7 0 7 0 0 2 2 0
0 0 8 8 1 1 1 1 1 1
1 1 1 1 1 1 0xE 0xE 0xE 0xE
0xE 0xE 0xE>;
};
};
};
cp110-slave {
config-space {
cps_pinctl: pinctl@44000 {
compatible = "marvell,mvebu-pinctrl",
"marvell,armada-8k-cps-pinctrl";
bank-name ="cp1-110";
reg = <0x440000 0x20>;
pin-count = <63>;
max-func = <0xf>;
/* MPP Bus:
* [0-11] RGMII0
* [27,31] GE_MDIO/MDC
* [32-62] = 0xff: Keep default CP1_shared_pins:
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
0x3 0x3 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff
0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff>;
};
};
};
}
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/pinctrl/pinctrl-bindings.txt
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== Introduction ==
Hardware modules that control pin multiplexing or configuration parameters
such as pull-up/down, tri-state, drive-strength etc are designated as pin
controllers. Each pin controller must be represented as a node in device tree,
just like any other hardware module.
Hardware modules whose signals are affected by pin configuration are
designated client devices. Again, each client device must be represented as a
node in device tree, just like any other hardware module.
For a client device to operate correctly, certain pin controllers must
set up certain specific pin configurations. Some client devices need a
single static pin configuration, e.g. set up during initialization. Others
need to reconfigure pins at run-time, for example to tri-state pins when the
device is inactive. Hence, each client device can define a set of named
states. The number and names of those states is defined by the client device's
own binding.
The common pinctrl bindings defined in this file provide an infrastructure
for client device device tree nodes to map those state names to the pin
configuration used by those states.
Note that pin controllers themselves may also be client devices of themselves.
For example, a pin controller may set up its own "active" state when the
driver loads. This would allow representing a board's static pin configuration
in a single place, rather than splitting it across multiple client device
nodes. The decision to do this or not somewhat rests with the author of
individual board device tree files, and any requirements imposed by the
bindings for the individual client devices in use by that board, i.e. whether
they require certain specific named states for dynamic pin configuration.
== Pinctrl client devices ==
For each client device individually, every pin state is assigned an integer
ID. These numbers start at 0, and are contiguous. For each state ID, a unique
property exists to define the pin configuration. Each state may also be
assigned a name. When names are used, another property exists to map from
those names to the integer IDs.
Each client device's own binding determines the set of states that must be
defined in its device tree node, and whether to define the set of state
IDs that must be provided, or whether to define the set of state names that
must be provided.
Required properties:
pinctrl-0: List of phandles, each pointing at a pin configuration
node. These referenced pin configuration nodes must be child
nodes of the pin controller that they configure. Multiple
entries may exist in this list so that multiple pin
controllers may be configured, or so that a state may be built
from multiple nodes for a single pin controller, each
contributing part of the overall configuration. See the next
section of this document for details of the format of these
pin configuration nodes.
In some cases, it may be useful to define a state, but for it
to be empty. This may be required when a common IP block is
used in an SoC either without a pin controller, or where the
pin controller does not affect the HW module in question. If
the binding for that IP block requires certain pin states to
exist, they must still be defined, but may be left empty.
Optional properties:
pinctrl-1: List of phandles, each pointing at a pin configuration
node within a pin controller.
...
pinctrl-n: List of phandles, each pointing at a pin configuration
node within a pin controller.
pinctrl-names: The list of names to assign states. List entry 0 defines the
name for integer state ID 0, list entry 1 for state ID 1, and
so on.
For example:
/* For a client device requiring named states */
device {
pinctrl-names = "active", "idle";
pinctrl-0 = <&state_0_node_a>;
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
};
/* For the same device if using state IDs */
device {
pinctrl-0 = <&state_0_node_a>;
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
};
/*
* For an IP block whose binding supports pin configuration,
* but in use on an SoC that doesn't have any pin control hardware
*/
device {
pinctrl-names = "active", "idle";
pinctrl-0 = <>;
pinctrl-1 = <>;
};
== Pin controller devices ==
Pin controller devices should contain the pin configuration nodes that client
devices reference.
For example:
pincontroller {
... /* Standard DT properties for the device itself elided */
state_0_node_a {
...
};
state_1_node_a {
...
};
state_1_node_b {
...
};
}
The contents of each of those pin configuration child nodes is defined
entirely by the binding for the individual pin controller device. There
exists no common standard for this content.
The pin configuration nodes need not be direct children of the pin controller
device; they may be grandchildren, for example. Whether this is legal, and
whether there is any interaction between the child and intermediate parent
nodes, is again defined entirely by the binding for the individual pin
controller device.
== Generic pin multiplexing node content ==
pin multiplexing nodes:
function - the mux function to select
groups - the list of groups to select with this function
(either this or "pins" must be specified)
pins - the list of pins to select with this function (either
this or "groups" must be specified)
Example:
state_0_node_a {
uart0 {
function = "uart0";
groups = "u0rxtx", "u0rtscts";
};
};
state_1_node_a {
spi0 {
function = "spi0";
groups = "spi0pins";
};
};
state_2_node_a {
function = "i2c0";
pins = "mfio29", "mfio30";
};
== Generic pin configuration node content ==
Many data items that are represented in a pin configuration node are common
and generic. Pin control bindings should use the properties defined below
where they are applicable; not all of these properties are relevant or useful
for all hardware or binding structures. Each individual binding document
should state which of these generic properties, if any, are used, and the
structure of the DT nodes that contain these properties.
Supported generic properties are:
pins - the list of pins that properties in the node
apply to (either this or "group" has to be
specified)
group - the group to apply the properties to, if the driver
supports configuration of whole groups rather than
individual pins (either this or "pins" has to be
specified)
bias-disable - disable any pin bias
bias-high-impedance - high impedance mode ("third-state", "floating")
bias-bus-hold - latch weakly
bias-pull-up - pull up the pin
bias-pull-down - pull down the pin
bias-pull-pin-default - use pin-default pull state
drive-push-pull - drive actively high and low
drive-open-drain - drive with open drain
drive-open-source - drive with open source
drive-strength - sink or source at most X mA
input-enable - enable input on pin (no effect on output)
input-disable - disable input on pin (no effect on output)
input-schmitt-enable - enable schmitt-trigger mode
input-schmitt-disable - disable schmitt-trigger mode
input-debounce - debounce mode with debound time X
power-source - select between different power supplies
low-power-enable - enable low power mode
low-power-disable - disable low power mode
output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
slew-rate - set the slew rate
For example:
state_0_node_a {
cts_rxd {
pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
bias-pull-up;
};
};
state_1_node_a {
rts_txd {
pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
output-high;
};
};
state_2_node_a {
foo {
group = "foo-group";
bias-pull-up;
};
};
Some of the generic properties take arguments. For those that do, the
arguments are described below.
- pins takes a list of pin names or IDs as a required argument. The specific
binding for the hardware defines:
- Whether the entries are integers or strings, and their meaning.
- bias-pull-up, -down and -pin-default take as optional argument on hardware
supporting it the pull strength in Ohm. bias-disable will disable the pull.
- drive-strength takes as argument the target strength in mA.
- input-debounce takes the debounce time in usec as argument
or 0 to disable debouncing
More in-depth documentation on these parameters can be found in
<include/linux/pinctrl/pinconf-generic.h>
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt
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* Rockchip Pinmux Controller
The Rockchip Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are several
muxing options with option 0 being the use as a GPIO.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The Rockchip pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and
config of the pins in that group. The 'pins' selects the function mode(also
named pin mode) this pin can work on and the 'config' configures various pad
settings such as pull-up, etc.
The pins are grouped into up to 5 individual pin banks which need to be
defined as gpio sub-nodes of the pinmux controller.
Required properties for iomux controller:
- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
"rockchip,rk3288-pinctrl"
- rockchip,grf: phandle referencing a syscon providing the
"general register files"
Optional properties for iomux controller:
- rockchip,pmu: phandle referencing a syscon providing the pmu registers
as some SoCs carry parts of the iomux controller registers there.
Required for at least rk3188 and rk3288.
Deprecated properties for iomux controller:
- reg: first element is the general register space of the iomux controller
It should be large enough to contain also separate pull registers.
second element is the separate pull register space of the rk3188.
Use rockchip,grf and rockchip,pmu described above instead.
Required properties for gpio sub nodes:
- compatible: "rockchip,gpio-bank"
- reg: register of the gpio bank (different than the iomux registerset)
- interrupts: base interrupt of the gpio bank in the interrupt controller
- clocks: clock that drives this bank
- gpio-controller: identifies the node as a gpio controller and pin bank.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See generic
GPIO binding documentation for description of particular cells.
- interrupt-controller: identifies the controller node as interrupt-parent.
- #interrupt-cells: the value of this property should be 2 and the interrupt
cells should use the standard two-cell scheme described in
bindings/interrupt-controller/interrupts.txt
Deprecated properties for gpio sub nodes:
- compatible: "rockchip,rk3188-gpio-bank0"
- reg: second element: separate pull register for rk3188 bank0, use
rockchip,pmu described above instead
Required properties for pin configuration node:
- rockchip,pins: 3 integers array, represents a group of pins mux and config
setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
The MUX 0 means gpio and MUX 1 to N mean the specific device function.
The phandle of a node containing the generic pinconfig options
to use, as described in pinctrl-bindings.txt in this directory.
Examples:
#include <dt-bindings/pinctrl/rockchip.h>
...
pinctrl@20008000 {
compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@20034000 {
compatible = "rockchip,gpio-bank";
reg = <0x20034000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...
pcfg_pull_default: pcfg_pull_default {
bias-pull-pin-default
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
<RK_GPIO1 9 1 &pcfg_pull_default>;
};
};
};
uart2: serial@20064000 {
compatible = "snps,dw-apb-uart";
reg = <0x20064000 0x400>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&mux_uart2>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
};
Example for rk3188:
pinctrl@20008000 {
compatible = "rockchip,rk3188-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmu>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@0x2000a000 {
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@0x2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...
};
source/bootloader/u-boot-2020.01/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt
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* STM32 GPIO and Pin Mux/Config controller
STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
controller. It controls the input/output settings on the available pins and
also provides ability to multiplex and configure the output of various on-chip
controllers onto these pads.
Pin controller node:
Required properies:
- compatible: value should be one of the following:
"st,stm32f429-pinctrl"
"st,stm32f469-pinctrl"
"st,stm32f746-pinctrl"
"st,stm32f769-pinctrl"
"st,stm32h743-pinctrl"
"st,stm32mp157-pinctrl"
"st,stm32mp157-z-pinctrl"
- #address-cells: The value of this property must be 1
- #size-cells : The value of this property must be 1
- ranges : defines mapping between pin controller node (parent) to
gpio-bank node (children).
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
GPIO controller/bank node:
Required properties:
- gpio-controller : Indicates this device is a GPIO controller
- #gpio-cells : Should be two.
The first cell is the pin number
The second one is the polarity:
- 0 for active high
- 1 for active low
- reg : The gpio address range, relative to the pinctrl range
- clocks : clock that drives this bank
- st,bank-name : Should be a name string for this bank as specified in
the datasheet
Optional properties:
- reset: : Reference to the reset controller
- st,syscfg: Should be phandle/offset/mask.
-The phandle to the syscon node which includes IRQ mux selection register.
-The offset of the IRQ mux selection register
-The field mask of IRQ mux, needed if different of 0xf.
- gpio-ranges: Define a dedicated mapping between a pin-controller and
a gpio controller. Format is <&phandle a b c> with:
-(phandle): phandle of pin-controller.
-(a): gpio base offset in range.
-(b): pin base offset in range.
-(c): gpio count in range
This entry has to be used either if there are holes inside a bank:
GPIOB0/B1/B2/B14/B15 (see example 2)
or if banks are not contiguous:
GPIOA/B/C/E...
NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
have to use a "gpio-ranges" entry.
More details in Documentation/devicetree/bindings/gpio/gpio.txt.
- st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
used to select GPIOs as interrupts).
- hwlocks: reference to a phandle of a hardware spinlock provider node.
- st,package: Indicates the SOC package used.
More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
Example 1:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
...
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
ranges = <0 0x40020000 0x3000>;
pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x400>;
resets = <&reset_ahb1 0>;
st,bank-name = "GPIOA";
};
...
pin-functions nodes follow...
};
Example 2:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
...
pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
ranges = <0 0x40020000 0x3000>;
pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x400>;
resets = <&reset_ahb1 0>;
st,bank-name = "GPIOA";
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x400>;
resets = <&reset_ahb1 0>;
st,bank-name = "GPIOB";
ngpios = 4;
gpio-ranges = <&pinctrl 0 16 3>,
<&pinctrl 14 30 2>;
};
...
pin-functions nodes follow...
};
Contents of function subnode node:
----------------------------------
Subnode format
A pinctrl node should contain at least one subnode representing the
pinctrl group available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive, output high/low and output speed.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined in
dt-bindings/pinctrl/<soc>-pinfunc.h directly.
These defines are calculated as:
((port * 16 + line) << 8) | function
With:
- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
- function: The function number, can be:
* 0 : GPIO
* 1 : Alternate Function 0
* 2 : Alternate Function 1
* 3 : Alternate Function 2
* ...
* 16 : Alternate Function 15
* 17 : Analog
To simplify the usage, macro is available to generate "pinmux" field.
This macro is available here:
- include/dt-bindings/pinctrl/stm32-pinfunc.h
Some examples of using macro:
/* GPIO A9 set as alernate function 2 */
... {
pinmux = <STM32_PINMUX('A', 9, AF2)>;
};
/* GPIO A9 set as GPIO */
... {
pinmux = <STM32_PINMUX('A', 9, GPIO)>;
};
/* GPIO A9 set as analog */
... {
pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
};
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use.
Available options are:
- bias-disable,
- bias-pull-down,
- bias-pull-up,
- drive-push-pull,
- drive-open-drain,
- output-low
- output-high
- slew-rate = <x>, with x being:
< 0 > : Low speed
< 1 > : Medium speed
< 2 > : Fast speed
< 3 > : High speed
Example:
pin-controller {
...
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 10, AF7)>;
bias-disable;
};
};
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
};