GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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Soft SPI
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The soft SPI bus implementation allows the use of GPIO pins to simulate a
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SPI bus. No SPI host is required for this to work. The down-side is that the
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performance will typically be much lower than a real SPI bus.
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The soft SPI node requires the following properties:
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Mandatory properties:
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compatible: "spi-gpio"
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cs-gpios: GPIOs to use for SPI chip select (output)
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gpio-sck: GPIO to use for SPI clock (output)
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And at least one of:
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gpio-mosi: GPIO to use for SPI MOSI line (output)
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gpio-miso: GPIO to use for SPI MISO line (input)
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Optional propertie:
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spi-delay-us: Number of microseconds of delay between each CS transition
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The GPIOs should be specified as required by the GPIO controller referenced.
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The first cell holds the phandle of the controller and the second cell
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typically holds the GPIO number.
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Example:
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soft-spi {
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compatible = "spi-gpio";
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cs-gpios = <&gpio 235 0>; /* Y43 */
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gpio-sck = <&gpio 225 0>; /* Y31 */
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gpio-mosi = <&gpio 227 0>; /* Y33 */
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gpio-miso = <&gpio 224 0>; /* Y30 */
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spi-delay-us = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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cs@0 {
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};
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};
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Andestech ATCSPI200 SPI controller Device Tree Bindings
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-------------------------------------------------------
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ATCSPI200 is a Serial Peripheral Interface (SPI) controller
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which serves as a SPI master or a SPI slave.
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It is often be embedded in AE3XX and AE250 platforms.
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Required properties:
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- compatible: has to be "andestech,atcspi200".
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- reg: Base address and size of the controllers memory area.
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- #address-cells: <1>, as required by generic SPI binding.
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- #size-cells: <0>, also as required by generic SPI binding.
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- interrupts: Property with a value describing the interrupt number.
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- clocks: Clock phandles (see clock bindings for details).
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- spi-max-frequency: Maximum SPI clocking speed of device in Hz.
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Optional properties:
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- num-cs: Number of chip selects used.
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Example:
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spi: spi@f0b00000 {
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compatible = "andestech,atcspi200";
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reg = <0xf0b00000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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clocks = <&spiclk>;
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interrupts = <3 4>;
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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spi-cpol;
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spi-cpha;
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};
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};
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@@ -0,0 +1,19 @@
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Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
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Required properties:
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- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
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- reg: Base address and size of the controllers memory area
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- #address-cells: <1>, as required by generic SPI binding.
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- #size-cells: <0>, also as required by generic SPI binding.
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Child nodes as per the generic SPI binding.
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Example:
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spi@1f000000 {
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compatible = "qca,ar9132-spi", "qca,ar7100-spi";
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reg = <0x1f000000 0x10>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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@@ -0,0 +1,94 @@
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SPI (Serial Peripheral Interface) busses
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SPI busses can be described with a node for the SPI master device
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and a set of child nodes for each SPI slave on the bus. For this
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discussion, it is assumed that the system's SPI controller is in
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SPI master mode. This binding does not describe SPI controllers
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in slave mode.
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The SPI master node requires the following properties:
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- #address-cells - number of cells required to define a chip select
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address on the SPI bus.
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- #size-cells - should be zero.
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- compatible - name of SPI bus controller following generic names
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recommended practice.
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- cs-gpios - (optional) gpios chip select.
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No other properties are required in the SPI bus node. It is assumed
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that a driver for an SPI bus device will understand that it is an SPI bus.
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However, the binding does not attempt to define the specific method for
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assigning chip select numbers. Since SPI chip select configuration is
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flexible and non-standardized, it is left out of this binding with the
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assumption that board specific platform code will be used to manage
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chip selects. Individual drivers can define additional properties to
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support describing the chip select layout.
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Optional property:
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- num-cs : total number of chipselects
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If cs-gpios is used the number of chip select will automatically increased
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with max(cs-gpios > hw cs)
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So if for example the controller has 2 CS lines, and the cs-gpios
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property looks like this:
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cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
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Then it should be configured so that num_chipselect = 4 with the
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following mapping:
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cs0 : &gpio1 0 0
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cs1 : native
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cs2 : &gpio1 1 0
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cs3 : &gpio1 2 0
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SPI slave nodes must be children of the SPI master node and can
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contain the following properties.
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- reg - (required) chip select address of device.
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- compatible - (required) name of SPI device following generic names
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recommended practice
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- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
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- spi-cpol - (optional) Empty property indicating device requires
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inverse clock polarity (CPOL) mode
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- spi-cpha - (optional) Empty property indicating device requires
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shifted clock phase (CPHA) mode
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- spi-cs-high - (optional) Empty property indicating device requires
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chip select active high
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- spi-3wire - (optional) Empty property indicating device requires
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3-wire mode.
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- spi-tx-bus-width - (optional) The bus width(number of data wires) that
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used for MOSI. Defaults to 1 if not present.
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- spi-rx-bus-width - (optional) The bus width(number of data wires) that
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used for MISO. Defaults to 1 if not present.
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- spi-half-duplex - (optional) Indicates that the SPI bus should wait for
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a header byte before reading data from the slave.
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Some SPI controllers and devices support Dual and Quad SPI transfer mode.
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It allows data in SPI system transferred in 2 wires(DUAL) or 4 wires(QUAD).
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Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
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only 1(SINGLE), 2(DUAL) and 4(QUAD).
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Dual/Quad mode is not allowed when 3-wire mode is used.
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If a gpio chipselect is used for the SPI slave the gpio number will be passed
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via the cs_gpio
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SPI example for an MPC5200 SPI bus:
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spi@f00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
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reg = <0xf00 0x20>;
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interrupts = <2 13 0 2 14 0>;
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interrupt-parent = <&mpc5200_pic>;
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ethernet-switch@0 {
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compatible = "micrel,ks8995m";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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codec@1 {
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compatible = "ti,tlv320aic26";
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spi-max-frequency = <100000>;
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reg = <1>;
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};
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};
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@@ -0,0 +1,31 @@
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Cadence QSPI controller device tree bindings
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--------------------------------------------
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Required properties:
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- compatible : should be "cdns,qspi-nor"
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- reg : 1.Physical base address and size of SPI registers map.
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2. Physical base address & size of NOR Flash.
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- clocks : Clock phandles (see clock bindings for details).
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- cdns,fifo-depth : Size of the data FIFO in words.
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- cdns,fifo-width : Bus width of the data FIFO in bytes.
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- cdns,trigger-address : 32-bit indirect AHB trigger address.
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- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
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- status : enable in requried dts.
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connected flash properties
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--------------------------
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- spi-max-frequency : Max supported spi frequency.
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- page-size : Flash page size.
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- block-size : Flash memory block size.
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- cdns,tshsl-ns : Added delay in master reference clocks (ref_clk) for
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the length that the master mode chip select outputs
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are de-asserted between transactions.
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- cdns,tsd2d-ns : Delay in master reference clocks (ref_clk) between one
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chip select being de-activated and the activation of
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another.
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- cdns,tchsh-ns : Delay in master reference clocks between last bit of
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current transaction and de-asserting the device chip
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select (n_ss_out).
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- cdns,tslch-ns : Delay in master reference clocks between setting
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n_ss_out low and first bit transfer
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@@ -0,0 +1,30 @@
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Freescale ColdFire DSPI controller
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Required properties:
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- compatible : "fsl,mcf-dspi"
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- #address-cells: <1>, as required by generic SPI binding
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- #size-cells: <0>, also as required by generic SPI binding
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- reg : offset and length of the register set for the device
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Optional properties:
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- spi-max-frequency : max supported spi frequency
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- num-cs : the number of the chipselect signals
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- spi-mode: spi motorola mode, 0 to 3
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- ctar-params: CTAR0 to 7 register configuration, as an array
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of 8 integer fields for each register, where each register
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is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>.
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Example:
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dspi0: dspi@fc05c000 {
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compatible = "fsl,mcf-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfc05c000 0x100>;
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spi-max-frequency = <50000000>;
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num-cs = <4>;
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spi-mode = <0>;
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ctar-fields = <7, 0, 0, 0, 0, 0, 1, 6>,
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<7, 0, 0, 0, 0, 0, 1, 6>,
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<7, 0, 0, 0, 0, 0, 1, 6>;
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};
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@@ -0,0 +1,44 @@
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* STMicroelectronics Quad Serial Peripheral Interface(QSPI)
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Required properties:
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- compatible: should be "st,stm32f469-qspi"
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- reg: the first contains the register location and length.
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the second contains the memory mapping address and length
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- reg-names: should contain the reg names "qspi" "qspi_mm"
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- interrupts: should contain the interrupt for the device
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- clocks: the phandle of the clock needed by the QSPI controller
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- A pinctrl must be defined to set pins in mode of operation for QSPI transfer
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Optional properties:
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- resets: must contain the phandle to the reset controller.
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A spi flash (NOR/NAND) must be a child of spi node and could have some
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properties. Also see jedec,spi-nor.txt.
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Required properties:
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- reg: chip-Select number (QSPI controller may connect 2 flashes)
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- spi-max-frequency: max frequency of spi bus
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Optional property:
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- spi-rx-bus-width: see ./spi-bus.txt for the description
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Example:
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qspi: spi@a0001000 {
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compatible = "st,stm32f469-qspi";
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reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
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reg-names = "qspi", "qspi_mm";
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interrupts = <91>;
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resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
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clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi0>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>;
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...
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};
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};
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@@ -0,0 +1,26 @@
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Xilinx Zynq QSPI controller Device Tree Bindings
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-------------------------------------------------
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Required properties:
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- compatible : Should be "xlnx,zynq-qspi-1.0".
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- reg : Physical base address and size of QSPI registers map.
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- interrupts : Property with a value describing the interrupt
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number.
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- interrupt-parent : Must be core interrupt controller
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- clock-names : List of input clock names - "ref_clk", "pclk"
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(See clock bindings for details).
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- clocks : Clock phandles (see clock bindings for details).
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Optional properties:
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- num-cs : Number of chip selects used.
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Example:
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qspi@e000d000 {
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compatible = "xlnx,zynq-qspi-1.0";
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clock-names = "ref_clk", "pclk";
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clocks = <&clkc 10>, <&clkc 43>;
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interrupt-parent = <&intc>;
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interrupts = <0 19 4>;
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num-cs = <1>;
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reg = <0xe000d000 0x1000>;
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} ;
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@@ -0,0 +1,32 @@
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Cadence SPI controller Device Tree Bindings
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-------------------------------------------
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Required properties:
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- compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
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- reg : Physical base address and size of SPI registers map.
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- interrupts : Property with a value describing the interrupt
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number.
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- interrupt-parent : Must be core interrupt controller
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- clock-names : List of input clock names - "ref_clk", "pclk"
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(See clock bindings for details).
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- clocks : Clock phandles (see clock bindings for details).
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- spi-max-frequency : Maximum SPI clocking speed of device in Hz
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Optional properties:
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- num-cs : Number of chip selects used.
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If a decoder is used, this will be the number of
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chip selects after the decoder.
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- is-decoded-cs : Flag to indicate whether decoder is used or not.
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Example:
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spi@e0007000 {
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compatible = "xlnx,zynq-spi-r1p6";
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clock-names = "ref_clk", "pclk";
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clocks = <&clkc 26>, <&clkc 35>;
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interrupt-parent = <&intc>;
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interrupts = <0 49 4>;
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num-cs = <4>;
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is-decoded-cs = <0>;
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reg = <0xe0007000 0x1000>;
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} ;
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@@ -0,0 +1,4 @@
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Altera SPI
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Required properties:
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- compatible : should be "altr,spi-1.0".
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