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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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source/bootloader/u-boot-2020.01/drivers/clk/mediatek/Makefile
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# SPDX-License-Identifier: GPL-2.0
# Core
obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
source/bootloader/u-boot-2020.01/drivers/clk/mediatek/clk-mt7623.c
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// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek clock driver for MT7623 SoC
*
* Copyright (C) 2018 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com>
*/
#include <common.h>
#include <dm.h>
#include <asm/arch-mediatek/reset.h>
#include <asm/io.h>
#include <dt-bindings/clock/mt7623-clk.h>
#include "clk-mtk.h"
#define MT7623_CLKSQ_STB_CON0 0x18
#define MT7623_PLL_ISO_CON0 0x24
#define MT7623_PLL_FMAX (2000UL * MHZ)
#define MT7623_CON0_RST_BAR BIT(27)
#define MCU_AXI_DIV 0x60
#define AXI_DIV_MSK GENMASK(4, 0)
#define AXI_DIV_SEL(x) (x)
/* apmixedsys */
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _pcw_reg, _pcw_shift) { \
.id = _id, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.rst_bar_mask = MT7623_CON0_RST_BAR, \
.fmax = MT7623_PLL_FMAX, \
.flags = _flags, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
}
static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
21, 0x204, 24, 0x204, 0),
PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
21, 0x210, 4, 0x214, 0),
PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
7, 0x220, 4, 0x224, 14),
PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
21, 0x230, 4, 0x234, 0),
PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
21, 0x240, 4, 0x244, 0),
PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0,
21, 0x250, 4, 0x254, 0),
PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0,
31, 0x270, 4, 0x274, 0),
PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
31, 0x280, 4, 0x284, 0),
PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0,
31, 0x290, 4, 0x294, 0),
PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0,
31, 0x2a0, 4, 0x2a4, 0),
PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0,
31, 0x2b0, 4, 0x2b4, 0),
PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0,
31, 0x2c0, 4, 0x2c4, 0),
PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x00000001, 0,
21, 0x2d0, 4, 0x2d4, 0),
};
/* topckgen */
#define FACTOR0(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
#define FACTOR1(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
#define FACTOR2(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, 0)
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000),
FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ),
FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0),
FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0),
FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0),
};
static const struct mtk_fixed_factor top_fixed_divs[] = {
FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1),
FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2),
FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4),
FACTOR1(CLK_TOP_SYSPLL1_D8, CLK_TOP_SYSPLL_D2, 1, 8),
FACTOR1(CLK_TOP_SYSPLL1_D16, CLK_TOP_SYSPLL_D2, 1, 16),
FACTOR1(CLK_TOP_SYSPLL2_D2, CLK_TOP_SYSPLL_D3, 1, 2),
FACTOR1(CLK_TOP_SYSPLL2_D4, CLK_TOP_SYSPLL_D3, 1, 4),
FACTOR1(CLK_TOP_SYSPLL2_D8, CLK_TOP_SYSPLL_D3, 1, 8),
FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2),
FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4),
FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2),
FACTOR1(CLK_TOP_SYSPLL4_D4, CLK_TOP_SYSPLL_D7, 1, 4),
FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 1),
FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7),
FACTOR0(CLK_TOP_UNIVPLL_D26, CLK_APMIXED_UNIVPLL, 1, 26),
FACTOR0(CLK_TOP_UNIVPLL_D52, CLK_APMIXED_UNIVPLL, 1, 52),
FACTOR0(CLK_TOP_UNIVPLL_D108, CLK_APMIXED_UNIVPLL, 1, 108),
FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2),
FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL_D2, 1, 4),
FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL_D2, 1, 8),
FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL_D3, 1, 2),
FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL_D3, 1, 4),
FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL_D3, 1, 8),
FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL_D3, 1, 16),
FACTOR1(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL_D3, 1, 32),
FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL_D5, 1, 2),
FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL_D5, 1, 4),
FACTOR1(CLK_TOP_UNIVPLL3_D8, CLK_TOP_UNIVPLL_D5, 1, 8),
FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4),
FACTOR0(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, 8),
FACTOR0(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1),
FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2),
FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4),
FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1),
FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
FACTOR0(CLK_TOP_TVDPLL_D2, CLK_APMIXED_TVDPLL, 1, 2),
FACTOR0(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4),
FACTOR0(CLK_TOP_VDECPLL, CLK_APMIXED_VDECPLL, 1, 1),
FACTOR0(CLK_TOP_TVD2PLL, CLK_APMIXED_TVD2PLL, 1, 1),
FACTOR0(CLK_TOP_TVD2PLL_D2, CLK_APMIXED_TVD2PLL, 1, 2),
FACTOR1(CLK_TOP_MIPIPLL, CLK_TOP_DPI, 1, 1),
FACTOR1(CLK_TOP_MIPIPLL_D2, CLK_TOP_DPI, 1, 2),
FACTOR1(CLK_TOP_MIPIPLL_D4, CLK_TOP_DPI, 1, 4),
FACTOR1(CLK_TOP_HDMIPLL, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 1),
FACTOR1(CLK_TOP_HDMIPLL_D2, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 2),
FACTOR1(CLK_TOP_HDMIPLL_D3, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 3),
FACTOR0(CLK_TOP_ARMPLL_1P3G, CLK_APMIXED_ARMPLL, 1, 1),
FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1),
FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4),
FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8),
FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16),
FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24),
FACTOR0(CLK_TOP_AUD1PLL_98M, CLK_APMIXED_AUD1PLL, 1, 3),
FACTOR0(CLK_TOP_AUD2PLL_90M, CLK_APMIXED_AUD2PLL, 1, 3),
FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3),
FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1),
FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1),
FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793),
FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1),
};
static const int axi_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_SYSPLL_D5,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_UNIVPLL_D5,
CLK_TOP_UNIVPLL2_D2,
CLK_TOP_MMPLL_D2,
CLK_TOP_DMPLL_D2
};
static const int mem_parents[] = {
CLK_XTAL,
CLK_TOP_DMPLL
};
static const int ddrphycfg_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D8
};
static const int mm_parents[] = {
CLK_XTAL,
CLK_TOP_VENCPLL,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_UNIVPLL_D5,
CLK_TOP_UNIVPLL1_D2,
CLK_TOP_UNIVPLL2_D2,
CLK_TOP_DMPLL
};
static const int pwm_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL2_D4,
CLK_TOP_UNIVPLL3_D2,
CLK_TOP_UNIVPLL1_D4
};
static const int vdec_parents[] = {
CLK_XTAL,
CLK_TOP_VDECPLL,
CLK_TOP_SYSPLL_D5,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_UNIVPLL_D5,
CLK_TOP_UNIVPLL2_D2,
CLK_TOP_VENCPLL,
CLK_TOP_MSDCPLL_D2,
CLK_TOP_MMPLL_D2
};
static const int mfg_parents[] = {
CLK_XTAL,
CLK_TOP_MMPLL,
CLK_TOP_DMPLL_X2,
CLK_TOP_MSDCPLL,
CLK_XTAL,
CLK_TOP_SYSPLL_D3,
CLK_TOP_UNIVPLL_D3,
CLK_TOP_UNIVPLL1_D2
};
static const int camtg_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL_D26,
CLK_TOP_UNIVPLL2_D2,
CLK_TOP_SYSPLL3_D2,
CLK_TOP_SYSPLL3_D4,
CLK_TOP_MSDCPLL_D2,
CLK_TOP_MMPLL_D2
};
static const int uart_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL2_D8
};
static const int spi_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL3_D2,
CLK_TOP_SYSPLL4_D2,
CLK_TOP_UNIVPLL2_D4,
CLK_TOP_UNIVPLL1_D8
};
static const int usb20_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL1_D8,
CLK_TOP_UNIVPLL3_D4
};
static const int msdc30_parents[] = {
CLK_XTAL,
CLK_TOP_MSDCPLL_D2,
CLK_TOP_SYSPLL2_D2,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_UNIVPLL1_D4,
CLK_TOP_UNIVPLL2_D4,
};
static const int aud_intbus_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_SYSPLL3_D2,
CLK_TOP_SYSPLL4_D2,
CLK_TOP_UNIVPLL3_D2,
CLK_TOP_UNIVPLL2_D4
};
static const int pmicspi_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D8,
CLK_TOP_SYSPLL2_D4,
CLK_TOP_SYSPLL4_D2,
CLK_TOP_SYSPLL3_D4,
CLK_TOP_SYSPLL2_D8,
CLK_TOP_SYSPLL1_D16,
CLK_TOP_UNIVPLL3_D4,
CLK_TOP_UNIVPLL_D26,
CLK_TOP_DMPLL_D2,
CLK_TOP_DMPLL_D4
};
static const int scp_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D8,
CLK_TOP_DMPLL_D2,
CLK_TOP_DMPLL_D4
};
static const int dpi0_tve_parents[] = {
CLK_XTAL,
CLK_TOP_MIPIPLL,
CLK_TOP_MIPIPLL_D2,
CLK_TOP_MIPIPLL_D4,
CLK_XTAL,
CLK_TOP_TVDPLL,
CLK_TOP_TVDPLL_D2,
CLK_TOP_TVDPLL_D4
};
static const int dpi1_parents[] = {
CLK_XTAL,
CLK_TOP_TVDPLL,
CLK_TOP_TVDPLL_D2,
CLK_TOP_TVDPLL_D4
};
static const int hdmi_parents[] = {
CLK_XTAL,
CLK_TOP_HDMIPLL,
CLK_TOP_HDMIPLL_D2,
CLK_TOP_HDMIPLL_D3
};
static const int apll_parents[] = {
CLK_XTAL,
CLK_TOP_AUDPLL,
CLK_TOP_AUDPLL_D4,
CLK_TOP_AUDPLL_D8,
CLK_TOP_AUDPLL_D16,
CLK_TOP_AUDPLL_D24,
CLK_XTAL,
CLK_XTAL
};
static const int rtc_parents[] = {
CLK_TOP_32K_INTERNAL,
CLK_TOP_32K_EXTERNAL,
CLK_XTAL,
CLK_TOP_UNIVPLL3_D8
};
static const int nfi2x_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL2_D2,
CLK_TOP_SYSPLL_D7,
CLK_TOP_UNIVPLL3_D2,
CLK_TOP_SYSPLL2_D4,
CLK_TOP_UNIVPLL3_D4,
CLK_TOP_SYSPLL4_D4,
CLK_XTAL
};
static const int emmc_hclk_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_SYSPLL2_D2
};
static const int flash_parents[] = {
CLK_TOP_CLK26M_D8,
CLK_XTAL,
CLK_TOP_SYSPLL2_D8,
CLK_TOP_SYSPLL3_D4,
CLK_TOP_UNIVPLL3_D4,
CLK_TOP_SYSPLL4_D2,
CLK_TOP_SYSPLL2_D4,
CLK_TOP_UNIVPLL2_D4
};
static const int di_parents[] = {
CLK_XTAL,
CLK_TOP_TVD2PLL,
CLK_TOP_TVD2PLL_D2,
CLK_XTAL
};
static const int nr_osd_parents[] = {
CLK_XTAL,
CLK_TOP_VENCPLL,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_UNIVPLL_D5,
CLK_TOP_UNIVPLL1_D2,
CLK_TOP_UNIVPLL2_D2,
CLK_TOP_DMPLL
};
static const int hdmirx_bist_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL_D3,
CLK_XTAL,
CLK_TOP_SYSPLL1_D16,
CLK_TOP_SYSPLL4_D2,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_VENCPLL,
CLK_XTAL
};
static const int intdir_parents[] = {
CLK_XTAL,
CLK_TOP_MMPLL,
CLK_TOP_SYSPLL_D2,
CLK_TOP_UNIVPLL_D2
};
static const int asm_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL2_D4,
CLK_TOP_UNIVPLL2_D2,
CLK_TOP_SYSPLL_D5
};
static const int ms_card_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL3_D8,
CLK_TOP_SYSPLL4_D4
};
static const int ethif_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_SYSPLL_D5,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_UNIVPLL_D5,
CLK_TOP_UNIVPLL1_D2,
CLK_TOP_DMPLL,
CLK_TOP_DMPLL_D2
};
static const int hdmirx_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL_D52
};
static const int cmsys_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_UNIVPLL1_D2,
CLK_TOP_UNIVPLL_D5,
CLK_TOP_SYSPLL_D5,
CLK_TOP_SYSPLL2_D2,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_SYSPLL3_D2,
CLK_TOP_SYSPLL2_D4,
CLK_TOP_SYSPLL1_D8,
CLK_XTAL,
CLK_XTAL,
CLK_XTAL,
CLK_XTAL,
CLK_XTAL
};
static const int clk_8bdac_parents[] = {
CLK_TOP_32K_INTERNAL,
CLK_TOP_8BDAC,
CLK_XTAL,
CLK_XTAL
};
static const int aud2dvd_parents[] = {
CLK_TOP_AUD_48K_TIMING,
CLK_TOP_AUD_44K_TIMING
};
static const int padmclk_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL_D26,
CLK_TOP_UNIVPLL_D52,
CLK_TOP_UNIVPLL_D108,
CLK_TOP_UNIVPLL2_D8,
CLK_TOP_UNIVPLL2_D16,
CLK_TOP_UNIVPLL2_D32
};
static const int aud_mux_parents[] = {
CLK_XTAL,
CLK_TOP_AUD1PLL_98M,
CLK_TOP_AUD2PLL_90M,
CLK_TOP_HADDS2PLL_98M,
CLK_TOP_AUD_EXTCK1_DIV,
CLK_TOP_AUD_EXTCK2_DIV
};
static const int aud_src_parents[] = {
CLK_TOP_AUD_MUX1_SEL,
CLK_TOP_AUD_MUX2_SEL
};
static const struct mtk_composite top_muxes[] = {
MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31,
CLK_DOMAIN_SCPSYS),
MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15),
MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23,
CLK_DOMAIN_SCPSYS),
MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31),
MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15),
MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23),
MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31),
MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7),
MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15),
MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23),
MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31),
MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7),
MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15),
MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23),
MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31),
MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7),
MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15),
MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7),
MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15),
MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31),
MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7),
MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15),
MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23),
MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31),
MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7),
MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15),
MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23),
MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31),
MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7),
MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23),
MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31,
CLK_DOMAIN_SCPSYS),
MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7),
MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15),
MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23),
MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31),
MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7),
MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15),
MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23),
MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3),
MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3),
MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3),
MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23),
MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24),
MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25),
MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26),
MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27),
MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28),
};
/* infracfg */
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x40,
.clr_ofs = 0x44,
.sta_ofs = 0x48,
};
#define GATE_INFRA(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &infra_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
}
static const struct mtk_gate infra_cgs[] = {
GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1),
GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4),
GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5),
GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6),
GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7),
GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12),
GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13),
GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14),
GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15),
GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16),
GATE_INFRA(CLK_INFRA_CEC, CLK_TOP_RTC_SEL, 18),
GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19),
GATE_INFRA(CLK_INFRA_PMICSPI, CLK_TOP_PMICSPI_SEL, 22),
GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23),
GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24),
};
/* pericfg */
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x10,
.sta_ofs = 0x18,
};
static const struct mtk_gate_regs peri1_cg_regs = {
.set_ofs = 0xC,
.clr_ofs = 0x14,
.sta_ofs = 0x1C,
};
#define GATE_PERI0(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &peri0_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
}
#define GATE_PERI1(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &peri1_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
}
static const struct mtk_gate peri_cgs[] = {
GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0),
GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2),
GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3),
GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4),
GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5),
GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6),
GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7),
GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9),
GATE_PERI0(CLK_PERI_USB0, CLK_TOP_USB20_SEL, 10),
GATE_PERI0(CLK_PERI_USB1, CLK_TOP_USB20_SEL, 11),
GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12),
GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13),
GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14),
GATE_PERI0(CLK_PERI_MSDC30_2, CLK_TOP_MSDC30_2_SEL, 15),
GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16),
GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17),
GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18),
GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19),
GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20),
GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21),
GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22),
GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23),
GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27),
GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28),
GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30),
GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
GATE_PERI1(CLK_PERI_USB_SLV, CLK_TOP_AXI_SEL, 1),
GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2),
GATE_PERI1(CLK_PERI_NFI_ECC, CLK_TOP_NFI1X_PAD, 3),
GATE_PERI1(CLK_PERI_NFI_PAD, CLK_TOP_NFI1X_PAD, 4),
GATE_PERI1(CLK_PERI_FLASH, CLK_TOP_NFI2X_SEL, 5),
GATE_PERI1(CLK_PERI_HOST89_INT, CLK_TOP_AXI_SEL, 6),
GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7),
GATE_PERI1(CLK_PERI_HOST89_DVD, CLK_TOP_AUD2DVD_SEL, 8),
GATE_PERI1(CLK_PERI_SPI1, CLK_TOP_SPI1_SEL, 9),
GATE_PERI1(CLK_PERI_SPI2, CLK_TOP_SPI2_SEL, 10),
GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11),
};
/* ethsys and hifsys */
static const struct mtk_gate_regs eth_hif_cg_regs = {
.sta_ofs = 0x30,
};
#define GATE_ETH_HIF(_id, _parent, _shift, _flag) { \
.id = _id, \
.parent = _parent, \
.regs = &eth_hif_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_NO_SETCLR_INV | (_flag), \
}
#define GATE_ETH_HIF0(_id, _parent, _shift) \
GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_APMIXED)
#define GATE_ETH_HIF1(_id, _parent, _shift) \
GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
static const struct mtk_gate eth_cgs[] = {
GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
GATE_ETH_HIF0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
};
static const struct mtk_gate hif_cgs[] = {
GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21),
GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22),
GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),
GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25),
GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
};
static const struct mtk_clk_tree mt7623_clk_tree = {
.xtal_rate = 26 * MHZ,
.xtal2_rate = 26 * MHZ,
.fdivs_offs = CLK_TOP_SYSPLL,
.muxes_offs = CLK_TOP_AXI_SEL,
.plls = apmixed_plls,
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
};
static int mt7623_mcucfg_probe(struct udevice *dev)
{
void __iomem *base;
base = dev_read_addr_ptr(dev);
if (!base)
return -ENOENT;
clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
AXI_DIV_SEL(0x12));
return 0;
}
static int mt7623_apmixedsys_probe(struct udevice *dev)
{
struct mtk_clk_priv *priv = dev_get_priv(dev);
int ret;
ret = mtk_common_clk_init(dev, &mt7623_clk_tree);
if (ret)
return ret;
/* reduce clock square disable time */
writel(0x50001, priv->base + MT7623_CLKSQ_STB_CON0);
/* extend control timing to 1us */
writel(0x888, priv->base + MT7623_PLL_ISO_CON0);
return 0;
}
static int mt7623_topckgen_probe(struct udevice *dev)
{
return mtk_common_clk_init(dev, &mt7623_clk_tree);
}
static int mt7623_infracfg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs);
}
static int mt7623_pericfg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
}
static int mt7623_hifsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs);
}
static int mt7623_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
}
static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
{
int ret = 0;
#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
if (ret)
debug("Warning: failed to bind reset controller\n");
#endif
return ret;
}
static const struct udevice_id mt7623_apmixed_compat[] = {
{ .compatible = "mediatek,mt7623-apmixedsys" },
{ }
};
static const struct udevice_id mt7623_topckgen_compat[] = {
{ .compatible = "mediatek,mt7623-topckgen" },
{ }
};
static const struct udevice_id mt7623_infracfg_compat[] = {
{ .compatible = "mediatek,mt7623-infracfg", },
{ }
};
static const struct udevice_id mt7623_pericfg_compat[] = {
{ .compatible = "mediatek,mt7623-pericfg", },
{ }
};
static const struct udevice_id mt7623_ethsys_compat[] = {
{ .compatible = "mediatek,mt7623-ethsys" },
{ }
};
static const struct udevice_id mt7623_hifsys_compat[] = {
{ .compatible = "mediatek,mt7623-hifsys" },
{ }
};
static const struct udevice_id mt7623_mcucfg_compat[] = {
{ .compatible = "mediatek,mt7623-mcucfg" },
{ }
};
U_BOOT_DRIVER(mtk_mcucfg) = {
.name = "mt7623-mcucfg",
.id = UCLASS_SYSCON,
.of_match = mt7623_mcucfg_compat,
.probe = mt7623_mcucfg_probe,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
.name = "mt7623-clock-apmixedsys",
.id = UCLASS_CLK,
.of_match = mt7623_apmixed_compat,
.probe = mt7623_apmixedsys_probe,
.priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_topckgen) = {
.name = "mt7623-clock-topckgen",
.id = UCLASS_CLK,
.of_match = mt7623_topckgen_compat,
.probe = mt7623_topckgen_probe,
.priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_infracfg) = {
.name = "mt7623-infracfg",
.id = UCLASS_CLK,
.of_match = mt7623_infracfg_compat,
.probe = mt7623_infracfg_probe,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_pericfg) = {
.name = "mt7623-pericfg",
.id = UCLASS_CLK,
.of_match = mt7623_pericfg_compat,
.probe = mt7623_pericfg_probe,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_hifsys) = {
.name = "mt7623-clock-hifsys",
.id = UCLASS_CLK,
.of_match = mt7623_hifsys_compat,
.probe = mt7623_hifsys_probe,
.bind = mt7623_ethsys_hifsys_bind,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
U_BOOT_DRIVER(mtk_clk_ethsys) = {
.name = "mt7623-clock-ethsys",
.id = UCLASS_CLK,
.of_match = mt7623_ethsys_compat,
.probe = mt7623_ethsys_probe,
.bind = mt7623_ethsys_hifsys_bind,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
source/bootloader/u-boot-2020.01/drivers/clk/mediatek/clk-mt7629.c
+724
View File
@@ -0,0 +1,724 @@
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek clock driver for MT7629 SoC
*
* Copyright (C) 2018 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com>
*/
#include <common.h>
#include <dm.h>
#include <asm/arch-mediatek/reset.h>
#include <asm/io.h>
#include <dt-bindings/clock/mt7629-clk.h>
#include "clk-mtk.h"
#define MT7629_CLKSQ_STB_CON0 0x20
#define MT7629_PLL_ISO_CON0 0x2c
#define MT7629_PLL_FMAX (2500UL * MHZ)
#define MT7629_CON0_RST_BAR BIT(24)
#define MCU_AXI_DIV 0x640
#define AXI_DIV_MSK GENMASK(4, 0)
#define AXI_DIV_SEL(x) (x)
#define MCU_BUS_MUX 0x7c0
#define MCU_BUS_MSK GENMASK(10, 9)
#define MCU_BUS_SEL(x) ((x) << 9)
/* apmixedsys */
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _pcw_reg, _pcw_shift) { \
.id = _id, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.rst_bar_mask = MT7629_CON0_RST_BAR, \
.fmax = MT7629_PLL_FMAX, \
.flags = _flags, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
}
static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
21, 0x204, 24, 0x204, 0),
PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
21, 0x214, 24, 0x214, 0),
PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
7, 0x224, 24, 0x224, 14),
PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
21, 0x300, 1, 0x304, 0),
PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
21, 0x314, 1, 0x318, 0),
PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
21, 0x358, 1, 0x35c, 0),
};
/* topckgen */
#define FACTOR0(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
#define FACTOR1(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
#define FACTOR2(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, 0)
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
};
static const struct mtk_fixed_factor top_fixed_divs[] = {
FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1),
FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1),
FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1),
FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4),
FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8),
FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4),
FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1),
FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1),
FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1),
FACTOR1(CLK_TOP_AP2WBHIF_HCLK, CLK_TOP_SYSPLL1_D8, 1, 1),
FACTOR1(CLK_TOP_10M_INFRAO, CLK_TOP_10M_SEL, 1, 1),
FACTOR1(CLK_TOP_MSDC30_1, CLK_TOP_MSDC30_1, 1, 1),
FACTOR1(CLK_TOP_SPI, CLK_TOP_SPI0_SEL, 1, 1),
FACTOR1(CLK_TOP_SF, CLK_TOP_NFI_INFRA_SEL, 1, 1),
FACTOR1(CLK_TOP_FLASH, CLK_TOP_FLASH_SEL, 1, 1),
FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_SATA_SEL, 1, 4),
FACTOR1(CLK_TOP_TO_USB3_MCU, CLK_TOP_AXI_SEL, 1, 1),
FACTOR1(CLK_TOP_TO_USB3_DMA, CLK_TOP_HIF_SEL, 1, 1),
FACTOR1(CLK_TOP_FROM_TOP_AHB, CLK_TOP_AXI_SEL, 1, 1),
FACTOR1(CLK_TOP_FROM_TOP_AXI, CLK_TOP_HIF_SEL, 1, 1),
FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
};
static const int axi_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_SYSPLL_D5,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_UNIVPLL_D5,
CLK_TOP_UNIVPLL2_D2,
CLK_TOP_UNIVPLL_D7,
CLK_TOP_DMPLL
};
static const int mem_parents[] = {
CLK_XTAL,
CLK_TOP_DMPLL
};
static const int ddrphycfg_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D8
};
static const int eth_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_UNIVPLL1_D2,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_UNIVPLL_D5,
CLK_TOP_SGMIIPLL_D2,
CLK_TOP_UNIVPLL_D7,
CLK_TOP_DMPLL
};
static const int pwm_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL2_D4
};
static const int f10m_ref_parents[] = {
CLK_XTAL,
CLK_TOP_SGMIIPLL_D2
};
static const int nfi_infra_parents[] = {
CLK_XTAL,
CLK_XTAL,
CLK_XTAL,
CLK_XTAL,
CLK_XTAL,
CLK_XTAL,
CLK_TOP_UNIVPLL2_D8,
CLK_TOP_UNIVPLL3_D4,
CLK_TOP_SYSPLL1_D8,
CLK_TOP_UNIVPLL1_D8,
CLK_TOP_SYSPLL4_D2,
CLK_TOP_SYSPLL2_D4,
CLK_TOP_UNIVPLL2_D4,
CLK_TOP_UNIVPLL3_D2,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_SYSPLL_D7
};
static const int flash_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL_D80_D4,
CLK_TOP_SYSPLL2_D8,
CLK_TOP_SYSPLL3_D4,
CLK_TOP_UNIVPLL3_D4,
CLK_TOP_UNIVPLL1_D8,
CLK_TOP_SYSPLL2_D4,
CLK_TOP_UNIVPLL2_D4
};
static const int uart_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL2_D8
};
static const int spi0_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL3_D2,
CLK_XTAL,
CLK_TOP_SYSPLL2_D4,
CLK_TOP_SYSPLL4_D2,
CLK_TOP_UNIVPLL2_D4,
CLK_TOP_UNIVPLL1_D8,
CLK_XTAL
};
static const int spi1_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL3_D2,
CLK_XTAL,
CLK_TOP_SYSPLL4_D4,
CLK_TOP_SYSPLL4_D2,
CLK_TOP_UNIVPLL2_D4,
CLK_TOP_UNIVPLL1_D8,
CLK_XTAL
};
static const int msdc30_0_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL2_D16,
CLK_TOP_UNIV48M
};
static const int msdc30_1_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL2_D16,
CLK_TOP_UNIV48M,
CLK_TOP_SYSPLL2_D4,
CLK_TOP_UNIVPLL2_D4,
CLK_TOP_SYSPLL_D7,
CLK_TOP_SYSPLL2_D2,
CLK_TOP_UNIVPLL2_D2
};
static const int ap2wbmcu_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_UNIV48M,
CLK_TOP_SYSPLL1_D8,
CLK_TOP_UNIVPLL2_D4,
CLK_TOP_SYSPLL_D7,
CLK_TOP_SYSPLL2_D2,
CLK_TOP_UNIVPLL2_D2
};
static const int audio_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL3_D4,
CLK_TOP_SYSPLL4_D4,
CLK_TOP_SYSPLL1_D16
};
static const int aud_intbus_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_SYSPLL4_D2,
CLK_TOP_DMPLL_D4
};
static const int pmicspi_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D8,
CLK_TOP_SYSPLL3_D4,
CLK_TOP_SYSPLL1_D16,
CLK_TOP_UNIVPLL3_D4,
CLK_XTAL,
CLK_TOP_UNIVPLL2_D4,
CLK_TOP_DMPLL_D8
};
static const int scp_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D8,
CLK_TOP_UNIVPLL2_D2,
CLK_TOP_UNIVPLL2_D4
};
static const int atb_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_SYSPLL_D5
};
static const int hif_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_UNIVPLL1_D2,
CLK_TOP_SYSPLL1_D4,
CLK_TOP_UNIVPLL_D5,
-1,
CLK_TOP_UNIVPLL_D7
};
static const int sata_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL2_D4
};
static const int usb20_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL3_D4,
CLK_TOP_SYSPLL1_D8
};
static const int aud1_parents[] = {
CLK_XTAL
};
static const int irrx_parents[] = {
CLK_XTAL,
CLK_TOP_SYSPLL4_D16
};
static const int crypto_parents[] = {
CLK_XTAL,
CLK_TOP_UNIVPLL_D3,
CLK_TOP_UNIVPLL1_D2,
CLK_TOP_SYSPLL1_D2,
CLK_TOP_UNIVPLL_D5,
CLK_TOP_SYSPLL_D5,
CLK_TOP_UNIVPLL2_D2,
CLK_TOP_SYSPLL_D2
};
static const int gpt10m_parents[] = {
CLK_XTAL,
CLK_TOP_CLKXTAL_D4
};
static const struct mtk_composite top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
/* CLK_CFG_1 */
MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
/* CLK_CFG_2 */
MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
/* CLK_CFG_3 */
MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15),
MUX_GATE(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23),
MUX_GATE(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31),
/* CLK_CFG_4 */
MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7),
MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31),
/* CLK_CFG_5 */
MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15,
CLK_DOMAIN_SCPSYS),
MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23),
MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
/* CLK_CFG_6 */
MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23),
MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31),
/* CLK_CFG_7 */
MUX_GATE(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7),
MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15),
MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23),
MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31),
/* CLK_CFG_8 */
MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7),
MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15),
MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23),
};
/* infracfg */
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x40,
.clr_ofs = 0x44,
.sta_ofs = 0x48,
};
#define GATE_INFRA(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &infra_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
}
static const struct mtk_gate infra_cgs[] = {
GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_HD_FAXI, 0),
GATE_INFRA(CLK_INFRA_TRNG_PD, CLK_TOP_HD_FAXI, 2),
GATE_INFRA(CLK_INFRA_DEVAPC_PD, CLK_TOP_HD_FAXI, 4),
GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_10M_INFRAO, 18),
GATE_INFRA(CLK_INFRA_SEJ_PD, CLK_TOP_10M_INFRAO, 19),
};
/* pericfg */
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x10,
.sta_ofs = 0x18,
};
static const struct mtk_gate_regs peri1_cg_regs = {
.set_ofs = 0xC,
.clr_ofs = 0x14,
.sta_ofs = 0x1C,
};
#define GATE_PERI0(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &peri0_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
}
#define GATE_PERI1(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &peri1_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
}
static const struct mtk_gate peri_cgs[] = {
GATE_PERI0(CLK_PERI_PWM1_PD, CLK_TOP_PWM_QTR_26M, 2),
GATE_PERI0(CLK_PERI_PWM2_PD, CLK_TOP_PWM_QTR_26M, 3),
GATE_PERI0(CLK_PERI_PWM3_PD, CLK_TOP_PWM_QTR_26M, 4),
GATE_PERI0(CLK_PERI_PWM4_PD, CLK_TOP_PWM_QTR_26M, 5),
GATE_PERI0(CLK_PERI_PWM5_PD, CLK_TOP_PWM_QTR_26M, 6),
GATE_PERI0(CLK_PERI_PWM6_PD, CLK_TOP_PWM_QTR_26M, 7),
GATE_PERI0(CLK_PERI_PWM7_PD, CLK_TOP_PWM_QTR_26M, 8),
GATE_PERI0(CLK_PERI_PWM_PD, CLK_TOP_PWM_QTR_26M, 9),
GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_FAXI, 12),
GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1, 14),
GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_FAXI, 17),
GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_FAXI, 18),
GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_FAXI, 19),
GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_FAXI, 20),
GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_FAXI, 22),
GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_FAXI, 23),
GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI, 28),
GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_SF, 29),
GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_FAXI, 30),
GATE_PERI0(CLK_PERI_NFIECC_PD, CLK_TOP_FAXI, 31),
GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH, 1),
};
/* ethsys */
static const struct mtk_gate_regs eth_cg_regs = {
.sta_ofs = 0x30,
};
#define GATE_ETH(_id, _parent, _shift, _flag) { \
.id = _id, \
.parent = _parent, \
.regs = &eth_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_NO_SETCLR_INV | (_flag), \
}
#define GATE_ETH0(_id, _parent, _shift) \
GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED)
#define GATE_ETH1(_id, _parent, _shift) \
GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
static const struct mtk_gate eth_cgs[] = {
GATE_ETH0(CLK_ETH_FE_EN, CLK_APMIXED_ETH2PLL, 6),
GATE_ETH1(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
GATE_ETH1(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
GATE_ETH1(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
GATE_ETH1(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 16),
};
static const struct mtk_gate_regs sgmii_cg_regs = {
.set_ofs = 0xE4,
.clr_ofs = 0xE4,
.sta_ofs = 0xE4,
};
#define GATE_SGMII(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &sgmii_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
}
static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_TX_EN, CLK_TOP_SSUSB_TX250M, 2),
GATE_SGMII(CLK_SGMII_RX_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
};
static const struct mtk_clk_tree mt7629_clk_tree = {
.xtal_rate = 40 * MHZ,
.xtal2_rate = 20 * MHZ,
.fdivs_offs = CLK_TOP_TO_USB3_SYS,
.muxes_offs = CLK_TOP_AXI_SEL,
.plls = apmixed_plls,
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
};
static int mt7629_mcucfg_probe(struct udevice *dev)
{
void __iomem *base;
base = dev_read_addr_ptr(dev);
if (!base)
return -ENOENT;
clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
AXI_DIV_SEL(0x12));
clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
MCU_BUS_SEL(0x1));
return 0;
}
static int mt7629_apmixedsys_probe(struct udevice *dev)
{
struct mtk_clk_priv *priv = dev_get_priv(dev);
int ret;
ret = mtk_common_clk_init(dev, &mt7629_clk_tree);
if (ret)
return ret;
/* reduce clock square disable time */
writel(0x501, priv->base + MT7629_CLKSQ_STB_CON0);
/* extend pwr/iso control timing to 1us */
writel(0x80008, priv->base + MT7629_PLL_ISO_CON0);
return 0;
}
static int mt7629_topckgen_probe(struct udevice *dev)
{
return mtk_common_clk_init(dev, &mt7629_clk_tree);
}
static int mt7629_infracfg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs);
}
static int mt7629_pericfg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs);
}
static int mt7629_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs);
}
static int mt7629_ethsys_bind(struct udevice *dev)
{
int ret = 0;
#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
if (ret)
debug("Warning: failed to bind reset controller\n");
#endif
return ret;
}
static int mt7629_sgmiisys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs);
}
static const struct udevice_id mt7629_apmixed_compat[] = {
{ .compatible = "mediatek,mt7629-apmixedsys" },
{ }
};
static const struct udevice_id mt7629_topckgen_compat[] = {
{ .compatible = "mediatek,mt7629-topckgen" },
{ }
};
static const struct udevice_id mt7629_infracfg_compat[] = {
{ .compatible = "mediatek,mt7629-infracfg", },
{ }
};
static const struct udevice_id mt7629_pericfg_compat[] = {
{ .compatible = "mediatek,mt7629-pericfg", },
{ }
};
static const struct udevice_id mt7629_ethsys_compat[] = {
{ .compatible = "mediatek,mt7629-ethsys", },
{ }
};
static const struct udevice_id mt7629_sgmiisys_compat[] = {
{ .compatible = "mediatek,mt7629-sgmiisys", },
{ }
};
static const struct udevice_id mt7629_mcucfg_compat[] = {
{ .compatible = "mediatek,mt7629-mcucfg" },
{ }
};
U_BOOT_DRIVER(mtk_mcucfg) = {
.name = "mt7629-mcucfg",
.id = UCLASS_SYSCON,
.of_match = mt7629_mcucfg_compat,
.probe = mt7629_mcucfg_probe,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
.name = "mt7629-clock-apmixedsys",
.id = UCLASS_CLK,
.of_match = mt7629_apmixed_compat,
.probe = mt7629_apmixedsys_probe,
.priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_topckgen) = {
.name = "mt7629-clock-topckgen",
.id = UCLASS_CLK,
.of_match = mt7629_topckgen_compat,
.probe = mt7629_topckgen_probe,
.priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_infracfg) = {
.name = "mt7629-clock-infracfg",
.id = UCLASS_CLK,
.of_match = mt7629_infracfg_compat,
.probe = mt7629_infracfg_probe,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_pericfg) = {
.name = "mt7629-clock-pericfg",
.id = UCLASS_CLK,
.of_match = mt7629_pericfg_compat,
.probe = mt7629_pericfg_probe,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_ethsys) = {
.name = "mt7629-clock-ethsys",
.id = UCLASS_CLK,
.of_match = mt7629_ethsys_compat,
.probe = mt7629_ethsys_probe,
.bind = mt7629_ethsys_bind,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
.name = "mt7629-clock-sgmiisys",
.id = UCLASS_CLK,
.of_match = mt7629_sgmiisys_compat,
.probe = mt7629_sgmiisys_probe,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
source/bootloader/u-boot-2020.01/drivers/clk/mediatek/clk-mt8516.c
+802
View File
@@ -0,0 +1,802 @@
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek clock driver for MT8516 SoC
*
* Copyright (C) 2018 BayLibre, SAS
* Author: Fabien Parent <fparent@baylibre.com>
*/
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <dt-bindings/clock/mt8516-clk.h>
#include "clk-mtk.h"
#define MT8516_PLL_FMAX (1502UL * MHZ)
#define MT8516_CON0_RST_BAR BIT(27)
/* apmixedsys */
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _pcw_reg, _pcw_shift) { \
.id = _id, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.rst_bar_mask = MT8516_CON0_RST_BAR, \
.fmax = MT8516_PLL_FMAX, \
.flags = _flags, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
}
static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
21, 0x0104, 24, 0x0104, 0),
PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
21, 0x0164, 24, 0x0164, 0),
PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
31, 0x0180, 1, 0x0184, 0),
PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 0,
31, 0x01A0, 1, 0x01A4, 0),
};
/* topckgen */
#define FACTOR0(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
#define FACTOR1(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
#define FACTOR2(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, 0)
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),
FIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),
};
static const struct mtk_fixed_factor top_fixed_divs[] = {
FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
FACTOR0(CLK_TOP_MAINPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
FACTOR0(CLK_TOP_MMPLL380M, CLK_APMIXED_MMPLL, 1, 1),
FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
FACTOR0(CLK_TOP_MMPLL_200M, CLK_APMIXED_MMPLL, 1, 3),
FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
FACTOR1(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2),
FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_RG_APLL1_D2_EN, 1, 2),
FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2),
FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2),
FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2),
FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2),
FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
};
static const int uart0_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D24,
};
static const int gfmux_emi1x_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_DMPLL,
};
static const int emi_ddrphy_parents[] = {
CLK_TOP_GFMUX_EMI1X_SEL,
CLK_TOP_GFMUX_EMI1X_SEL,
};
static const int ahb_infra_parents[] = {
CLK_TOP_CLK_NULL,
CLK_TOP_CLK26M,
CLK_TOP_MAINPLL_D11,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D12,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D10,
};
static const int csw_mux_mfg_parents[] = {
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_UNIVPLL_D3,
CLK_TOP_UNIVPLL_D2,
CLK_TOP_CLK26M,
CLK_TOP_MAINPLL_D4,
CLK_TOP_UNIVPLL_D24,
CLK_TOP_MMPLL380M,
};
static const int msdc0_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D6,
CLK_TOP_MAINPLL_D8,
CLK_TOP_UNIVPLL_D8,
CLK_TOP_MAINPLL_D16,
CLK_TOP_MMPLL_200M,
CLK_TOP_MAINPLL_D12,
CLK_TOP_MMPLL_D2,
};
static const int pwm_mm_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D12,
};
static const int uart1_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D24,
};
static const int msdc1_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D6,
CLK_TOP_MAINPLL_D8,
CLK_TOP_UNIVPLL_D8,
CLK_TOP_MAINPLL_D16,
CLK_TOP_MMPLL_200M,
CLK_TOP_MAINPLL_D12,
CLK_TOP_MMPLL_D2,
};
static const int spm_52m_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D24,
};
static const int pmicspi_parents[] = {
CLK_TOP_UNIVPLL_D20,
CLK_TOP_USB_PHY48M,
CLK_TOP_UNIVPLL_D16,
CLK_TOP_CLK26M,
};
static const int qaxi_aud26m_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_AHB_INFRA_SEL,
};
static const int aud_intbus_parents[] = {
CLK_TOP_CLK_NULL,
CLK_TOP_CLK26M,
CLK_TOP_MAINPLL_D22,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D11,
};
static const int nfi2x_pad_parents[] = {
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK26M,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D12,
CLK_TOP_MAINPLL_D8,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D6,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D4,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D10,
CLK_TOP_MAINPLL_D7,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D5
};
static const int nfi1x_pad_parents[] = {
CLK_TOP_AHB_INFRA_SEL,
CLK_TOP_NFI1X,
};
static const int mfg_mm_parents[] = {
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CSW_MUX_MFG_SEL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D3,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D5,
CLK_TOP_MAINPLL_D7,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D14
};
static const int ddrphycfg_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_MAINPLL_D16
};
static const int usb_78m_parents[] = {
CLK_TOP_CLK_NULL,
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D16,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D20,
};
static const int spinor_parents[] = {
CLK_TOP_CLK26M_D2,
CLK_TOP_CLK26M,
CLK_TOP_MAINPLL_D40,
CLK_TOP_UNIVPLL_D24,
CLK_TOP_UNIVPLL_D20,
CLK_TOP_MAINPLL_D20,
CLK_TOP_MAINPLL_D16,
CLK_TOP_UNIVPLL_D12
};
static const int msdc2_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D6,
CLK_TOP_MAINPLL_D8,
CLK_TOP_UNIVPLL_D8,
CLK_TOP_MAINPLL_D16,
CLK_TOP_MMPLL_200M,
CLK_TOP_MAINPLL_D12,
CLK_TOP_MMPLL_D2
};
static const int eth_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_MAINPLL_D40,
CLK_TOP_UNIVPLL_D24,
CLK_TOP_UNIVPLL_D20,
CLK_TOP_MAINPLL_D20
};
static const int axi_mfg_in_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_MAINPLL_D11,
CLK_TOP_UNIVPLL_D24,
CLK_TOP_MMPLL380M,
};
static const int slow_mfg_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D12,
CLK_TOP_UNIVPLL_D24
};
static const int aud1_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_APLL1
};
static const int aud2_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_APLL2
};
static const int aud_engen1_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_RG_APLL1_D2_EN,
CLK_TOP_RG_APLL1_D4_EN,
CLK_TOP_RG_APLL1_D8_EN
};
static const int aud_engen2_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_RG_APLL2_D2_EN,
CLK_TOP_RG_APLL2_D4_EN,
CLK_TOP_RG_APLL2_D8_EN
};
static const int i2c_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D20,
CLK_TOP_UNIVPLL_D16,
CLK_TOP_UNIVPLL_D12
};
static const int aud_i2s0_m_parents[] = {
CLK_TOP_RG_AUD1,
CLK_TOP_RG_AUD2
};
static const int pwm_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D12
};
static const int spi_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D12,
CLK_TOP_UNIVPLL_D8,
CLK_TOP_UNIVPLL_D6
};
static const int aud_spdifin_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D2
};
static const int uart2_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_UNIVPLL_D24
};
static const int bsi_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_MAINPLL_D10,
CLK_TOP_MAINPLL_D12,
CLK_TOP_MAINPLL_D20
};
static const int dbg_atclk_parents[] = {
CLK_TOP_CLK_NULL,
CLK_TOP_CLK26M,
CLK_TOP_MAINPLL_D5,
CLK_TOP_CLK_NULL,
CLK_TOP_UNIVPLL_D5
};
static const int csw_nfiecc_parents[] = {
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D7,
CLK_TOP_MAINPLL_D6,
CLK_TOP_CLK_NULL,
CLK_TOP_MAINPLL_D5
};
static const int nfiecc_parents[] = {
CLK_TOP_CLK_NULL,
CLK_TOP_NFI2X_PAD_SEL,
CLK_TOP_MAINPLL_D4,
CLK_TOP_CLK_NULL,
CLK_TOP_CSW_NFIECC_SEL,
};
static const struct mtk_composite top_muxes[] = {
/* CLK_MUX_SEL0 */
MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1),
MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4),
MUX(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3),
MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1),
MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3),
MUX(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1),
MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),
MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1),
MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),
/* CLK_MUX_SEL1 */
MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7),
MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1),
MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6),
MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3),
/* CLK_MUX_SEL8 */
MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
MUX(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2),
MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2),
MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
/* CLK_MUX_SEL9 */
MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1),
MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1),
MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1),
MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
/* CLK_MUX_SEL13 */
MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1),
MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2),
MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3),
MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3),
};
static const struct mtk_gate_regs top0_cg_regs = {
.set_ofs = 0x50,
.clr_ofs = 0x80,
.sta_ofs = 0x20,
};
static const struct mtk_gate_regs top1_cg_regs = {
.set_ofs = 0x54,
.clr_ofs = 0x84,
.sta_ofs = 0x24,
};
static const struct mtk_gate_regs top2_cg_regs = {
.set_ofs = 0x6c,
.clr_ofs = 0x9c,
.sta_ofs = 0x3c,
};
static const struct mtk_gate_regs top3_cg_regs = {
.set_ofs = 0xa0,
.clr_ofs = 0xb0,
.sta_ofs = 0x70,
};
static const struct mtk_gate_regs top4_cg_regs = {
.set_ofs = 0xa4,
.clr_ofs = 0xb4,
.sta_ofs = 0x74,
};
static const struct mtk_gate_regs top5_cg_regs = {
.set_ofs = 0x44,
.clr_ofs = 0x44,
.sta_ofs = 0x44,
};
#define GATE_TOP0(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &top0_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
}
#define GATE_TOP1(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &top1_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
}
#define GATE_TOP2(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &top2_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
}
#define GATE_TOP2_I(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &top2_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
}
#define GATE_TOP3(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &top3_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
}
#define GATE_TOP4_I(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &top4_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
}
#define GATE_TOP5(_id, _parent, _shift) { \
.id = _id, \
.parent = _parent, \
.regs = &top5_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
}
static const struct mtk_gate top_clks[] = {
/* TOP0 */
GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
GATE_TOP0(CLK_TOP_MFG_MM, CLK_TOP_MFG_MM_SEL, 2),
GATE_TOP0(CLK_TOP_SPM_52M, CLK_TOP_SPM_52M_SEL, 3),
/* TOP1 */
GATE_TOP1(CLK_TOP_THEM, CLK_TOP_AHB_INFRA_SEL, 1),
GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AHB_INFRA_SEL, 2),
GATE_TOP1(CLK_TOP_I2C0, CLK_IFR_I2C0_SEL, 3),
GATE_TOP1(CLK_TOP_I2C1, CLK_IFR_I2C1_SEL, 4),
GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_AHB_INFRA_SEL, 5),
GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_PAD_SEL, 6),
GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_RG_NFIECC, 7),
GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_RG_DBG_ATCLK, 8),
GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AHB_INFRA_SEL, 9),
GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
GATE_TOP1(CLK_TOP_BTIF, CLK_TOP_AHB_INFRA_SEL, 12),
GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_78M, 13),
GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_AHB_INFRA_SEL, 15),
GATE_TOP1(CLK_TOP_I2C2, CLK_IFR_I2C2_SEL, 16),
GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_PAD_SEL, 19),
GATE_TOP1(CLK_TOP_PMICWRAP_AP, CLK_TOP_CLK26M, 20),
GATE_TOP1(CLK_TOP_SEJ, CLK_TOP_AHB_INFRA_SEL, 21),
GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI_SEL, 23),
GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
GATE_TOP1(CLK_TOP_AUDIO, CLK_TOP_CLK26M, 25),
GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_CLK26M, 28),
GATE_TOP1(CLK_TOP_PMICWRAP_26M, CLK_TOP_CLK26M, 29),
GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
/* TOP2 */
GATE_TOP2(CLK_TOP_MSDC2, CLK_TOP_AHB_INFRA_SEL, 0),
GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AHB_INFRA_SEL, 2),
GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AHB_INFRA_SEL, 4),
GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AHB_INFRA_SEL, 5),
GATE_TOP2(CLK_TOP_SEJ_13M, CLK_TOP_CLK26M, 6),
GATE_TOP2(CLK_TOP_AES, CLK_TOP_AHB_INFRA_SEL, 7),
GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_RG_PWM_INFRA, 8),
GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_RG_PWM_INFRA, 9),
GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_RG_PWM_INFRA, 10),
GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_RG_PWM_INFRA, 11),
GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_RG_PWM_INFRA, 12),
GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_RG_PWM_INFRA, 13),
GATE_TOP2(CLK_TOP_USB_1P, CLK_TOP_USB_78M, 14),
GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AHB_INFRA_SEL, 15),
GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AHB_INFRA_D2, 19),
GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AHB_INFRA_SEL, 20),
GATE_TOP2(CLK_TOP_FETH_25M, CLK_IFR_ETH_25M_SEL, 21),
GATE_TOP2(CLK_TOP_FETH_50M, CLK_TOP_RG_ETH, 22),
GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_AHB_INFRA_SEL, 23),
GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AHB_INFRA_SEL, 24),
GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
GATE_TOP2(CLK_TOP_BSI, CLK_TOP_AHB_INFRA_SEL, 26),
GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, CLK_TOP_MSDC0, 28),
GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, CLK_TOP_MSDC1, 29),
GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, CLK_TOP_RG_MSDC2, 30),
GATE_TOP2(CLK_TOP_USB_78M, CLK_TOP_USB_78M_SEL, 31),
/* TOP3 */
GATE_TOP3(CLK_TOP_RG_SPINOR, CLK_TOP_SPINOR_SEL, 0),
GATE_TOP3(CLK_TOP_RG_MSDC2, CLK_TOP_MSDC2_SEL, 1),
GATE_TOP3(CLK_TOP_RG_ETH, CLK_TOP_ETH_SEL, 2),
GATE_TOP3(CLK_TOP_RG_AXI_MFG, CLK_TOP_AXI_MFG_IN_SEL, 6),
GATE_TOP3(CLK_TOP_RG_SLOW_MFG, CLK_TOP_SLOW_MFG_SEL, 7),
GATE_TOP3(CLK_TOP_RG_AUD1, CLK_TOP_AUD1_SEL, 8),
GATE_TOP3(CLK_TOP_RG_AUD2, CLK_TOP_AUD2_SEL, 9),
GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, CLK_TOP_AUD_ENGEN1_SEL, 10),
GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, CLK_TOP_AUD_ENGEN2_SEL, 11),
GATE_TOP3(CLK_TOP_RG_I2C, CLK_TOP_I2C_SEL, 12),
GATE_TOP3(CLK_TOP_RG_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
GATE_TOP3(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
GATE_TOP3(CLK_TOP_RG_BSI, CLK_TOP_BSI_SEL, 16),
GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, CLK_TOP_DBG_ATCLK_SEL, 17),
GATE_TOP3(CLK_TOP_RG_NFIECC, CLK_TOP_NFIECC_SEL, 18),
/* TOP4 */
GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, CLK_TOP_APLL1_D2, 8),
GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, CLK_TOP_APLL1_D4, 9),
GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, CLK_TOP_APLL1_D8, 10),
GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, CLK_TOP_APLL2_D2, 11),
GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, CLK_TOP_APLL2_D4, 12),
GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, CLK_TOP_APLL2_D8, 13),
/* TOP5 */
GATE_TOP5(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
GATE_TOP5(CLK_TOP_APLL12_DIV1, CLK_TOP_APLL12_CK_DIV1, 1),
GATE_TOP5(CLK_TOP_APLL12_DIV2, CLK_TOP_APLL12_CK_DIV2, 2),
GATE_TOP5(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
GATE_TOP5(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
GATE_TOP5(CLK_TOP_APLL12_DIV4B, CLK_TOP_APLL12_CK_DIV4B, 5),
GATE_TOP5(CLK_TOP_APLL12_DIV5, CLK_TOP_APLL12_CK_DIV5, 6),
GATE_TOP5(CLK_TOP_APLL12_DIV5B, CLK_TOP_APLL12_CK_DIV5B, 7),
GATE_TOP5(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
};
static const struct mtk_clk_tree mt8516_clk_tree = {
.xtal_rate = 26 * MHZ,
.xtal2_rate = 26 * MHZ,
.fdivs_offs = CLK_TOP_DMPLL,
.muxes_offs = CLK_TOP_UART0_SEL,
.plls = apmixed_plls,
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
};
static int mt8516_apmixedsys_probe(struct udevice *dev)
{
return mtk_common_clk_init(dev, &mt8516_clk_tree);
}
static int mt8516_topckgen_probe(struct udevice *dev)
{
return mtk_common_clk_init(dev, &mt8516_clk_tree);
}
static int mt8516_topckgen_cg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks);
}
static const struct udevice_id mt8516_apmixed_compat[] = {
{ .compatible = "mediatek,mt8516-apmixedsys", },
{ }
};
static const struct udevice_id mt8516_topckgen_compat[] = {
{ .compatible = "mediatek,mt8516-topckgen", },
{ }
};
static const struct udevice_id mt8516_topckgen_cg_compat[] = {
{ .compatible = "mediatek,mt8516-topckgen-cg", },
{ }
};
U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
.name = "mt8516-apmixedsys",
.id = UCLASS_CLK,
.of_match = mt8516_apmixed_compat,
.probe = mt8516_apmixedsys_probe,
.priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_topckgen) = {
.name = "mt8516-topckgen",
.id = UCLASS_CLK,
.of_match = mt8516_topckgen_compat,
.probe = mt8516_topckgen_probe,
.priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
.name = "mt8516-topckgen-cg",
.id = UCLASS_CLK,
.of_match = mt8516_topckgen_cg_compat,
.probe = mt8516_topckgen_cg_probe,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
source/bootloader/u-boot-2020.01/drivers/clk/mediatek/clk-mt8518.c
+1558
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source/bootloader/u-boot-2020.01/drivers/clk/mediatek/clk-mtk.c
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@@ -0,0 +1,505 @@
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek common clock driver
*
* Copyright (C) 2018 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com>
*/
#include <common.h>
#include <clk-uclass.h>
#include <div64.h>
#include <dm.h>
#include <asm/io.h>
#include "clk-mtk.h"
#define REG_CON0 0
#define REG_CON1 4
#define CON0_BASE_EN BIT(0)
#define CON0_PWR_ON BIT(0)
#define CON0_ISO_EN BIT(1)
#define CON1_PCW_CHG BIT(31)
#define POSTDIV_MASK 0x7
#define INTEGER_BITS 7
/* scpsys clock off control */
#define CLK_SCP_CFG0 0x200
#define CLK_SCP_CFG1 0x204
#define SCP_ARMCK_OFF_EN GENMASK(9, 0)
#define SCP_AXICK_DCM_DIS_EN BIT(0)
#define SCP_AXICK_26M_SEL_EN BIT(4)
/* shared functions */
/*
* In case the rate change propagation to parent clocks is undesirable,
* this function is recursively called to find the parent to calculate
* the accurate frequency.
*/
static int mtk_clk_find_parent_rate(struct clk *clk, int id,
const struct driver *drv)
{
struct clk parent = { .id = id, };
if (drv) {
struct udevice *dev;
if (uclass_get_device_by_driver(UCLASS_CLK, drv, &dev))
return -ENODEV;
parent.dev = dev;
} else {
parent.dev = clk->dev;
}
return clk_get_rate(&parent);
}
static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent,
const struct mtk_composite *mux)
{
u32 val, index = 0;
while (mux->parent[index] != parent)
if (++index == mux->num_parents)
return -EINVAL;
/* switch mux to a select parent */
val = readl(base + mux->mux_reg);
val &= ~(mux->mux_mask << mux->mux_shift);
val |= index << mux->mux_shift;
writel(val, base + mux->mux_reg);
return 0;
}
/* apmixedsys functions */
static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll,
u32 fin, u32 pcw, int postdiv)
{
int pcwbits = pll->pcwbits;
int pcwfbits;
u64 vco;
u8 c = 0;
/* The fractional part of the PLL divider. */
pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
vco = (u64)fin * pcw;
if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
c = 1;
vco >>= pcwfbits;
if (c)
vco++;
return ((unsigned long)vco + postdiv - 1) / postdiv;
}
/**
* MediaTek PLLs are configured through their pcw value. The pcw value
* describes a divider in the PLL feedback loop which consists of 7 bits
* for the integer part and the remaining bits (if present) for the
* fractional part. Also they have a 3 bit power-of-two post divider.
*/
static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
u32 val;
/* set postdiv */
val = readl(priv->base + pll->pd_reg);
val &= ~(POSTDIV_MASK << pll->pd_shift);
val |= (ffs(postdiv) - 1) << pll->pd_shift;
/* postdiv and pcw need to set at the same time if on same register */
if (pll->pd_reg != pll->pcw_reg) {
writel(val, priv->base + pll->pd_reg);
val = readl(priv->base + pll->pcw_reg);
}
/* set pcw */
val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
val |= pcw << pll->pcw_shift;
val &= ~CON1_PCW_CHG;
writel(val, priv->base + pll->pcw_reg);
val |= CON1_PCW_CHG;
writel(val, priv->base + pll->pcw_reg);
udelay(20);
}
/**
* mtk_pll_calc_values - calculate good values for a given input frequency.
* @clk: The clk
* @pcw: The pcw value (output)
* @postdiv: The post divider (output)
* @freq: The desired target frequency
*/
static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv,
u32 freq)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
unsigned long fmin = 1000 * MHZ;
u64 _pcw;
u32 val;
if (freq > pll->fmax)
freq = pll->fmax;
for (val = 0; val < 5; val++) {
*postdiv = 1 << val;
if ((u64)freq * *postdiv >= fmin)
break;
}
/* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
_pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS);
do_div(_pcw, priv->tree->xtal2_rate);
*pcw = (u32)_pcw;
}
static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)
{
u32 pcw = 0;
u32 postdiv;
mtk_pll_calc_values(clk, &pcw, &postdiv, rate);
mtk_pll_set_rate_regs(clk, pcw, postdiv);
return 0;
}
static ulong mtk_apmixedsys_get_rate(struct clk *clk)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
u32 postdiv;
u32 pcw;
postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) &
POSTDIV_MASK;
postdiv = 1 << postdiv;
pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift;
pcw &= GENMASK(pll->pcwbits - 1, 0);
return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate,
pcw, postdiv);
}
static int mtk_apmixedsys_enable(struct clk *clk)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
u32 r;
r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON;
writel(r, priv->base + pll->pwr_reg);
udelay(1);
r = readl(priv->base + pll->pwr_reg) & ~CON0_ISO_EN;
writel(r, priv->base + pll->pwr_reg);
udelay(1);
r = readl(priv->base + pll->reg + REG_CON0);
r |= pll->en_mask;
writel(r, priv->base + pll->reg + REG_CON0);
udelay(20);
if (pll->flags & HAVE_RST_BAR) {
r = readl(priv->base + pll->reg + REG_CON0);
r |= pll->rst_bar_mask;
writel(r, priv->base + pll->reg + REG_CON0);
}
return 0;
}
static int mtk_apmixedsys_disable(struct clk *clk)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
u32 r;
if (pll->flags & HAVE_RST_BAR) {
r = readl(priv->base + pll->reg + REG_CON0);
r &= ~pll->rst_bar_mask;
writel(r, priv->base + pll->reg + REG_CON0);
}
r = readl(priv->base + pll->reg + REG_CON0);
r &= ~CON0_BASE_EN;
writel(r, priv->base + pll->reg + REG_CON0);
r = readl(priv->base + pll->pwr_reg) | CON0_ISO_EN;
writel(r, priv->base + pll->pwr_reg);
r = readl(priv->base + pll->pwr_reg) & ~CON0_PWR_ON;
writel(r, priv->base + pll->pwr_reg);
return 0;
}
/* topckgen functions */
static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv,
ulong parent_rate)
{
u64 rate = parent_rate * fdiv->mult;
do_div(rate, fdiv->div);
return rate;
}
static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
ulong rate;
switch (fdiv->flags & CLK_PARENT_MASK) {
case CLK_PARENT_APMIXED:
rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
DM_GET_DRIVER(mtk_clk_apmixedsys));
break;
case CLK_PARENT_TOPCKGEN:
rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
break;
default:
rate = priv->tree->xtal_rate;
}
return mtk_factor_recalc_rate(fdiv, rate);
}
static int mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_composite *mux = &priv->tree->muxes[off];
u32 index;
index = readl(priv->base + mux->mux_reg);
index &= mux->mux_mask << mux->mux_shift;
index = index >> mux->mux_shift;
if (mux->parent[index])
return mtk_clk_find_parent_rate(clk, mux->parent[index],
NULL);
return priv->tree->xtal_rate;
}
static ulong mtk_topckgen_get_rate(struct clk *clk)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
if (clk->id < priv->tree->fdivs_offs)
return priv->tree->fclks[clk->id].rate;
else if (clk->id < priv->tree->muxes_offs)
return mtk_topckgen_get_factor_rate(clk, clk->id -
priv->tree->fdivs_offs);
else
return mtk_topckgen_get_mux_rate(clk, clk->id -
priv->tree->muxes_offs);
}
static int mtk_topckgen_enable(struct clk *clk)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_composite *mux;
u32 val;
if (clk->id < priv->tree->muxes_offs)
return 0;
mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
if (mux->gate_shift < 0)
return 0;
/* enable clock gate */
val = readl(priv->base + mux->gate_reg);
val &= ~BIT(mux->gate_shift);
writel(val, priv->base + mux->gate_reg);
if (mux->flags & CLK_DOMAIN_SCPSYS) {
/* enable scpsys clock off control */
writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0);
writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN,
priv->base + CLK_SCP_CFG1);
}
return 0;
}
static int mtk_topckgen_disable(struct clk *clk)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_composite *mux;
u32 val;
if (clk->id < priv->tree->muxes_offs)
return 0;
mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
if (mux->gate_shift < 0)
return 0;
/* disable clock gate */
val = readl(priv->base + mux->gate_reg);
val |= BIT(mux->gate_shift);
writel(val, priv->base + mux->gate_reg);
return 0;
}
static int mtk_topckgen_set_parent(struct clk *clk, struct clk *parent)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
if (clk->id < priv->tree->muxes_offs)
return 0;
return mtk_clk_mux_set_parent(priv->base, parent->id,
&priv->tree->muxes[clk->id - priv->tree->muxes_offs]);
}
/* CG functions */
static int mtk_clk_gate_enable(struct clk *clk)
{
struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
const struct mtk_gate *gate = &priv->gates[clk->id];
u32 bit = BIT(gate->shift);
switch (gate->flags & CLK_GATE_MASK) {
case CLK_GATE_SETCLR:
writel(bit, priv->base + gate->regs->clr_ofs);
break;
case CLK_GATE_SETCLR_INV:
writel(bit, priv->base + gate->regs->set_ofs);
break;
case CLK_GATE_NO_SETCLR:
clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
break;
case CLK_GATE_NO_SETCLR_INV:
clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
break;
default:
return -EINVAL;
}
return 0;
}
static int mtk_clk_gate_disable(struct clk *clk)
{
struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
const struct mtk_gate *gate = &priv->gates[clk->id];
u32 bit = BIT(gate->shift);
switch (gate->flags & CLK_GATE_MASK) {
case CLK_GATE_SETCLR:
writel(bit, priv->base + gate->regs->set_ofs);
break;
case CLK_GATE_SETCLR_INV:
writel(bit, priv->base + gate->regs->clr_ofs);
break;
case CLK_GATE_NO_SETCLR:
clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
break;
case CLK_GATE_NO_SETCLR_INV:
clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static ulong mtk_clk_gate_get_rate(struct clk *clk)
{
struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
const struct mtk_gate *gate = &priv->gates[clk->id];
switch (gate->flags & CLK_PARENT_MASK) {
case CLK_PARENT_APMIXED:
return mtk_clk_find_parent_rate(clk, gate->parent,
DM_GET_DRIVER(mtk_clk_apmixedsys));
break;
case CLK_PARENT_TOPCKGEN:
return mtk_clk_find_parent_rate(clk, gate->parent,
DM_GET_DRIVER(mtk_clk_topckgen));
break;
default:
return priv->tree->xtal_rate;
}
}
const struct clk_ops mtk_clk_apmixedsys_ops = {
.enable = mtk_apmixedsys_enable,
.disable = mtk_apmixedsys_disable,
.set_rate = mtk_apmixedsys_set_rate,
.get_rate = mtk_apmixedsys_get_rate,
};
const struct clk_ops mtk_clk_topckgen_ops = {
.enable = mtk_topckgen_enable,
.disable = mtk_topckgen_disable,
.get_rate = mtk_topckgen_get_rate,
.set_parent = mtk_topckgen_set_parent,
};
const struct clk_ops mtk_clk_gate_ops = {
.enable = mtk_clk_gate_enable,
.disable = mtk_clk_gate_disable,
.get_rate = mtk_clk_gate_get_rate,
};
int mtk_common_clk_init(struct udevice *dev,
const struct mtk_clk_tree *tree)
{
struct mtk_clk_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr_ptr(dev);
if (!priv->base)
return -ENOENT;
priv->tree = tree;
return 0;
}
int mtk_common_clk_gate_init(struct udevice *dev,
const struct mtk_clk_tree *tree,
const struct mtk_gate *gates)
{
struct mtk_cg_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr_ptr(dev);
if (!priv->base)
return -ENOENT;
priv->tree = tree;
priv->gates = gates;
return 0;
}
source/bootloader/u-boot-2020.01/drivers/clk/mediatek/clk-mtk.h
+196
View File
@@ -0,0 +1,196 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com>
*/
#ifndef __DRV_CLK_MTK_H
#define __DRV_CLK_MTK_H
#define CLK_XTAL 0
#define MHZ (1000 * 1000)
#define HAVE_RST_BAR BIT(0)
#define CLK_DOMAIN_SCPSYS BIT(0)
#define CLK_GATE_SETCLR BIT(0)
#define CLK_GATE_SETCLR_INV BIT(1)
#define CLK_GATE_NO_SETCLR BIT(2)
#define CLK_GATE_NO_SETCLR_INV BIT(3)
#define CLK_GATE_MASK GENMASK(3, 0)
#define CLK_PARENT_APMIXED BIT(4)
#define CLK_PARENT_TOPCKGEN BIT(5)
#define CLK_PARENT_MASK GENMASK(5, 4)
#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
/* struct mtk_pll_data - hardware-specific PLLs data */
struct mtk_pll_data {
const int id;
u32 reg;
u32 pwr_reg;
u32 en_mask;
u32 pd_reg;
int pd_shift;
u32 flags;
u32 rst_bar_mask;
u64 fmax;
int pcwbits;
u32 pcw_reg;
int pcw_shift;
};
/**
* struct mtk_fixed_clk - fixed clocks
*
* @id: index of clocks
* @parent: index of parnet clocks
* @rate: fixed rate
*/
struct mtk_fixed_clk {
const int id;
const int parent;
unsigned long rate;
};
#define FIXED_CLK(_id, _parent, _rate) { \
.id = _id, \
.parent = _parent, \
.rate = _rate, \
}
/**
* struct mtk_fixed_factor - fixed multiplier and divider clocks
*
* @id: index of clocks
* @parent: index of parnet clocks
* @mult: multiplier
* @div: divider
* @flag: hardware-specific flags
*/
struct mtk_fixed_factor {
const int id;
const int parent;
u32 mult;
u32 div;
u32 flags;
};
#define FACTOR(_id, _parent, _mult, _div, _flags) { \
.id = _id, \
.parent = _parent, \
.mult = _mult, \
.div = _div, \
.flags = _flags, \
}
/**
* struct mtk_composite - aggregate clock of mux, divider and gate clocks
*
* @id: index of clocks
* @parent: index of parnet clocks
* @mux_reg: hardware-specific mux register
* @gate_reg: hardware-specific gate register
* @mux_mask: mask to the mux bit field
* @mux_shift: shift to the mux bit field
* @gate_shift: shift to the gate bit field
* @num_parents: number of parent clocks
* @flags: hardware-specific flags
*/
struct mtk_composite {
const int id;
const int *parent;
u32 mux_reg;
u32 gate_reg;
u32 mux_mask;
signed char mux_shift;
signed char gate_shift;
signed char num_parents;
u16 flags;
};
#define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \
_flags) { \
.id = _id, \
.mux_reg = _reg, \
.mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, \
.gate_reg = _reg, \
.gate_shift = _gate, \
.parent = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
.flags = _flags, \
}
#define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \
MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
#define MUX(_id, _parents, _reg, _shift, _width) { \
.id = _id, \
.mux_reg = _reg, \
.mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, \
.gate_shift = -1, \
.parent = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
.flags = 0, \
}
struct mtk_gate_regs {
u32 sta_ofs;
u32 clr_ofs;
u32 set_ofs;
};
/**
* struct mtk_gate - gate clocks
*
* @id: index of gate clocks
* @parent: index of parnet clocks
* @regs: hardware-specific mux register
* @shift: shift to the gate bit field
* @flags: hardware-specific flags
*/
struct mtk_gate {
const int id;
const int parent;
const struct mtk_gate_regs *regs;
int shift;
u32 flags;
};
/* struct mtk_clk_tree - clock tree */
struct mtk_clk_tree {
unsigned long xtal_rate;
unsigned long xtal2_rate;
const int fdivs_offs;
const int muxes_offs;
const struct mtk_pll_data *plls;
const struct mtk_fixed_clk *fclks;
const struct mtk_fixed_factor *fdivs;
const struct mtk_composite *muxes;
};
struct mtk_clk_priv {
void __iomem *base;
const struct mtk_clk_tree *tree;
};
struct mtk_cg_priv {
void __iomem *base;
const struct mtk_clk_tree *tree;
const struct mtk_gate *gates;
};
extern const struct clk_ops mtk_clk_apmixedsys_ops;
extern const struct clk_ops mtk_clk_topckgen_ops;
extern const struct clk_ops mtk_clk_gate_ops;
int mtk_common_clk_init(struct udevice *dev,
const struct mtk_clk_tree *tree);
int mtk_common_clk_gate_init(struct udevice *dev,
const struct mtk_clk_tree *tree,
const struct mtk_gate *gates);
#endif /* __DRV_CLK_MTK_H */