GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,91 @@
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config CLK_RENESAS
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bool "Renesas clock drivers"
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depends on CLK && ARCH_RMOBILE
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help
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Enable support for clock present on Renesas RCar SoCs.
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config CLK_RCAR_GEN2
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bool "Renesas RCar Gen2 clock driver"
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def_bool y if RCAR_32
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depends on CLK_RENESAS
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help
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Enable this to support the clocks on Renesas RCar Gen2 SoC.
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config CLK_R8A7790
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bool "Renesas R8A7790 clock driver"
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depends on CLK_RCAR_GEN2
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help
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Enable this to support the clocks on Renesas R8A7790 SoC.
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config CLK_R8A7791
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bool "Renesas R8A7791 clock driver"
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depends on CLK_RCAR_GEN2
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help
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Enable this to support the clocks on Renesas R8A7791 SoC.
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config CLK_R8A7792
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bool "Renesas R8A7792 clock driver"
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depends on CLK_RCAR_GEN2
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help
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Enable this to support the clocks on Renesas R8A7792 SoC.
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config CLK_R8A7793
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bool "Renesas R8A7793 clock driver"
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depends on CLK_RCAR_GEN2
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help
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Enable this to support the clocks on Renesas R8A7793 SoC.
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config CLK_R8A7794
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bool "Renesas R8A7794 clock driver"
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depends on CLK_RCAR_GEN2
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help
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Enable this to support the clocks on Renesas R8A7794 SoC.
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config CLK_RCAR_GEN3
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bool "Renesas RCar Gen3 clock driver"
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def_bool y if RCAR_GEN3
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depends on CLK_RENESAS
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help
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Enable this to support the clocks on Renesas RCar Gen3 SoC.
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config CLK_R8A7795
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bool "Renesas R8A7795 clock driver"
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depends on CLK_RCAR_GEN3
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help
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Enable this to support the clocks on Renesas R8A7795 SoC.
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config CLK_R8A7796
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bool "Renesas R8A7796 clock driver"
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depends on CLK_RCAR_GEN3
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help
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Enable this to support the clocks on Renesas R8A7796 SoC.
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config CLK_R8A77965
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bool "Renesas R8A77965 clock driver"
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depends on CLK_RCAR_GEN3
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help
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Enable this to support the clocks on Renesas R8A77965 SoC.
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config CLK_R8A77970
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bool "Renesas R8A77970 clock driver"
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depends on CLK_RCAR_GEN3
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help
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Enable this to support the clocks on Renesas R8A77970 SoC.
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config CLK_R8A77980
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bool "Renesas R8A77980 clock driver"
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depends on CLK_RCAR_GEN3
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help
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Enable this to support the clocks on Renesas R8A77980 SoC.
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config CLK_R8A77990
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bool "Renesas R8A77990 clock driver"
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depends on CLK_RCAR_GEN3
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help
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Enable this to support the clocks on Renesas R8A77990 SoC.
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config CLK_R8A77995
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bool "Renesas R8A77995 clock driver"
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depends on CLK_RCAR_GEN3
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help
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Enable this to support the clocks on Renesas R8A77995 SoC.
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@@ -0,0 +1,15 @@
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obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
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obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
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obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7793) += r8a7791-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
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obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
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obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
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@@ -0,0 +1,324 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Renesas RCar Gen2 CPG MSSR driver
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*
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* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on the following driver from Linux kernel:
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* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2016 Glider bvba
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen2-cpg.h"
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#define CPG_RST_MODEMR 0x0060
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#define CPG_PLL0CR 0x00d8
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#define CPG_SDCKCR 0x0074
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struct clk_div_table {
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u8 val;
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u8 div;
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};
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/* SDHI divisors */
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static const struct clk_div_table cpg_sdh_div_table[] = {
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{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
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{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
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{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
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};
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static const struct clk_div_table cpg_sd01_div_table[] = {
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{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
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{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
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{ 0, 0 },
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};
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static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val)
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{
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for (;;) {
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if (!(*table).div)
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return 0xff;
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if ((*table).val == val)
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return (*table).div;
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table++;
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}
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}
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static int gen2_clk_enable(struct clk *clk)
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{
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struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
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return renesas_clk_endisable(clk, priv->base, true);
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}
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static int gen2_clk_disable(struct clk *clk)
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{
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struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
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return renesas_clk_endisable(clk, priv->base, false);
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}
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static ulong gen2_clk_get_rate(struct clk *clk)
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{
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struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
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struct cpg_mssr_info *info = priv->info;
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struct clk parent;
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const struct cpg_core_clk *core;
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const struct rcar_gen2_cpg_pll_config *pll_config =
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priv->cpg_pll_config;
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u32 value, mult, div, rate = 0;
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int ret;
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debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
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ret = renesas_clk_get_parent(clk, info, &parent);
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if (ret) {
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printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
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return ret;
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}
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if (renesas_clk_is_mod(clk)) {
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rate = gen2_clk_get_rate(&parent);
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debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
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__func__, __LINE__, parent.id, rate);
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return rate;
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}
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ret = renesas_clk_get_core(clk, info, &core);
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if (ret)
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return ret;
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switch (core->type) {
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case CLK_TYPE_IN:
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if (core->id == info->clk_extal_id) {
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rate = clk_get_rate(&priv->clk_extal);
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debug("%s[%i] EXTAL clk: rate=%u\n",
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__func__, __LINE__, rate);
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return rate;
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}
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if (core->id == info->clk_extal_usb_id) {
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rate = clk_get_rate(&priv->clk_extal_usb);
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debug("%s[%i] EXTALR clk: rate=%u\n",
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__func__, __LINE__, rate);
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return rate;
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}
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return -EINVAL;
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case CLK_TYPE_FF:
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rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
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debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, core->mult, core->div, rate);
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return rate;
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case CLK_TYPE_DIV6P1: /* DIV6 Clock with 1 parent clock */
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value = (readl(priv->base + core->offset) & 0x3f) + 1;
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rate = gen2_clk_get_rate(&parent) / value;
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debug("%s[%i] DIV6P1 clk: parent=%i div=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, value, rate);
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return rate;
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case CLK_TYPE_GEN2_MAIN:
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rate = gen2_clk_get_rate(&parent) / pll_config->extal_div;
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debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, pll_config->extal_div, rate);
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return rate;
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case CLK_TYPE_GEN2_PLL0:
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/*
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* PLL0 is a configurable multiplier clock except on R-Car
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* V2H/E2. Register the PLL0 clock as a fixed factor clock for
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* now as there's no generic multiplier clock implementation and
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* we currently have no need to change the multiplier value.
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*/
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mult = pll_config->pll0_mult;
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if (!mult) {
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value = readl(priv->base + CPG_PLL0CR);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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}
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rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div;
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debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
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__func__, __LINE__, core->parent, mult, rate);
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return rate;
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case CLK_TYPE_GEN2_PLL1:
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rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2;
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debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, pll_config->pll1_mult, rate);
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return rate;
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case CLK_TYPE_GEN2_PLL3:
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rate = gen2_clk_get_rate(&parent) * pll_config->pll3_mult;
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debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, pll_config->pll3_mult, rate);
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return rate;
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case CLK_TYPE_GEN2_SDH:
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value = (readl(priv->base + CPG_SDCKCR) >> 8) & 0xf;
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div = gen2_clk_get_sdh_div(cpg_sdh_div_table, value);
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rate = gen2_clk_get_rate(&parent) / div;
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debug("%s[%i] SDH clk: parent=%i div=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, div, rate);
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return rate;
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case CLK_TYPE_GEN2_SD0:
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value = (readl(priv->base + CPG_SDCKCR) >> 4) & 0xf;
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div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
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rate = gen2_clk_get_rate(&parent) / div;
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debug("%s[%i] SD0 clk: parent=%i div=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, div, rate);
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return rate;
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case CLK_TYPE_GEN2_SD1:
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value = (readl(priv->base + CPG_SDCKCR) >> 0) & 0xf;
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div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
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rate = gen2_clk_get_rate(&parent) / div;
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debug("%s[%i] SD1 clk: parent=%i div=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, div, rate);
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return rate;
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}
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printf("%s[%i] unknown fail\n", __func__, __LINE__);
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return -ENOENT;
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}
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static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate)
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{
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struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
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struct cpg_mssr_info *info = priv->info;
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const struct cpg_core_clk *core;
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struct clk parent, pparent;
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u32 val;
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int ret;
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ret = renesas_clk_get_parent(clk, info, &parent);
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if (ret) {
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debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
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return ret;
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}
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if (renesas_clk_is_mod(&parent))
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return 0;
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ret = renesas_clk_get_core(&parent, info, &core);
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if (ret)
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return ret;
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if (strcmp(core->name, "mmc0") && strcmp(core->name, "mmc1"))
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return 0;
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ret = renesas_clk_get_parent(&parent, info, &pparent);
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if (ret) {
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debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
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return ret;
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}
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val = (gen2_clk_get_rate(&pparent) / rate) - 1;
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debug("%s[%i] MMCIF offset=%x\n", __func__, __LINE__, core->offset);
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writel(val, priv->base + core->offset);
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return 0;
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}
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static ulong gen2_clk_set_rate(struct clk *clk, ulong rate)
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{
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/* Force correct MMC-IF divider configuration if applicable */
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gen2_clk_setup_mmcif_div(clk, rate);
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return gen2_clk_get_rate(clk);
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}
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static int gen2_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
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{
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if (args->args_count != 2) {
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debug("Invaild args_count: %d\n", args->args_count);
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return -EINVAL;
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}
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clk->id = (args->args[0] << 16) | args->args[1];
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return 0;
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}
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const struct clk_ops gen2_clk_ops = {
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.enable = gen2_clk_enable,
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.disable = gen2_clk_disable,
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.get_rate = gen2_clk_get_rate,
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.set_rate = gen2_clk_set_rate,
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.of_xlate = gen2_clk_of_xlate,
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};
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int gen2_clk_probe(struct udevice *dev)
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{
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struct gen2_clk_priv *priv = dev_get_priv(dev);
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struct cpg_mssr_info *info =
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(struct cpg_mssr_info *)dev_get_driver_data(dev);
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fdt_addr_t rst_base;
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u32 cpg_mode;
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int ret;
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priv->base = (struct gen2_base *)devfdt_get_addr(dev);
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if (!priv->base)
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return -EINVAL;
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priv->info = info;
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ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
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if (ret < 0)
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return ret;
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rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
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if (rst_base == FDT_ADDR_T_NONE)
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return -EINVAL;
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cpg_mode = readl(rst_base + CPG_RST_MODEMR);
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priv->cpg_pll_config =
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(struct rcar_gen2_cpg_pll_config *)info->get_pll_config(cpg_mode);
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if (!priv->cpg_pll_config->extal_div)
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return -EINVAL;
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ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
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if (ret < 0)
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return ret;
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|
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if (info->extal_usb_node) {
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ret = clk_get_by_name(dev, info->extal_usb_node,
|
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&priv->clk_extal_usb);
|
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if (ret < 0)
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return ret;
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}
|
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|
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return 0;
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}
|
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|
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int gen2_clk_remove(struct udevice *dev)
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{
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struct gen2_clk_priv *priv = dev_get_priv(dev);
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|
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return renesas_clk_remove(priv->base, priv->info);
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}
|
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@@ -0,0 +1,400 @@
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||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Renesas RCar Gen3 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <wait_bit.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
#define CPG_RST_MODEMR 0x0060
|
||||
|
||||
#define CPG_PLL0CR 0x00d8
|
||||
#define CPG_PLL2CR 0x002c
|
||||
#define CPG_PLL4CR 0x01f4
|
||||
|
||||
#define CPG_RPC_PREDIV_MASK 0x3
|
||||
#define CPG_RPC_PREDIV_OFFSET 3
|
||||
#define CPG_RPC_POSTDIV_MASK 0x7
|
||||
#define CPG_RPC_POSTDIV_OFFSET 0
|
||||
|
||||
/*
|
||||
* SDn Clock
|
||||
*/
|
||||
#define CPG_SD_STP_HCK BIT(9)
|
||||
#define CPG_SD_STP_CK BIT(8)
|
||||
|
||||
#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
|
||||
#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
|
||||
|
||||
#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
|
||||
{ \
|
||||
.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
|
||||
((stp_ck) ? CPG_SD_STP_CK : 0) | \
|
||||
((sd_srcfc) << 2) | \
|
||||
((sd_fc) << 0), \
|
||||
.div = (sd_div), \
|
||||
}
|
||||
|
||||
struct sd_div_table {
|
||||
u32 val;
|
||||
unsigned int div;
|
||||
};
|
||||
|
||||
/* SDn divider
|
||||
* sd_srcfc sd_fc div
|
||||
* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 (1) 1 (4) 4
|
||||
* 0 0 1 (2) 1 (4) 8
|
||||
* 1 0 2 (4) 1 (4) 16
|
||||
* 1 0 3 (8) 1 (4) 32
|
||||
* 1 0 4 (16) 1 (4) 64
|
||||
* 0 0 0 (1) 0 (2) 2
|
||||
* 0 0 1 (2) 0 (2) 4
|
||||
* 1 0 2 (4) 0 (2) 8
|
||||
* 1 0 3 (8) 0 (2) 16
|
||||
* 1 0 4 (16) 0 (2) 32
|
||||
*/
|
||||
static const struct sd_div_table cpg_sd_div_table[] = {
|
||||
/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
|
||||
};
|
||||
|
||||
static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
|
||||
struct cpg_mssr_info *info, struct clk *parent)
|
||||
{
|
||||
const struct cpg_core_clk *core;
|
||||
int ret;
|
||||
|
||||
if (!renesas_clk_is_mod(clk)) {
|
||||
ret = renesas_clk_get_core(clk, info, &core);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (core->type == CLK_TYPE_GEN3_MDSEL) {
|
||||
parent->dev = clk->dev;
|
||||
parent->id = core->parent >> (priv->sscg ? 16 : 0);
|
||||
parent->id &= 0xffff;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return renesas_clk_get_parent(clk, info, parent);
|
||||
}
|
||||
|
||||
static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
|
||||
{
|
||||
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
struct cpg_mssr_info *info = priv->info;
|
||||
const struct cpg_core_clk *core;
|
||||
struct clk parent;
|
||||
int ret;
|
||||
|
||||
ret = gen3_clk_get_parent(priv, clk, info, &parent);
|
||||
if (ret) {
|
||||
printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (renesas_clk_is_mod(&parent))
|
||||
return 0;
|
||||
|
||||
ret = renesas_clk_get_core(&parent, info, &core);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (core->type != CLK_TYPE_GEN3_SD)
|
||||
return 0;
|
||||
|
||||
debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
|
||||
|
||||
writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gen3_clk_enable(struct clk *clk)
|
||||
{
|
||||
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
|
||||
return renesas_clk_endisable(clk, priv->base, true);
|
||||
}
|
||||
|
||||
static int gen3_clk_disable(struct clk *clk)
|
||||
{
|
||||
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
|
||||
return renesas_clk_endisable(clk, priv->base, false);
|
||||
}
|
||||
|
||||
static u64 gen3_clk_get_rate64(struct clk *clk)
|
||||
{
|
||||
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
struct cpg_mssr_info *info = priv->info;
|
||||
struct clk parent;
|
||||
const struct cpg_core_clk *core;
|
||||
const struct rcar_gen3_cpg_pll_config *pll_config =
|
||||
priv->cpg_pll_config;
|
||||
u32 value, mult, div, prediv, postdiv;
|
||||
u64 rate = 0;
|
||||
int i, ret;
|
||||
|
||||
debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
|
||||
|
||||
ret = gen3_clk_get_parent(priv, clk, info, &parent);
|
||||
if (ret) {
|
||||
printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (renesas_clk_is_mod(clk)) {
|
||||
rate = gen3_clk_get_rate64(&parent);
|
||||
debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n",
|
||||
__func__, __LINE__, parent.id, rate);
|
||||
return rate;
|
||||
}
|
||||
|
||||
ret = renesas_clk_get_core(clk, info, &core);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_IN:
|
||||
if (core->id == info->clk_extal_id) {
|
||||
rate = clk_get_rate(&priv->clk_extal);
|
||||
debug("%s[%i] EXTAL clk: rate=%llu\n",
|
||||
__func__, __LINE__, rate);
|
||||
return rate;
|
||||
}
|
||||
|
||||
if (core->id == info->clk_extalr_id) {
|
||||
rate = clk_get_rate(&priv->clk_extalr);
|
||||
debug("%s[%i] EXTALR clk: rate=%llu\n",
|
||||
__func__, __LINE__, rate);
|
||||
return rate;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
|
||||
case CLK_TYPE_GEN3_MAIN:
|
||||
rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div;
|
||||
debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, pll_config->extal_div, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL0:
|
||||
value = readl(priv->base + CPG_PLL0CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
rate = gen3_clk_get_rate64(&parent) * mult;
|
||||
debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",
|
||||
__func__, __LINE__, core->parent, mult, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL1:
|
||||
rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
|
||||
rate /= pll_config->pll1_div;
|
||||
debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, pll_config->pll1_mult,
|
||||
pll_config->pll1_div, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL2:
|
||||
value = readl(priv->base + CPG_PLL2CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
rate = gen3_clk_get_rate64(&parent) * mult;
|
||||
debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",
|
||||
__func__, __LINE__, core->parent, mult, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL3:
|
||||
rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
|
||||
rate /= pll_config->pll3_div;
|
||||
debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, pll_config->pll3_mult,
|
||||
pll_config->pll3_div, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL4:
|
||||
value = readl(priv->base + CPG_PLL4CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
rate = gen3_clk_get_rate64(&parent) * mult;
|
||||
debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%llu\n",
|
||||
__func__, __LINE__, core->parent, mult, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_FF:
|
||||
rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div;
|
||||
debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, core->mult, core->div, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN3_MDSEL:
|
||||
div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
|
||||
rate = gen3_clk_get_rate64(&parent) / div;
|
||||
debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
|
||||
__func__, __LINE__,
|
||||
(core->parent >> (priv->sscg ? 16 : 0)) & 0xffff,
|
||||
div, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN3_SD: /* FIXME */
|
||||
value = readl(priv->base + core->offset);
|
||||
value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
|
||||
if (cpg_sd_div_table[i].val != value)
|
||||
continue;
|
||||
|
||||
rate = gen3_clk_get_rate64(&parent) /
|
||||
cpg_sd_div_table[i].div;
|
||||
debug("%s[%i] SD clk: parent=%i div=%i => rate=%llu\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, cpg_sd_div_table[i].div, rate);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
|
||||
case CLK_TYPE_GEN3_RPC:
|
||||
rate = gen3_clk_get_rate64(&parent);
|
||||
|
||||
value = readl(priv->base + core->offset);
|
||||
|
||||
prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
|
||||
CPG_RPC_PREDIV_MASK;
|
||||
if (prediv == 2)
|
||||
rate /= 5;
|
||||
else if (prediv == 3)
|
||||
rate /= 6;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
|
||||
CPG_RPC_POSTDIV_MASK;
|
||||
rate /= postdiv + 1;
|
||||
|
||||
debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, prediv, postdiv, rate);
|
||||
|
||||
return -EINVAL;
|
||||
|
||||
}
|
||||
|
||||
printf("%s[%i] unknown fail\n", __func__, __LINE__);
|
||||
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static ulong gen3_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return gen3_clk_get_rate64(clk);
|
||||
}
|
||||
|
||||
static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
|
||||
{
|
||||
/* Force correct SD-IF divider configuration if applicable */
|
||||
gen3_clk_setup_sdif_div(clk, rate);
|
||||
return gen3_clk_get_rate64(clk);
|
||||
}
|
||||
|
||||
static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
|
||||
{
|
||||
if (args->args_count != 2) {
|
||||
debug("Invaild args_count: %d\n", args->args_count);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
clk->id = (args->args[0] << 16) | args->args[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops gen3_clk_ops = {
|
||||
.enable = gen3_clk_enable,
|
||||
.disable = gen3_clk_disable,
|
||||
.get_rate = gen3_clk_get_rate,
|
||||
.set_rate = gen3_clk_set_rate,
|
||||
.of_xlate = gen3_clk_of_xlate,
|
||||
};
|
||||
|
||||
int gen3_clk_probe(struct udevice *dev)
|
||||
{
|
||||
struct gen3_clk_priv *priv = dev_get_priv(dev);
|
||||
struct cpg_mssr_info *info =
|
||||
(struct cpg_mssr_info *)dev_get_driver_data(dev);
|
||||
fdt_addr_t rst_base;
|
||||
u32 cpg_mode;
|
||||
int ret;
|
||||
|
||||
priv->base = (struct gen3_base *)devfdt_get_addr(dev);
|
||||
if (!priv->base)
|
||||
return -EINVAL;
|
||||
|
||||
priv->info = info;
|
||||
ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
|
||||
if (rst_base == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
cpg_mode = readl(rst_base + CPG_RST_MODEMR);
|
||||
|
||||
priv->cpg_pll_config =
|
||||
(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
|
||||
if (!priv->cpg_pll_config->extal_div)
|
||||
return -EINVAL;
|
||||
|
||||
priv->sscg = !(cpg_mode & BIT(12));
|
||||
|
||||
ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (info->extalr_node) {
|
||||
ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int gen3_clk_remove(struct udevice *dev)
|
||||
{
|
||||
struct gen3_clk_priv *priv = dev_get_priv(dev);
|
||||
|
||||
return renesas_clk_remove(priv->base, priv->info);
|
||||
}
|
||||
@@ -0,0 +1,289 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a7790 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen2.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7790_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_USB_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7790_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7790_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
|
||||
DEF_BASE("lb", R8A7790_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("adsp", R8A7790_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7790_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7790_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
DEF_BASE("sd1", R8A7790_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
|
||||
DEF_BASE("qspi", R8A7790_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
DEF_BASE("rcan", R8A7790_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
|
||||
|
||||
DEF_FIXED("z2", R8A7790_CLK_Z2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("zg", R8A7790_CLK_ZG, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zx", R8A7790_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zs", R8A7790_CLK_ZS, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("hp", R8A7790_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7790_CLK_I, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("b", R8A7790_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("p", R8A7790_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7790_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7790_CLK_M2, CLK_PLL1, 8, 1),
|
||||
DEF_FIXED("imp", R8A7790_CLK_IMP, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED("zb3", R8A7790_CLK_ZB3, CLK_PLL3, 4, 1),
|
||||
DEF_FIXED("zb3d2", R8A7790_CLK_ZB3D2, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("ddr", R8A7790_CLK_DDR, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("mp", R8A7790_CLK_MP, CLK_PLL1_DIV2, 15, 1),
|
||||
DEF_FIXED("cp", R8A7790_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("r", R8A7790_CLK_R, CLK_PLL1, 49152, 1),
|
||||
DEF_FIXED("osc", R8A7790_CLK_OSC, CLK_PLL1, 12288, 1),
|
||||
|
||||
DEF_DIV6P1("sd2", R8A7790_CLK_SD2, CLK_PLL1_DIV2, 0x078),
|
||||
DEF_DIV6P1("sd3", R8A7790_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
|
||||
DEF_DIV6P1("mmc0", R8A7790_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
|
||||
DEF_DIV6P1("mmc1", R8A7790_CLK_MMC1, CLK_PLL1_DIV2, 0x244),
|
||||
DEF_DIV6P1("ssp", R8A7790_CLK_SSP, CLK_PLL1_DIV2, 0x248),
|
||||
DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7790_mod_clks[] = {
|
||||
DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
|
||||
DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vpc1", 102, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vpc0", 103, R8A7790_CLK_ZS),
|
||||
DEF_MOD("jpu", 106, R8A7790_CLK_M2),
|
||||
DEF_MOD("ssp1", 109, R8A7790_CLK_ZS),
|
||||
DEF_MOD("tmu1", 111, R8A7790_CLK_P),
|
||||
DEF_MOD("3dg", 112, R8A7790_CLK_ZG),
|
||||
DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
|
||||
DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
|
||||
DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
|
||||
DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS),
|
||||
DEF_MOD("tmu3", 121, R8A7790_CLK_P),
|
||||
DEF_MOD("tmu2", 122, R8A7790_CLK_P),
|
||||
DEF_MOD("cmt0", 124, R8A7790_CLK_R),
|
||||
DEF_MOD("tmu0", 125, R8A7790_CLK_CP),
|
||||
DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS),
|
||||
DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS),
|
||||
DEF_MOD("scifa2", 202, R8A7790_CLK_MP),
|
||||
DEF_MOD("scifa1", 203, R8A7790_CLK_MP),
|
||||
DEF_MOD("scifa0", 204, R8A7790_CLK_MP),
|
||||
DEF_MOD("msiof2", 205, R8A7790_CLK_MP),
|
||||
DEF_MOD("scifb0", 206, R8A7790_CLK_MP),
|
||||
DEF_MOD("scifb1", 207, R8A7790_CLK_MP),
|
||||
DEF_MOD("msiof1", 208, R8A7790_CLK_MP),
|
||||
DEF_MOD("msiof3", 215, R8A7790_CLK_MP),
|
||||
DEF_MOD("scifb2", 216, R8A7790_CLK_MP),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7790_CLK_ZS),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7790_CLK_ZS),
|
||||
DEF_MOD("iic2", 300, R8A7790_CLK_HP),
|
||||
DEF_MOD("tpu0", 304, R8A7790_CLK_CP),
|
||||
DEF_MOD("mmcif1", 305, R8A7790_CLK_MMC1),
|
||||
DEF_MOD("scif2", 310, R8A7790_CLK_P),
|
||||
DEF_MOD("sdhi3", 311, R8A7790_CLK_SD3),
|
||||
DEF_MOD("sdhi2", 312, R8A7790_CLK_SD2),
|
||||
DEF_MOD("sdhi1", 313, R8A7790_CLK_SD1),
|
||||
DEF_MOD("sdhi0", 314, R8A7790_CLK_SD0),
|
||||
DEF_MOD("mmcif0", 315, R8A7790_CLK_MMC0),
|
||||
DEF_MOD("iic0", 318, R8A7790_CLK_HP),
|
||||
DEF_MOD("pciec", 319, R8A7790_CLK_MP),
|
||||
DEF_MOD("iic1", 323, R8A7790_CLK_HP),
|
||||
DEF_MOD("usb3.0", 328, R8A7790_CLK_MP),
|
||||
DEF_MOD("cmt1", 329, R8A7790_CLK_R),
|
||||
DEF_MOD("usbhs-dmac0", 330, R8A7790_CLK_HP),
|
||||
DEF_MOD("usbhs-dmac1", 331, R8A7790_CLK_HP),
|
||||
DEF_MOD("rwdt", 402, R8A7790_CLK_R),
|
||||
DEF_MOD("irqc", 407, R8A7790_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7790_CLK_ZS),
|
||||
DEF_MOD("audio-dmac1", 501, R8A7790_CLK_HP),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7790_CLK_HP),
|
||||
DEF_MOD("adsp_mod", 506, R8A7790_CLK_ADSP),
|
||||
DEF_MOD("thermal", 522, CLK_EXTAL),
|
||||
DEF_MOD("pwm", 523, R8A7790_CLK_P),
|
||||
DEF_MOD("usb-ehci", 703, R8A7790_CLK_MP),
|
||||
DEF_MOD("usbhs", 704, R8A7790_CLK_HP),
|
||||
DEF_MOD("hscif1", 716, R8A7790_CLK_ZS),
|
||||
DEF_MOD("hscif0", 717, R8A7790_CLK_ZS),
|
||||
DEF_MOD("scif1", 720, R8A7790_CLK_P),
|
||||
DEF_MOD("scif0", 721, R8A7790_CLK_P),
|
||||
DEF_MOD("du2", 722, R8A7790_CLK_ZX),
|
||||
DEF_MOD("du1", 723, R8A7790_CLK_ZX),
|
||||
DEF_MOD("du0", 724, R8A7790_CLK_ZX),
|
||||
DEF_MOD("lvds1", 725, R8A7790_CLK_ZX),
|
||||
DEF_MOD("lvds0", 726, R8A7790_CLK_ZX),
|
||||
DEF_MOD("mlb", 802, R8A7790_CLK_HP),
|
||||
DEF_MOD("vin3", 808, R8A7790_CLK_ZG),
|
||||
DEF_MOD("vin2", 809, R8A7790_CLK_ZG),
|
||||
DEF_MOD("vin1", 810, R8A7790_CLK_ZG),
|
||||
DEF_MOD("vin0", 811, R8A7790_CLK_ZG),
|
||||
DEF_MOD("etheravb", 812, R8A7790_CLK_HP),
|
||||
DEF_MOD("ether", 813, R8A7790_CLK_P),
|
||||
DEF_MOD("sata1", 814, R8A7790_CLK_ZS),
|
||||
DEF_MOD("sata0", 815, R8A7790_CLK_ZS),
|
||||
DEF_MOD("gyro-adc", 901, R8A7790_CLK_P),
|
||||
DEF_MOD("gpio5", 907, R8A7790_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A7790_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A7790_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A7790_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A7790_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A7790_CLK_CP),
|
||||
DEF_MOD("can1", 915, R8A7790_CLK_P),
|
||||
DEF_MOD("can0", 916, R8A7790_CLK_P),
|
||||
DEF_MOD("qspi_mod", 917, R8A7790_CLK_QSPI),
|
||||
DEF_MOD("iicdvfs", 926, R8A7790_CLK_CP),
|
||||
DEF_MOD("i2c3", 928, R8A7790_CLK_HP),
|
||||
DEF_MOD("i2c2", 929, R8A7790_CLK_HP),
|
||||
DEF_MOD("i2c1", 930, R8A7790_CLK_HP),
|
||||
DEF_MOD("i2c0", 931, R8A7790_CLK_HP),
|
||||
DEF_MOD("ssi-all", 1005, R8A7790_CLK_P),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7790_CLK_P),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *1
|
||||
*---------------------------------------------------
|
||||
* 0 0 0 15 x172/2 x208/2 x106
|
||||
* 0 0 1 15 x172/2 x208/2 x88
|
||||
* 0 1 0 20 x130/2 x156/2 x80
|
||||
* 0 1 1 20 x130/2 x156/2 x66
|
||||
* 1 0 0 26 / 2 x200/2 x240/2 x122
|
||||
* 1 0 1 26 / 2 x200/2 x240/2 x102
|
||||
* 1 1 0 30 / 2 x172/2 x208/2 x106
|
||||
* 1 1 1 30 / 2 x172/2 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
|
||||
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
|
||||
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7790_mstp_table[] = {
|
||||
{ 0x00640801, 0x400000, 0x00640801, 0x0 },
|
||||
{ 0xDB6E9BDF, 0x0, 0xDB6E9BDF, 0x0 },
|
||||
{ 0x300DA1FC, 0x2010, 0x300DA1FC, 0x0 },
|
||||
{ 0xF08CF831, 0x0, 0xF08CF831, 0x0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0x0 },
|
||||
{ 0x44C00046, 0x0, 0x44C00046, 0x0 },
|
||||
{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
|
||||
{ 0x07F30718, 0x200000, 0x07F30718, 0x0 },
|
||||
{ 0x01F0FF84, 0x0, 0x01F0FF84, 0x0 },
|
||||
{ 0xF5979FCF, 0x0, 0xF5979FCF, 0x0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x00000000, 0x0 },
|
||||
};
|
||||
|
||||
static const void *r8a7790_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7790_cpg_mssr_info = {
|
||||
.core_clk = r8a7790_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7790_core_clks),
|
||||
.mod_clk = r8a7790_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7790_mod_clks),
|
||||
.mstp_table = r8a7790_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7790_mstp_table),
|
||||
.reset_node = "renesas,r8a7790-rst",
|
||||
.extal_usb_node = "usb_extal",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extal_usb_id = CLK_USB_EXTAL,
|
||||
.pll0_div = 2,
|
||||
.get_pll_config = r8a7790_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7790_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7790-cpg-mssr",
|
||||
.data = (ulong)&r8a7790_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7790) = {
|
||||
.name = "clk_r8a7790",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7790_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
|
||||
.ops = &gen2_clk_ops,
|
||||
.probe = gen2_clk_probe,
|
||||
.remove = gen2_clk_remove,
|
||||
};
|
||||
@@ -0,0 +1,295 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R8A7791 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7791 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2015-2017 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen2.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7791_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_USB_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7791_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
|
||||
DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
DEF_BASE("qspi", R8A7791_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
DEF_BASE("rcan", R8A7791_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
|
||||
|
||||
DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("lb", R8A7791_CLK_LB, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
|
||||
DEF_FIXED("zb3", R8A7791_CLK_ZB3, CLK_PLL3, 4, 1),
|
||||
DEF_FIXED("zb3d2", R8A7791_CLK_ZB3D2, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("ddr", R8A7791_CLK_DDR, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("mp", R8A7791_CLK_MP, CLK_PLL1_DIV2, 15, 1),
|
||||
DEF_FIXED("cp", R8A7791_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("r", R8A7791_CLK_R, CLK_PLL1, 49152, 1),
|
||||
DEF_FIXED("osc", R8A7791_CLK_OSC, CLK_PLL1, 12288, 1),
|
||||
|
||||
DEF_DIV6P1("sd2", R8A7791_CLK_SD2, CLK_PLL1_DIV2, 0x078),
|
||||
DEF_DIV6P1("sd3", R8A7791_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
|
||||
DEF_DIV6P1("mmc0", R8A7791_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
|
||||
DEF_DIV6P1("ssp", R8A7791_CLK_SSP, CLK_PLL1_DIV2, 0x248),
|
||||
DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7791_mod_clks[] = {
|
||||
DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
|
||||
DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
|
||||
DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
|
||||
DEF_MOD("jpu", 106, R8A7791_CLK_M2),
|
||||
DEF_MOD("ssp1", 109, R8A7791_CLK_ZS),
|
||||
DEF_MOD("tmu1", 111, R8A7791_CLK_P),
|
||||
DEF_MOD("3dg", 112, R8A7791_CLK_ZG),
|
||||
DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
|
||||
DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
|
||||
DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
|
||||
DEF_MOD("tmu3", 121, R8A7791_CLK_P),
|
||||
DEF_MOD("tmu2", 122, R8A7791_CLK_P),
|
||||
DEF_MOD("cmt0", 124, R8A7791_CLK_R),
|
||||
DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
|
||||
DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
|
||||
DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
|
||||
DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS),
|
||||
DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifa0", 204, R8A7791_CLK_MP),
|
||||
DEF_MOD("msiof2", 205, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifb0", 206, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifb1", 207, R8A7791_CLK_MP),
|
||||
DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifb2", 216, R8A7791_CLK_MP),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7791_CLK_ZS),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7791_CLK_ZS),
|
||||
DEF_MOD("tpu0", 304, R8A7791_CLK_CP),
|
||||
DEF_MOD("sdhi3", 311, R8A7791_CLK_SD3),
|
||||
DEF_MOD("sdhi2", 312, R8A7791_CLK_SD2),
|
||||
DEF_MOD("sdhi0", 314, R8A7791_CLK_SD0),
|
||||
DEF_MOD("mmcif0", 315, R8A7791_CLK_MMC0),
|
||||
DEF_MOD("iic0", 318, R8A7791_CLK_HP),
|
||||
DEF_MOD("pciec", 319, R8A7791_CLK_MP),
|
||||
DEF_MOD("iic1", 323, R8A7791_CLK_HP),
|
||||
DEF_MOD("usb3.0", 328, R8A7791_CLK_MP),
|
||||
DEF_MOD("cmt1", 329, R8A7791_CLK_R),
|
||||
DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
|
||||
DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
|
||||
DEF_MOD("rwdt", 402, R8A7791_CLK_R),
|
||||
DEF_MOD("irqc", 407, R8A7791_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
|
||||
DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7791_CLK_HP),
|
||||
DEF_MOD("adsp_mod", 506, R8A7791_CLK_ADSP),
|
||||
DEF_MOD("thermal", 522, CLK_EXTAL),
|
||||
DEF_MOD("pwm", 523, R8A7791_CLK_P),
|
||||
DEF_MOD("usb-ehci", 703, R8A7791_CLK_MP),
|
||||
DEF_MOD("usbhs", 704, R8A7791_CLK_HP),
|
||||
DEF_MOD("hscif2", 713, R8A7791_CLK_ZS),
|
||||
DEF_MOD("scif5", 714, R8A7791_CLK_P),
|
||||
DEF_MOD("scif4", 715, R8A7791_CLK_P),
|
||||
DEF_MOD("hscif1", 716, R8A7791_CLK_ZS),
|
||||
DEF_MOD("hscif0", 717, R8A7791_CLK_ZS),
|
||||
DEF_MOD("scif3", 718, R8A7791_CLK_P),
|
||||
DEF_MOD("scif2", 719, R8A7791_CLK_P),
|
||||
DEF_MOD("scif1", 720, R8A7791_CLK_P),
|
||||
DEF_MOD("scif0", 721, R8A7791_CLK_P),
|
||||
DEF_MOD("du1", 723, R8A7791_CLK_ZX),
|
||||
DEF_MOD("du0", 724, R8A7791_CLK_ZX),
|
||||
DEF_MOD("lvds0", 726, R8A7791_CLK_ZX),
|
||||
DEF_MOD("ipmmu-sgx", 800, R8A7791_CLK_ZX),
|
||||
DEF_MOD("mlb", 802, R8A7791_CLK_HP),
|
||||
DEF_MOD("vin2", 809, R8A7791_CLK_ZG),
|
||||
DEF_MOD("vin1", 810, R8A7791_CLK_ZG),
|
||||
DEF_MOD("vin0", 811, R8A7791_CLK_ZG),
|
||||
DEF_MOD("etheravb", 812, R8A7791_CLK_HP),
|
||||
DEF_MOD("ether", 813, R8A7791_CLK_P),
|
||||
DEF_MOD("sata1", 814, R8A7791_CLK_ZS),
|
||||
DEF_MOD("sata0", 815, R8A7791_CLK_ZS),
|
||||
DEF_MOD("gyro-adc", 901, R8A7791_CLK_P),
|
||||
DEF_MOD("gpio7", 904, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio6", 905, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio5", 907, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A7791_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A7791_CLK_CP),
|
||||
DEF_MOD("can1", 915, R8A7791_CLK_P),
|
||||
DEF_MOD("can0", 916, R8A7791_CLK_P),
|
||||
DEF_MOD("qspi_mod", 917, R8A7791_CLK_QSPI),
|
||||
DEF_MOD("i2c5", 925, R8A7791_CLK_HP),
|
||||
DEF_MOD("iicdvfs", 926, R8A7791_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A7791_CLK_HP),
|
||||
DEF_MOD("i2c3", 928, R8A7791_CLK_HP),
|
||||
DEF_MOD("i2c2", 929, R8A7791_CLK_HP),
|
||||
DEF_MOD("i2c1", 930, R8A7791_CLK_HP),
|
||||
DEF_MOD("i2c0", 931, R8A7791_CLK_HP),
|
||||
DEF_MOD("ssi-all", 1005, R8A7791_CLK_P),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7791_CLK_P),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scifa3", 1106, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifa4", 1107, R8A7791_CLK_MP),
|
||||
DEF_MOD("scifa5", 1108, R8A7791_CLK_MP),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *1
|
||||
*---------------------------------------------------
|
||||
* 0 0 0 15 x172/2 x208/2 x106
|
||||
* 0 0 1 15 x172/2 x208/2 x88
|
||||
* 0 1 0 20 x130/2 x156/2 x80
|
||||
* 0 1 1 20 x130/2 x156/2 x66
|
||||
* 1 0 0 26 / 2 x200/2 x240/2 x122
|
||||
* 1 0 1 26 / 2 x200/2 x240/2 x102
|
||||
* 1 1 0 30 / 2 x172/2 x208/2 x106
|
||||
* 1 1 1 30 / 2 x172/2 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
|
||||
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
|
||||
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7791_mstp_table[] = {
|
||||
{ 0x00640801, 0x400000, 0x00640801, 0x0 },
|
||||
{ 0x9B6C9B5A, 0x0, 0x9B6C9B5A, 0x0 },
|
||||
{ 0x100D21FC, 0x2000, 0x100D21FC, 0x0 },
|
||||
{ 0xF08CD810, 0x0, 0xF08CD810, 0x0 },
|
||||
{ 0x800001C4, 0x180, 0x800001C4, 0x0 },
|
||||
{ 0x44C00046, 0x0, 0x44C00046, 0x0 },
|
||||
{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
|
||||
{ 0x05BFE618, 0x200000, 0x05BFE618, 0x0 },
|
||||
{ 0x40C0FE85, 0x0, 0x40C0FE85, 0x0 },
|
||||
{ 0xFF979FFF, 0x0, 0xFF979FFF, 0x0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
|
||||
{ 0x000001C0, 0x0, 0x000001C0, 0x0 },
|
||||
};
|
||||
|
||||
static const void *r8a7791_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7791_cpg_mssr_info = {
|
||||
.core_clk = r8a7791_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7791_core_clks),
|
||||
.mod_clk = r8a7791_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7791_mod_clks),
|
||||
.mstp_table = r8a7791_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7791_mstp_table),
|
||||
.reset_node = "renesas,r8a7791-rst",
|
||||
.extal_usb_node = "usb_extal",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extal_usb_id = CLK_USB_EXTAL,
|
||||
.pll0_div = 2,
|
||||
.get_pll_config = r8a7791_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7791_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7791-cpg-mssr",
|
||||
.data = (ulong)&r8a7791_cpg_mssr_info
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,r8a7793-cpg-mssr",
|
||||
.data = (ulong)&r8a7791_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7791) = {
|
||||
.name = "clk_r8a7791",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7791_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
|
||||
.ops = &gen2_clk_ops,
|
||||
.probe = gen2_clk_probe,
|
||||
.remove = gen2_clk_remove,
|
||||
};
|
||||
@@ -0,0 +1,241 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a7792 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen2.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7792_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7792_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
|
||||
DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
|
||||
DEF_FIXED("zg", R8A7792_CLK_ZG, CLK_PLL1, 5, 1),
|
||||
DEF_FIXED("zx", R8A7792_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zs", R8A7792_CLK_ZS, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("lb", R8A7792_CLK_LB, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
|
||||
DEF_FIXED("imp", R8A7792_CLK_IMP, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED("zb3", R8A7792_CLK_ZB3, CLK_PLL3, 4, 1),
|
||||
DEF_FIXED("zb3d2", R8A7792_CLK_ZB3D2, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("ddr", R8A7792_CLK_DDR, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("sd", R8A7792_CLK_SD, CLK_PLL1_DIV2, 8, 1),
|
||||
DEF_FIXED("mp", R8A7792_CLK_MP, CLK_PLL1_DIV2, 15, 1),
|
||||
DEF_FIXED("cp", R8A7792_CLK_CP, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cpex", R8A7792_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("rcan", R8A7792_CLK_RCAN, CLK_PLL1_DIV2, 49, 1),
|
||||
DEF_FIXED("r", R8A7792_CLK_R, CLK_PLL1, 49152, 1),
|
||||
DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7792_mod_clks[] = {
|
||||
DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
|
||||
DEF_MOD("jpu", 106, R8A7792_CLK_M2),
|
||||
DEF_MOD("tmu1", 111, R8A7792_CLK_P),
|
||||
DEF_MOD("3dg", 112, R8A7792_CLK_ZG),
|
||||
DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS),
|
||||
DEF_MOD("tmu3", 121, R8A7792_CLK_P),
|
||||
DEF_MOD("tmu2", 122, R8A7792_CLK_P),
|
||||
DEF_MOD("cmt0", 124, R8A7792_CLK_R),
|
||||
DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
|
||||
DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
|
||||
DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
|
||||
DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
|
||||
DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
|
||||
DEF_MOD("tpu0", 304, R8A7792_CLK_CP),
|
||||
DEF_MOD("sdhi0", 314, R8A7792_CLK_SD),
|
||||
DEF_MOD("cmt1", 329, R8A7792_CLK_R),
|
||||
DEF_MOD("rwdt", 402, R8A7792_CLK_R),
|
||||
DEF_MOD("irqc", 407, R8A7792_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP),
|
||||
DEF_MOD("thermal", 522, CLK_EXTAL),
|
||||
DEF_MOD("pwm", 523, R8A7792_CLK_P),
|
||||
DEF_MOD("hscif1", 716, R8A7792_CLK_ZS),
|
||||
DEF_MOD("hscif0", 717, R8A7792_CLK_ZS),
|
||||
DEF_MOD("scif3", 718, R8A7792_CLK_P),
|
||||
DEF_MOD("scif2", 719, R8A7792_CLK_P),
|
||||
DEF_MOD("scif1", 720, R8A7792_CLK_P),
|
||||
DEF_MOD("scif0", 721, R8A7792_CLK_P),
|
||||
DEF_MOD("du1", 723, R8A7792_CLK_ZX),
|
||||
DEF_MOD("du0", 724, R8A7792_CLK_ZX),
|
||||
DEF_MOD("vin5", 804, R8A7792_CLK_ZG),
|
||||
DEF_MOD("vin4", 805, R8A7792_CLK_ZG),
|
||||
DEF_MOD("vin3", 808, R8A7792_CLK_ZG),
|
||||
DEF_MOD("vin2", 809, R8A7792_CLK_ZG),
|
||||
DEF_MOD("vin1", 810, R8A7792_CLK_ZG),
|
||||
DEF_MOD("vin0", 811, R8A7792_CLK_ZG),
|
||||
DEF_MOD("etheravb", 812, R8A7792_CLK_HP),
|
||||
DEF_MOD("imr-lx3", 821, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-1", 822, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-0", 823, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-5", 825, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-4", 826, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-3", 827, R8A7792_CLK_ZG),
|
||||
DEF_MOD("imr-lsx3-2", 828, R8A7792_CLK_ZG),
|
||||
DEF_MOD("gyro-adc", 901, R8A7792_CLK_P),
|
||||
DEF_MOD("gpio7", 904, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio6", 905, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio5", 907, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio11", 913, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio10", 914, R8A7792_CLK_CP),
|
||||
DEF_MOD("can1", 915, R8A7792_CLK_P),
|
||||
DEF_MOD("can0", 916, R8A7792_CLK_P),
|
||||
DEF_MOD("qspi_mod", 917, R8A7792_CLK_QSPI),
|
||||
DEF_MOD("gpio9", 919, R8A7792_CLK_CP),
|
||||
DEF_MOD("gpio8", 921, R8A7792_CLK_CP),
|
||||
DEF_MOD("i2c5", 925, R8A7792_CLK_HP),
|
||||
DEF_MOD("iicdvfs", 926, R8A7792_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A7792_CLK_HP),
|
||||
DEF_MOD("i2c3", 928, R8A7792_CLK_HP),
|
||||
DEF_MOD("i2c2", 929, R8A7792_CLK_HP),
|
||||
DEF_MOD("i2c1", 930, R8A7792_CLK_HP),
|
||||
DEF_MOD("i2c0", 931, R8A7792_CLK_HP),
|
||||
DEF_MOD("ssi-all", 1005, R8A7792_CLK_P),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *2
|
||||
*---------------------------------------------------
|
||||
* 0 0 0 15 x200/3 x208/2 x106
|
||||
* 0 0 1 15 x200/3 x208/2 x88
|
||||
* 0 1 0 20 x150/3 x156/2 x80
|
||||
* 0 1 1 20 x150/3 x156/2 x66
|
||||
* 1 0 0 26 / 2 x230/3 x240/2 x122
|
||||
* 1 0 1 26 / 2 x230/3 x240/2 x102
|
||||
* 1 1 0 30 / 2 x200/3 x208/2 x106
|
||||
* 1 1 1 30 / 2 x200/3 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
|
||||
* *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
|
||||
{ 1, 208, 106, 200 },
|
||||
{ 1, 208, 88, 200 },
|
||||
{ 1, 156, 80, 150 },
|
||||
{ 1, 156, 66, 150 },
|
||||
{ 2, 240, 122, 230 },
|
||||
{ 2, 240, 102, 230 },
|
||||
{ 2, 208, 106, 200 },
|
||||
{ 2, 208, 88, 200 },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7792_mstp_table[] = {
|
||||
{ 0x00400801, 0x400000, 0x00400801, 0x0 },
|
||||
{ 0x9B6F987F, 0x0, 0x9B6F987F, 0x0 },
|
||||
{ 0x108CE100, 0x0, 0x108CE100, 0x80000 },
|
||||
{ 0x20004010, 0x4000, 0x20004010, 0x0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0x0 },
|
||||
{ 0x44C00004, 0x0, 0x44C00004, 0x0 },
|
||||
{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
|
||||
{ 0x01BF0000, 0x200000, 0x01BF0000, 0x0 },
|
||||
{ 0x1FE01FB0, 0x0, 0x1FE01FB0, 0x0 },
|
||||
{ 0xFE2BFFB2, 0x20000, 0xFE2BFFB2, 0x0 },
|
||||
{ 0x00001820, 0x0, 0x00001820, 0x0 },
|
||||
{ 0x00000008, 0x0, 0x00000008, 0x0 },
|
||||
};
|
||||
|
||||
static const void *r8a7792_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7792_cpg_mssr_info = {
|
||||
.core_clk = r8a7792_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7792_core_clks),
|
||||
.mod_clk = r8a7792_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7792_mod_clks),
|
||||
.mstp_table = r8a7792_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7792_mstp_table),
|
||||
.reset_node = "renesas,r8a7792-rst",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.pll0_div = 2,
|
||||
.get_pll_config = r8a7792_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7792_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7792-cpg-mssr",
|
||||
.data = (ulong)&r8a7792_cpg_mssr_info
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,r8a7793-cpg-mssr",
|
||||
.data = (ulong)&r8a7792_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7792) = {
|
||||
.name = "clk_r8a7792",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7792_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
|
||||
.ops = &gen2_clk_ops,
|
||||
.probe = gen2_clk_probe,
|
||||
.remove = gen2_clk_remove,
|
||||
};
|
||||
@@ -0,0 +1,270 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a7794 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen2.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7794_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_USB_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7794_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
DEF_BASE("qspi", R8A7794_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
DEF_BASE("rcan", R8A7794_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
|
||||
|
||||
DEF_FIXED("z2", R8A7794_CLK_Z2, CLK_PLL0, 1, 1),
|
||||
DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("lb", R8A7794_CLK_LB, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7794_CLK_M2, CLK_PLL1, 8, 1),
|
||||
DEF_FIXED("zb3", R8A7794_CLK_ZB3, CLK_PLL3, 4, 1),
|
||||
DEF_FIXED("zb3d2", R8A7794_CLK_ZB3D2, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("ddr", R8A7794_CLK_DDR, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("mp", R8A7794_CLK_MP, CLK_PLL1_DIV2, 15, 1),
|
||||
DEF_FIXED("cpex", R8A7794_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("r", R8A7794_CLK_R, CLK_PLL1, 49152, 1),
|
||||
DEF_FIXED("osc", R8A7794_CLK_OSC, CLK_PLL1, 12288, 1),
|
||||
|
||||
DEF_DIV6P1("sd2", R8A7794_CLK_SD2, CLK_PLL1_DIV2, 0x078),
|
||||
DEF_DIV6P1("sd3", R8A7794_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
|
||||
DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7794_mod_clks[] = {
|
||||
DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
|
||||
DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
|
||||
DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
|
||||
DEF_MOD("jpu", 106, R8A7794_CLK_M2),
|
||||
DEF_MOD("tmu1", 111, R8A7794_CLK_P),
|
||||
DEF_MOD("3dg", 112, R8A7794_CLK_ZG),
|
||||
DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS),
|
||||
DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS),
|
||||
DEF_MOD("tmu3", 121, R8A7794_CLK_P),
|
||||
DEF_MOD("tmu2", 122, R8A7794_CLK_P),
|
||||
DEF_MOD("cmt0", 124, R8A7794_CLK_R),
|
||||
DEF_MOD("tmu0", 125, R8A7794_CLK_CP),
|
||||
DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS),
|
||||
DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS),
|
||||
DEF_MOD("scifa2", 202, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifa1", 203, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifa0", 204, R8A7794_CLK_MP),
|
||||
DEF_MOD("msiof2", 205, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifb0", 206, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifb1", 207, R8A7794_CLK_MP),
|
||||
DEF_MOD("msiof1", 208, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifb2", 216, R8A7794_CLK_MP),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS),
|
||||
DEF_MOD("tpu0", 304, R8A7794_CLK_CP),
|
||||
DEF_MOD("sdhi3", 311, R8A7794_CLK_SD3),
|
||||
DEF_MOD("sdhi2", 312, R8A7794_CLK_SD2),
|
||||
DEF_MOD("sdhi0", 314, R8A7794_CLK_SD0),
|
||||
DEF_MOD("mmcif0", 315, R8A7794_CLK_MMC0),
|
||||
DEF_MOD("iic0", 318, R8A7794_CLK_HP),
|
||||
DEF_MOD("iic1", 323, R8A7794_CLK_HP),
|
||||
DEF_MOD("cmt1", 329, R8A7794_CLK_R),
|
||||
DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP),
|
||||
DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP),
|
||||
DEF_MOD("rwdt", 402, R8A7794_CLK_R),
|
||||
DEF_MOD("irqc", 407, R8A7794_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP),
|
||||
DEF_MOD("adsp_mod", 506, R8A7794_CLK_ADSP),
|
||||
DEF_MOD("pwm", 523, R8A7794_CLK_P),
|
||||
DEF_MOD("usb-ehci", 703, R8A7794_CLK_MP),
|
||||
DEF_MOD("usbhs", 704, R8A7794_CLK_HP),
|
||||
DEF_MOD("hscif2", 713, R8A7794_CLK_ZS),
|
||||
DEF_MOD("scif5", 714, R8A7794_CLK_P),
|
||||
DEF_MOD("scif4", 715, R8A7794_CLK_P),
|
||||
DEF_MOD("hscif1", 716, R8A7794_CLK_ZS),
|
||||
DEF_MOD("hscif0", 717, R8A7794_CLK_ZS),
|
||||
DEF_MOD("scif3", 718, R8A7794_CLK_P),
|
||||
DEF_MOD("scif2", 719, R8A7794_CLK_P),
|
||||
DEF_MOD("scif1", 720, R8A7794_CLK_P),
|
||||
DEF_MOD("scif0", 721, R8A7794_CLK_P),
|
||||
DEF_MOD("du1", 723, R8A7794_CLK_ZX),
|
||||
DEF_MOD("du0", 724, R8A7794_CLK_ZX),
|
||||
DEF_MOD("ipmmu-sgx", 800, R8A7794_CLK_ZX),
|
||||
DEF_MOD("mlb", 802, R8A7794_CLK_HP),
|
||||
DEF_MOD("vin1", 810, R8A7794_CLK_ZG),
|
||||
DEF_MOD("vin0", 811, R8A7794_CLK_ZG),
|
||||
DEF_MOD("etheravb", 812, R8A7794_CLK_HP),
|
||||
DEF_MOD("ether", 813, R8A7794_CLK_P),
|
||||
DEF_MOD("gyro-adc", 901, R8A7794_CLK_P),
|
||||
DEF_MOD("gpio6", 905, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio5", 907, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A7794_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A7794_CLK_CP),
|
||||
DEF_MOD("can1", 915, R8A7794_CLK_P),
|
||||
DEF_MOD("can0", 916, R8A7794_CLK_P),
|
||||
DEF_MOD("qspi_mod", 917, R8A7794_CLK_QSPI),
|
||||
DEF_MOD("i2c5", 925, R8A7794_CLK_HP),
|
||||
DEF_MOD("i2c4", 927, R8A7794_CLK_HP),
|
||||
DEF_MOD("i2c3", 928, R8A7794_CLK_HP),
|
||||
DEF_MOD("i2c2", 929, R8A7794_CLK_HP),
|
||||
DEF_MOD("i2c1", 930, R8A7794_CLK_HP),
|
||||
DEF_MOD("i2c0", 931, R8A7794_CLK_HP),
|
||||
DEF_MOD("ssi-all", 1005, R8A7794_CLK_P),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7794_CLK_P),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scifa3", 1106, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifa4", 1107, R8A7794_CLK_MP),
|
||||
DEF_MOD("scifa5", 1108, R8A7794_CLK_MP),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *2
|
||||
*---------------------------------------------------
|
||||
* 0 0 1 15 x200/3 x208/2 x88
|
||||
* 0 1 1 20 x150/3 x156/2 x66
|
||||
* 1 0 1 26 / 2 x230/3 x240/2 x102
|
||||
* 1 1 1 30 / 2 x200/3 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3)
|
||||
* *2 : Table 7.5c indicates VCO output (PLL1 = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
|
||||
(((md) & BIT(13)) >> 13))
|
||||
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = {
|
||||
{ 1, 208, 88, 200 },
|
||||
{ 1, 156, 66, 150 },
|
||||
{ 2, 240, 102, 230 },
|
||||
{ 2, 208, 88, 200 },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7794_mstp_table[] = {
|
||||
{ 0x00440801, 0x400000, 0x00440801, 0x0 },
|
||||
{ 0x936899DA, 0x0, 0x936899DA, 0x0 },
|
||||
{ 0x100D21FC, 0x2000, 0x100D21FC, 0x0 },
|
||||
{ 0xE084D810, 0x0, 0xE084D810, 0x0 },
|
||||
{ 0x800001C4, 0x180, 0x800001C4, 0x0 },
|
||||
{ 0x40C00044, 0x0, 0x40C00044, 0x0 },
|
||||
{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
|
||||
{ 0x013FE618, 0x80000, 0x013FE618, 0x0 },
|
||||
{ 0x40803C05, 0x0, 0x40803C05, 0x0 },
|
||||
{ 0xFB879FEE, 0x0, 0xFB879FEE, 0x0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
|
||||
{ 0x000001C0, 0x0, 0x000001C0, 0x0 },
|
||||
};
|
||||
|
||||
static const void *r8a7794_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7794_cpg_mssr_info = {
|
||||
.core_clk = r8a7794_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7794_core_clks),
|
||||
.mod_clk = r8a7794_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7794_mod_clks),
|
||||
.mstp_table = r8a7794_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7794_mstp_table),
|
||||
.reset_node = "renesas,r8a7794-rst",
|
||||
.extal_usb_node = "usb_extal",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extal_usb_id = CLK_USB_EXTAL,
|
||||
.pll0_div = 2,
|
||||
.get_pll_config = r8a7794_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7794_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7794-cpg-mssr",
|
||||
.data = (ulong)&r8a7794_cpg_mssr_info
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,r8a7793-cpg-mssr",
|
||||
.data = (ulong)&r8a7794_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7794) = {
|
||||
.name = "clk_r8a7794",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7794_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
|
||||
.ops = &gen2_clk_ops,
|
||||
.probe = gen2_clk_probe,
|
||||
.remove = gen2_clk_remove,
|
||||
};
|
||||
@@ -0,0 +1,379 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen3.c
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7795_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
|
||||
DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
|
||||
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
|
||||
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7795_mod_clks[] = {
|
||||
DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
|
||||
DEF_MOD("cmt3", 300, R8A7795_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A7795_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A7795_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A7795_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
|
||||
DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
|
||||
DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
|
||||
DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A7795_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("thermal", 522, R8A7795_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
|
||||
DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
|
||||
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
|
||||
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
|
||||
DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
|
||||
DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
|
||||
DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
|
||||
DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
|
||||
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7795_mstp_table[] = {
|
||||
{ 0x00640800, 0x0, 0x00640800, 0 },
|
||||
{ 0xF3EE9390, 0x0, 0xF3EE9390, 0 },
|
||||
{ 0x340FAFDC, 0x2040, 0x340FAFDC, 0 },
|
||||
{ 0xD80C7CDF, 0x400, 0xD80C7CDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0x40BFFF46, 0x0, 0x40BFFF46, 0 },
|
||||
{ 0xE5FBEECF, 0x0, 0xE5FBEECF, 0 },
|
||||
{ 0x39FFFF0E, 0x0, 0x39FFFF0E, 0 },
|
||||
{ 0x01F19FF4, 0x0, 0x01F19FF4, 0 },
|
||||
{ 0xFFDFFFFF, 0x0, 0xFFDFFFFF, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x00000000, 0x0, 0x00000000, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a7795_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7795_cpg_mssr_info = {
|
||||
.core_clk = r8a7795_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7795_core_clks),
|
||||
.mod_clk = r8a7795_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks),
|
||||
.mstp_table = r8a7795_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table),
|
||||
.reset_node = "renesas,r8a7795-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a7795_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7795_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7795-cpg-mssr",
|
||||
.data = (ulong)&r8a7795_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7795) = {
|
||||
.name = "clk_r8a7795",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7795_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
@@ -0,0 +1,357 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R8A7796 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7796_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
|
||||
DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
|
||||
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7796_mod_clks[] = {
|
||||
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A7796_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("cmt3", 300, R8A7796_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A7796_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A7796_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A7796_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
|
||||
DEF_MOD("sdif1", 313, R8A7796_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
|
||||
DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A7796_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("thermal", 522, R8A7796_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A7796_CLK_S0D12),
|
||||
DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
|
||||
DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
|
||||
DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("imr1", 822, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("imr0", 823, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
|
||||
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7796_mstp_table[] = {
|
||||
{ 0x00200000, 0x0, 0x00200000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
|
||||
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a7796_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
|
||||
.core_clk = r8a7796_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7796_core_clks),
|
||||
.mod_clk = r8a7796_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks),
|
||||
.mstp_table = r8a7796_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table),
|
||||
.reset_node = "renesas,r8a7796-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a7796_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7796_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7796-cpg-mssr",
|
||||
.data = (ulong)&r8a7796_cpg_mssr_info,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7796) = {
|
||||
.name = "clk_r8a7796",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7796_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
@@ -0,0 +1,355 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a77965 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a77965-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77965_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a77965_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
|
||||
DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A77965_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A77965_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A77965_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A77965_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A77965_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A77965_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A77965_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A77965_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d1", R8A77965_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A77965_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A77965_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A77965_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A77965_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A77965_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A77965_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_GEN3_RPC("rpc", R8A77965_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77965_mod_clks[] = {
|
||||
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A77965_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
|
||||
|
||||
DEF_MOD("cmt3", 300, R8A77965_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77965_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77965_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A77965_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A77965_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A77965_CLK_SD2),
|
||||
DEF_MOD("sdif1", 313, R8A77965_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A77965_CLK_SD0),
|
||||
DEF_MOD("pcie1", 318, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A77965_CLK_S3D1),
|
||||
|
||||
DEF_MOD("rwdt", 402, R8A77965_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
|
||||
|
||||
DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3),
|
||||
DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3),
|
||||
DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif4", 511, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif3", 512, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif2", 513, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif1", 514, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif0", 515, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("thermal", 522, R8A77965_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A77965_CLK_S0D12),
|
||||
|
||||
DEF_MOD("fcpvd1", 602, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("fcpvb0", 607, R8A77965_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A77965_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A77965_CLK_S0D1),
|
||||
DEF_MOD("fcpcs", 619, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vspd1", 622, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
|
||||
|
||||
DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
|
||||
DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI),
|
||||
|
||||
DEF_MOD("vin7", 804, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("sata0", 815, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("imr1", 822, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("imr0", 823, R8A77965_CLK_S0D2),
|
||||
|
||||
DEF_MOD("gpio7", 905, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A77965_CLK_RPC),
|
||||
DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A77965_CLK_S3D2),
|
||||
|
||||
DEF_MOD("ssi-all", 1005, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-----------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a77965_mstp_table[] = {
|
||||
{ 0x00200000, 0x0, 0x00200000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
|
||||
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a77965_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a77965_cpg_mssr_info = {
|
||||
.core_clk = r8a77965_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a77965_core_clks),
|
||||
.mod_clk = r8a77965_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a77965_mod_clks),
|
||||
.mstp_table = r8a77965_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a77965_mstp_table),
|
||||
.reset_node = "renesas,r8a77965-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a77965_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77965_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77965-cpg-mssr",
|
||||
.data = (ulong)&r8a77965_cpg_mssr_info,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77965) = {
|
||||
.name = "clk_r8a77965",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77965_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
@@ -0,0 +1,232 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Renesas R8A77970 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_PLL0D2,
|
||||
CLK_PLL0D3,
|
||||
CLK_PLL0D5,
|
||||
CLK_PLL1D2,
|
||||
CLK_PE,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a77970_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
|
||||
DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
|
||||
|
||||
DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
||||
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
|
||||
|
||||
DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77970_mod_clks[] = {
|
||||
DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
|
||||
DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
|
||||
DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
|
||||
DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
|
||||
DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
|
||||
DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
|
||||
DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
|
||||
DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
|
||||
DEF_MOD("thermal", 522, R8A77970_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
|
||||
DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
|
||||
DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
|
||||
DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
|
||||
DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz)
|
||||
*-------------------------------------------------
|
||||
* 0 0 0 16.66 x 1 x192 x192 x96
|
||||
* 0 0 1 16.66 x 1 x192 x192 x80
|
||||
* 0 1 0 20 x 1 x160 x160 x80
|
||||
* 0 1 1 20 x 1 x160 x160 x66
|
||||
* 1 0 0 27 / 2 x236 x236 x118
|
||||
* 1 0 1 27 / 2 x236 x236 x98
|
||||
* 1 1 0 33.33 / 2 x192 x192 x96
|
||||
* 1 1 1 33.33 / 2 x192 x192 x80
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 192, 1, 96, 1, },
|
||||
{ 1, 192, 1, 80, 1, },
|
||||
{ 1, 160, 1, 80, 1, },
|
||||
{ 1, 160, 1, 66, 1, },
|
||||
{ 2, 236, 1, 118, 1, },
|
||||
{ 2, 236, 1, 98, 1, },
|
||||
{ 2, 192, 1, 96, 1, },
|
||||
{ 2, 192, 1, 80, 1, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a77970_mstp_table[] = {
|
||||
{ 0x00230000, 0x0, 0x00230000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x14062FD8, 0x2040, 0x14062FD8, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 },
|
||||
{ 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a77970_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
|
||||
.core_clk = r8a77970_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a77970_core_clks),
|
||||
.mod_clk = r8a77970_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks),
|
||||
.mstp_table = r8a77970_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table),
|
||||
.reset_node = "renesas,r8a77970-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a77970_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77970_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77970-cpg-mssr",
|
||||
.data = (ulong)&r8a77970_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77970) = {
|
||||
.name = "clk_r8a77970",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77970_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
@@ -0,0 +1,255 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a77980 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a77980_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
DEF_RATE(".oco", CLK_OCO, 32768),
|
||||
|
||||
DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A77980_CLK_RPC),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1),
|
||||
DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074),
|
||||
|
||||
DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
|
||||
DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77980_mod_clks[] = {
|
||||
DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
|
||||
DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A77980_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A77980_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("cmt3", 300, R8A77980_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77980_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77980_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A77980_CLK_R),
|
||||
DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
|
||||
DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
|
||||
DEF_MOD("rwdt", 402, R8A77980_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("imp4", 521, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("thermal", 522, R8A77980_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A77980_CLK_S0D12),
|
||||
DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
|
||||
DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp2", 825, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp1", 826, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp0", 827, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("impram", 830, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("gpio5", 907, R8A77980_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A77980_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A77980_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A77980_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
|
||||
DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2),
|
||||
DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL2 PLL1 PLL3 OSC
|
||||
* 14 13 (MHz)
|
||||
* --------------------------------------------------------
|
||||
* 0 0 16.66 x 1 x240 x192 x192 /16
|
||||
* 0 1 20 x 1 x200 x160 x160 /19
|
||||
* 1 0 27 x 1 x148 x118 x118 /26
|
||||
* 1 1 33.33 / 2 x240 x192 x192 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
|
||||
(((md) & BIT(13)) >> 13))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 118, 1, 118, 1, 26, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a77980_mstp_table[] = {
|
||||
{ 0x00230000, 0x0, 0x00230000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x14062FD8, 0x2040, 0x14062FD8, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 },
|
||||
{ 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a77980_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a77980_cpg_mssr_info = {
|
||||
.core_clk = r8a77980_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a77980_core_clks),
|
||||
.mod_clk = r8a77980_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a77980_mod_clks),
|
||||
.mstp_table = r8a77980_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a77980_mstp_table),
|
||||
.reset_node = "renesas,r8a77980-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a77980_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77980_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77980-cpg-mssr",
|
||||
.data = (ulong)&r8a77980_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77980) = {
|
||||
.name = "clk_r8a77980",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77980_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
@@ -0,0 +1,314 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a77990 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL0D4,
|
||||
CLK_PLL0D6,
|
||||
CLK_PLL0D8,
|
||||
CLK_PLL0D20,
|
||||
CLK_PLL0D24,
|
||||
CLK_PLL1D2,
|
||||
CLK_PE,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a77990_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
|
||||
DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
|
||||
DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
|
||||
DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
|
||||
DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
|
||||
DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
|
||||
DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
|
||||
DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
|
||||
DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("s0d1", R8A77990_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d3", R8A77990_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d6", R8A77990_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d12", R8A77990_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s0d24", R8A77990_CLK_S0D24, CLK_S0, 24, 1),
|
||||
DEF_FIXED("s1d1", R8A77990_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A77990_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A77990_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A77990_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A77990_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A77990_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A77990_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074),
|
||||
DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
|
||||
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
|
||||
|
||||
DEF_GEN3_RPC("rpc", R8A77990_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A77990_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
|
||||
DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
|
||||
DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
|
||||
|
||||
DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77990_mod_clks[] = {
|
||||
DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("msiof3", 208, R8A77990_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A77990_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A77990_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A77990_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
|
||||
|
||||
DEF_MOD("cmt3", 300, R8A77990_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77990_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77990_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A77990_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A77990_CLK_S3D4C),
|
||||
DEF_MOD("sdif3", 311, R8A77990_CLK_SD3),
|
||||
DEF_MOD("sdif1", 313, R8A77990_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A77990_CLK_SD0),
|
||||
DEF_MOD("pcie0", 319, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A77990_CLK_S3D1),
|
||||
|
||||
DEF_MOD("rwdt", 402, R8A77990_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
|
||||
|
||||
DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
|
||||
DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
|
||||
DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
|
||||
DEF_MOD("hscif1", 519, R8A77990_CLK_S3D1C),
|
||||
DEF_MOD("hscif0", 520, R8A77990_CLK_S3D1C),
|
||||
DEF_MOD("thermal", 522, R8A77990_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A77990_CLK_S3D4C),
|
||||
|
||||
DEF_MOD("fcpvd1", 602, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("fcpvb0", 607, R8A77990_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A77990_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A77990_CLK_S0D1),
|
||||
DEF_MOD("fcpcs", 619, R8A77990_CLK_S0D1),
|
||||
DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("vspd0", 623, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
|
||||
|
||||
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
|
||||
DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
|
||||
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
|
||||
|
||||
DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
|
||||
|
||||
DEF_MOD("gpio6", 906, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A77990_CLK_RPC),
|
||||
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c2", 929, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
|
||||
|
||||
DEF_MOD("i2c7", 1003, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
|
||||
*--------------------------------------------------------------------
|
||||
* 0 48 x 1 x100/1 x100/3 x100/3
|
||||
* 1 48 x 1 x100/1 x100/3 x58/3
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 100, 3, 100, 3, },
|
||||
{ 1, 100, 3, 58, 3, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a77990_mstp_table[] = {
|
||||
{ 0x00200000, 0x0, 0x00200000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
|
||||
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a77990_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a77990_cpg_mssr_info = {
|
||||
.core_clk = r8a77990_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a77990_core_clks),
|
||||
.mod_clk = r8a77990_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a77990_mod_clks),
|
||||
.mstp_table = r8a77990_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a77990_mstp_table),
|
||||
.reset_node = "renesas,r8a77990-rst",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = ~0,
|
||||
.get_pll_config = r8a77990_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77990_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77990-cpg-mssr",
|
||||
.data = (ulong)&r8a77990_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77990) = {
|
||||
.name = "clk_r8a77990",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77990_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
@@ -0,0 +1,253 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a77995 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL0D2,
|
||||
CLK_PLL0D3,
|
||||
CLK_PLL0D5,
|
||||
CLK_PLL1D2,
|
||||
CLK_PE,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a77995_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
|
||||
DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
|
||||
DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
|
||||
DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
|
||||
DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
|
||||
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
|
||||
DEF_GEN3_RPC("rpc", R8A77995_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
|
||||
DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
|
||||
DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
|
||||
|
||||
DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77995_mod_clks[] = {
|
||||
DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("cmt3", 300, R8A77995_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77995_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77995_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A77995_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
|
||||
DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A77995_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
|
||||
DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
|
||||
DEF_MOD("thermal", 522, R8A77995_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
|
||||
DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
|
||||
DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
|
||||
DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A77995_CLK_RPC),
|
||||
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
|
||||
*--------------------------------------------------------------------
|
||||
* 0 48 x 1 x250/4 x100/3 x100/3
|
||||
* 1 48 x 1 x250/4 x100/3 x58/3
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 100, 3, 100, 3, },
|
||||
{ 1, 100, 3, 58, 3, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a77995_mstp_table[] = {
|
||||
{ 0x00200000, 0x0, 0x00200000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
|
||||
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a77995_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
|
||||
.core_clk = r8a77995_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a77995_core_clks),
|
||||
.mod_clk = r8a77995_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks),
|
||||
.mstp_table = r8a77995_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table),
|
||||
.reset_node = "renesas,r8a77995-rst",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = ~0,
|
||||
.get_pll_config = r8a77995_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77995_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77995-cpg-mssr",
|
||||
.data = (ulong)&r8a77995_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77995) = {
|
||||
.name = "clk_r8a77995",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77995_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* R-Car Gen2 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
|
||||
#define __CLK_RENESAS_RCAR_GEN2_CPG_H__
|
||||
|
||||
enum rcar_gen2_clk_types {
|
||||
CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM,
|
||||
CLK_TYPE_GEN2_PLL0,
|
||||
CLK_TYPE_GEN2_PLL1,
|
||||
CLK_TYPE_GEN2_PLL3,
|
||||
CLK_TYPE_GEN2_Z,
|
||||
CLK_TYPE_GEN2_LB,
|
||||
CLK_TYPE_GEN2_ADSP,
|
||||
CLK_TYPE_GEN2_SDH,
|
||||
CLK_TYPE_GEN2_SD0,
|
||||
CLK_TYPE_GEN2_SD1,
|
||||
CLK_TYPE_GEN2_QSPI,
|
||||
CLK_TYPE_GEN2_RCAN,
|
||||
};
|
||||
|
||||
struct rcar_gen2_cpg_pll_config {
|
||||
unsigned int extal_div;
|
||||
unsigned int pll1_mult;
|
||||
unsigned int pll3_mult;
|
||||
unsigned int pll0_mult; /* leave as zero if PLL0CR exists */
|
||||
};
|
||||
|
||||
struct gen2_clk_priv {
|
||||
void __iomem *base;
|
||||
struct cpg_mssr_info *info;
|
||||
struct clk clk_extal;
|
||||
struct clk clk_extal_usb;
|
||||
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
|
||||
};
|
||||
|
||||
int gen2_clk_probe(struct udevice *dev);
|
||||
int gen2_clk_remove(struct udevice *dev);
|
||||
|
||||
extern const struct clk_ops gen2_clk_ops;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,86 @@
|
||||
/*
|
||||
* R-Car Gen3 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2015-2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
||||
#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
||||
|
||||
enum rcar_gen3_clk_types {
|
||||
CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
|
||||
CLK_TYPE_GEN3_PLL0,
|
||||
CLK_TYPE_GEN3_PLL1,
|
||||
CLK_TYPE_GEN3_PLL2,
|
||||
CLK_TYPE_GEN3_PLL3,
|
||||
CLK_TYPE_GEN3_PLL4,
|
||||
CLK_TYPE_GEN3_SD,
|
||||
CLK_TYPE_GEN3_R,
|
||||
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
|
||||
CLK_TYPE_GEN3_Z,
|
||||
CLK_TYPE_GEN3_Z2,
|
||||
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
|
||||
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
|
||||
CLK_TYPE_GEN3_RPCSRC,
|
||||
CLK_TYPE_GEN3_RPC,
|
||||
CLK_TYPE_GEN3_RPCD2,
|
||||
|
||||
/* SoC specific definitions start here */
|
||||
CLK_TYPE_GEN3_SOC_BASE,
|
||||
};
|
||||
|
||||
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
|
||||
(_parent0) << 16 | (_parent1), \
|
||||
.div = (_div0) << 16 | (_div1), .offset = _md)
|
||||
|
||||
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
|
||||
_div_clean) \
|
||||
DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
|
||||
_parent_clean, _div_clean)
|
||||
|
||||
#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
|
||||
|
||||
#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
|
||||
(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
|
||||
|
||||
|
||||
struct rcar_gen3_cpg_pll_config {
|
||||
u8 extal_div;
|
||||
u8 pll1_mult;
|
||||
u8 pll1_div;
|
||||
u8 pll3_mult;
|
||||
u8 pll3_div;
|
||||
u8 osc_prediv;
|
||||
};
|
||||
|
||||
#define CPG_RPCCKCR 0x238
|
||||
#define CPG_RCKCR 0x240
|
||||
|
||||
struct gen3_clk_priv {
|
||||
void __iomem *base;
|
||||
struct cpg_mssr_info *info;
|
||||
struct clk clk_extal;
|
||||
struct clk clk_extalr;
|
||||
bool sscg;
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
};
|
||||
|
||||
int gen3_clk_probe(struct udevice *dev);
|
||||
int gen3_clk_remove(struct udevice *dev);
|
||||
|
||||
extern const struct clk_ops gen3_clk_ops;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,174 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Renesas RCar Gen3 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <wait_bit.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
|
||||
/*
|
||||
* Module Standby and Software Reset register offets.
|
||||
*
|
||||
* If the registers exist, these are valid for SH-Mobile, R-Mobile,
|
||||
* R-Car Gen2, R-Car Gen3, and RZ/G1.
|
||||
* These are NOT valid for R-Car Gen1 and RZ/A1!
|
||||
*/
|
||||
|
||||
/*
|
||||
* Module Stop Status Register offsets
|
||||
*/
|
||||
|
||||
static const u16 mstpsr[] = {
|
||||
0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
|
||||
0x9A0, 0x9A4, 0x9A8, 0x9AC,
|
||||
};
|
||||
|
||||
#define MSTPSR(i) mstpsr[i]
|
||||
|
||||
|
||||
/*
|
||||
* System Module Stop Control Register offsets
|
||||
*/
|
||||
|
||||
static const u16 smstpcr[] = {
|
||||
0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
|
||||
0x990, 0x994, 0x998, 0x99C,
|
||||
};
|
||||
|
||||
#define SMSTPCR(i) smstpcr[i]
|
||||
|
||||
|
||||
/* Realtime Module Stop Control Register offsets */
|
||||
#define RMSTPCR(i) (smstpcr[i] - 0x20)
|
||||
|
||||
/* Modem Module Stop Control Register offsets (r8a73a4) */
|
||||
#define MMSTPCR(i) (smstpcr[i] + 0x20)
|
||||
|
||||
/* Software Reset Clearing Register offsets */
|
||||
#define SRSTCLR(i) (0x940 + (i) * 4)
|
||||
|
||||
bool renesas_clk_is_mod(struct clk *clk)
|
||||
{
|
||||
return (clk->id >> 16) == CPG_MOD;
|
||||
}
|
||||
|
||||
int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
|
||||
const struct mssr_mod_clk **mssr)
|
||||
{
|
||||
const unsigned long clkid = clk->id & 0xffff;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < info->mod_clk_size; i++) {
|
||||
if (info->mod_clk[i].id !=
|
||||
(info->mod_clk_base + MOD_CLK_PACK(clkid)))
|
||||
continue;
|
||||
|
||||
*mssr = &info->mod_clk[i];
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
|
||||
const struct cpg_core_clk **core)
|
||||
{
|
||||
const unsigned long clkid = clk->id & 0xffff;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < info->core_clk_size; i++) {
|
||||
if (info->core_clk[i].id != clkid)
|
||||
continue;
|
||||
|
||||
*core = &info->core_clk[i];
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
|
||||
struct clk *parent)
|
||||
{
|
||||
const struct cpg_core_clk *core;
|
||||
const struct mssr_mod_clk *mssr;
|
||||
int ret;
|
||||
|
||||
if (renesas_clk_is_mod(clk)) {
|
||||
ret = renesas_clk_get_mod(clk, info, &mssr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
parent->id = mssr->parent;
|
||||
} else {
|
||||
ret = renesas_clk_get_core(clk, info, &core);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (core->type == CLK_TYPE_IN)
|
||||
parent->id = ~0; /* Top-level clock */
|
||||
else
|
||||
parent->id = core->parent;
|
||||
}
|
||||
|
||||
parent->dev = clk->dev;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
|
||||
{
|
||||
const unsigned long clkid = clk->id & 0xffff;
|
||||
const unsigned int reg = clkid / 100;
|
||||
const unsigned int bit = clkid % 100;
|
||||
const u32 bitmask = BIT(bit);
|
||||
|
||||
if (!renesas_clk_is_mod(clk))
|
||||
return -EINVAL;
|
||||
|
||||
debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
|
||||
clkid, reg, bit, enable ? "ON" : "OFF");
|
||||
|
||||
if (enable) {
|
||||
clrbits_le32(base + SMSTPCR(reg), bitmask);
|
||||
return wait_for_bit_le32(base + MSTPSR(reg),
|
||||
bitmask, 0, 100, 0);
|
||||
} else {
|
||||
setbits_le32(base + SMSTPCR(reg), bitmask);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/* Stop TMU0 */
|
||||
clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
|
||||
|
||||
/* Stop module clock */
|
||||
for (i = 0; i < info->mstp_table_size; i++) {
|
||||
clrsetbits_le32(base + SMSTPCR(i),
|
||||
info->mstp_table[i].sdis,
|
||||
info->mstp_table[i].sen);
|
||||
clrsetbits_le32(base + RMSTPCR(i),
|
||||
info->mstp_table[i].rdis,
|
||||
info->mstp_table[i].ren);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,119 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Renesas RCar Gen3 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
|
||||
#define __DRIVERS_CLK_RENESAS_CPG_MSSR__
|
||||
|
||||
struct cpg_mssr_info {
|
||||
const struct cpg_core_clk *core_clk;
|
||||
unsigned int core_clk_size;
|
||||
const struct mssr_mod_clk *mod_clk;
|
||||
unsigned int mod_clk_size;
|
||||
const struct mstp_stop_table *mstp_table;
|
||||
unsigned int mstp_table_size;
|
||||
const char *reset_node;
|
||||
const char *extalr_node;
|
||||
const char *extal_usb_node;
|
||||
unsigned int mod_clk_base;
|
||||
unsigned int clk_extal_id;
|
||||
unsigned int clk_extalr_id;
|
||||
unsigned int clk_extal_usb_id;
|
||||
unsigned int pll0_div;
|
||||
const void *(*get_pll_config)(const u32 cpg_mode);
|
||||
};
|
||||
|
||||
/*
|
||||
* Definitions of CPG Core Clocks
|
||||
*
|
||||
* These include:
|
||||
* - Clock outputs exported to DT
|
||||
* - External input clocks
|
||||
* - Internal CPG clocks
|
||||
*/
|
||||
struct cpg_core_clk {
|
||||
/* Common */
|
||||
const char *name;
|
||||
unsigned int id;
|
||||
unsigned int type;
|
||||
/* Depending on type */
|
||||
unsigned int parent; /* Core Clocks only */
|
||||
unsigned int div;
|
||||
unsigned int mult;
|
||||
unsigned int offset;
|
||||
};
|
||||
|
||||
enum clk_types {
|
||||
/* Generic */
|
||||
CLK_TYPE_IN, /* External Clock Input */
|
||||
CLK_TYPE_FF, /* Fixed Factor Clock */
|
||||
CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
|
||||
CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
|
||||
CLK_TYPE_FR, /* Fixed Rate Clock */
|
||||
|
||||
/* Custom definitions start here */
|
||||
CLK_TYPE_CUSTOM,
|
||||
};
|
||||
|
||||
#define DEF_TYPE(_name, _id, _type...) \
|
||||
{ .name = _name, .id = _id, .type = _type }
|
||||
#define DEF_BASE(_name, _id, _type, _parent...) \
|
||||
DEF_TYPE(_name, _id, _type, .parent = _parent)
|
||||
|
||||
#define DEF_INPUT(_name, _id) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_IN)
|
||||
#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
|
||||
#define DEF_DIV6P1(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
|
||||
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
|
||||
#define DEF_RATE(_name, _id, _rate) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
|
||||
|
||||
/*
|
||||
* Definitions of Module Clocks
|
||||
*/
|
||||
struct mssr_mod_clk {
|
||||
const char *name;
|
||||
unsigned int id;
|
||||
unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
|
||||
};
|
||||
|
||||
/* Convert from sparse base-100 to packed index space */
|
||||
#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
|
||||
|
||||
#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
|
||||
|
||||
#define DEF_MOD(_name, _mod, _parent...) \
|
||||
{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
|
||||
|
||||
struct mstp_stop_table {
|
||||
u32 sdis;
|
||||
u32 sen;
|
||||
u32 rdis;
|
||||
u32 ren;
|
||||
};
|
||||
|
||||
#define TSTR0 0x04
|
||||
#define TSTR0_STR0 BIT(0)
|
||||
|
||||
bool renesas_clk_is_mod(struct clk *clk);
|
||||
int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
|
||||
const struct mssr_mod_clk **mssr);
|
||||
int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
|
||||
const struct cpg_core_clk **core);
|
||||
int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
|
||||
struct clk *parent);
|
||||
int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
|
||||
int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
|
||||
|
||||
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
|
||||
Reference in New Issue
Block a user